1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #define INCLUDE_JTAG_INTERFACE_H
38 static u8 output_value = 0x0;
39 static int dev_mem_fd;
40 static void *gpio_controller;
41 static volatile u8 *gpio_data_register;
42 static volatile u8 *gpio_data_direction_register;
44 /* low level command set
46 static int ep93xx_read(void);
47 static void ep93xx_write(int tck, int tms, int tdi);
48 static void ep93xx_reset(int trst, int srst);
50 static int ep93xx_speed(int speed);
51 static int ep93xx_register_commands(struct command_context_s *cmd_ctx);
52 static int ep93xx_init(void);
53 static int ep93xx_quit(void);
55 struct timespec ep93xx_zzzz;
57 jtag_interface_t ep93xx_interface =
61 .execute_queue = bitbang_execute_queue,
63 .speed = ep93xx_speed,
64 .register_commands = ep93xx_register_commands,
69 static bitbang_interface_t ep93xx_bitbang =
72 .write = ep93xx_write,
73 .reset = ep93xx_reset,
77 static int ep93xx_read(void)
79 return !!(*gpio_data_register & TDO_BIT);
82 static void ep93xx_write(int tck, int tms, int tdi)
85 output_value |= TCK_BIT;
87 output_value &= ~TCK_BIT;
90 output_value |= TMS_BIT;
92 output_value &= ~TMS_BIT;
95 output_value |= TDI_BIT;
97 output_value &= ~TDI_BIT;
99 *gpio_data_register = output_value;
100 nanosleep(&ep93xx_zzzz, NULL);
103 /* (1) assert or (0) deassert reset lines */
104 static void ep93xx_reset(int trst, int srst)
107 output_value |= TRST_BIT;
109 output_value &= ~TRST_BIT;
112 output_value |= SRST_BIT;
114 output_value &= ~SRST_BIT;
116 *gpio_data_register = output_value;
117 nanosleep(&ep93xx_zzzz, NULL);
120 static int ep93xx_speed(int speed)
126 static int ep93xx_register_commands(struct command_context_s *cmd_ctx)
132 static int set_gonk_mode(void)
137 syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
138 MAP_SHARED, dev_mem_fd, 0x80930000);
139 if (syscon == MAP_FAILED) {
141 return ERROR_JTAG_INIT_FAILED;
144 devicecfg = *((volatile int *)(syscon + 0x80));
145 *((volatile int *)(syscon + 0xc0)) = 0xaa;
146 *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
148 munmap(syscon, 4096);
153 static int ep93xx_init(void)
157 bitbang_interface = &ep93xx_bitbang;
159 ep93xx_zzzz.tv_sec = 0;
160 ep93xx_zzzz.tv_nsec = 10000000;
162 dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
163 if (dev_mem_fd < 0) {
165 return ERROR_JTAG_INIT_FAILED;
168 gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
169 MAP_SHARED, dev_mem_fd, 0x80840000);
170 if (gpio_controller == MAP_FAILED) {
173 return ERROR_JTAG_INIT_FAILED;
176 ret = set_gonk_mode();
177 if (ret != ERROR_OK) {
178 munmap(gpio_controller, 4096);
184 /* Use GPIO port A. */
185 gpio_data_register = gpio_controller + 0x00;
186 gpio_data_direction_register = gpio_controller + 0x10;
189 /* Use GPIO port B. */
190 gpio_data_register = gpio_controller + 0x04;
191 gpio_data_direction_register = gpio_controller + 0x14;
193 /* Use GPIO port C. */
194 gpio_data_register = gpio_controller + 0x08;
195 gpio_data_direction_register = gpio_controller + 0x18;
197 /* Use GPIO port D. */
198 gpio_data_register = gpio_controller + 0x0c;
199 gpio_data_direction_register = gpio_controller + 0x1c;
202 /* Use GPIO port C. */
203 gpio_data_register = gpio_controller + 0x08;
204 gpio_data_direction_register = gpio_controller + 0x18;
206 LOG_INFO("gpio_data_register = %p\n", gpio_data_register);
207 LOG_INFO("gpio_data_direction_reg = %p\n", gpio_data_direction_register);
209 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
210 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
211 * TMS/TRST/SRST high.
213 output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
214 *gpio_data_register = output_value;
215 nanosleep(&ep93xx_zzzz, NULL);
218 * Configure the direction register. 1 = output, 0 = input.
220 *gpio_data_direction_register =
221 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
223 nanosleep(&ep93xx_zzzz, NULL);
227 static int ep93xx_quit(void)