1 /***************************************************************************
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2 * Copyright (C) 2005 by Dominic Rath *
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3 * Dominic.Rath@gmx.de *
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5 * This program is free software; you can redistribute it and/or modify *
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6 * it under the terms of the GNU General Public License as published by *
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7 * the Free Software Foundation; either version 2 of the License, or *
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8 * (at your option) any later version. *
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10 * This program is distributed in the hope that it will be useful, *
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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13 * GNU General Public License for more details. *
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15 * You should have received a copy of the GNU General Public License *
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16 * along with this program; if not, write to the *
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17 * Free Software Foundation, Inc., *
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18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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19 ***************************************************************************/
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20 #ifdef HAVE_CONFIG_H
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26 #include "bitbang.h"
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36 /* system includes */
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40 #include <sys/mman.h>
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44 static u8 output_value = 0x0;
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45 static int dev_mem_fd;
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46 static void *gpio_controller;
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47 static volatile u8 *gpio_data_register;
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48 static volatile u8 *gpio_data_direction_register;
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50 /* low level command set
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52 int ep93xx_read(void);
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53 void ep93xx_write(int tck, int tms, int tdi);
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54 void ep93xx_reset(int trst, int srst);
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56 int ep93xx_speed(int speed);
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57 int ep93xx_register_commands(struct command_context_s *cmd_ctx);
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58 int ep93xx_init(void);
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59 int ep93xx_quit(void);
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61 struct timespec ep93xx_zzzz;
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63 jtag_interface_t ep93xx_interface =
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67 .execute_queue = bitbang_execute_queue,
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69 .speed = ep93xx_speed,
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70 .register_commands = ep93xx_register_commands,
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71 .init = ep93xx_init,
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72 .quit = ep93xx_quit,
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75 bitbang_interface_t ep93xx_bitbang =
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77 .read = ep93xx_read,
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78 .write = ep93xx_write,
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79 .reset = ep93xx_reset,
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83 int ep93xx_read(void)
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85 return !!(*gpio_data_register & TDO_BIT);
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88 void ep93xx_write(int tck, int tms, int tdi)
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91 output_value |= TCK_BIT;
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93 output_value &= TCK_BIT;
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96 output_value |= TMS_BIT;
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98 output_value &= TMS_BIT;
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101 output_value |= TDI_BIT;
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103 output_value &= TDI_BIT;
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105 *gpio_data_register = output_value;
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106 nanosleep(ep93xx_zzzz);
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109 /* (1) assert or (0) deassert reset lines */
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110 void ep93xx_reset(int trst, int srst)
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113 output_value |= TRST_BIT;
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114 else if (trst == 1)
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115 output_value &= TRST_BIT;
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118 output_value |= SRST_BIT;
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119 else if (srst == 1)
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120 output_value &= SRST_BIT;
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122 *gpio_data_register = output_value;
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123 nanosleep(ep93xx_zzzz);
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126 int ep93xx_speed(int speed)
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132 int ep93xx_register_commands(struct command_context_s *cmd_ctx)
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138 static int set_gonk_mode(void)
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143 syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
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144 MAP_SHARED, dev_mem_fd, 0x80930000);
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145 if (syscon == MAP_FAILED) {
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147 return ERROR_JTAG_INIT_FAILED;
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150 devicecfg = *((volatile int *)(syscon + 0x80));
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151 *((volatile int *)(syscon + 0xc0)) = 0xaa;
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152 *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
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154 munmap(syscon, 4096);
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159 int ep93xx_init(void)
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163 bitbang_interface = &ep93xx_bitbang;
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165 ep93xx_zzzz.tv_sec = 0;
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166 ep93xx_zzzz.tv_nsec = 10000000;
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168 dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
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169 if (dev_mem_fd < 0) {
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171 return ERROR_JTAG_INIT_FAILED;
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174 gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
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175 MAP_SHARED, dev_mem_fd, 0x80840000);
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176 if (gpio_controller == MAP_FAILED) {
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179 return ERROR_JTAG_INIT_FAILED;
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182 ret = set_gonk_mode();
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183 if (ret != ERROR_OK) {
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184 munmap(gpio_controller, 4096);
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190 /* Use GPIO port A. */
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191 gpio_data_register = gpio_controller + 0x00;
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192 gpio_data_direction_register = gpio_controller + 0x10;
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195 /* Use GPIO port B. */
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196 gpio_data_register = gpio_controller + 0x04;
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197 gpio_data_direction_register = gpio_controller + 0x14;
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199 /* Use GPIO port C. */
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200 gpio_data_register = gpio_controller + 0x08;
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201 gpio_data_direction_register = gpio_controller + 0x18;
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203 /* Use GPIO port D. */
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204 gpio_data_register = gpio_controller + 0x0c;
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205 gpio_data_direction_register = gpio_controller + 0x1c;
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208 /* Use GPIO port C. */
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209 gpio_data_register = gpio_controller + 0x08;
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210 gpio_data_direction_register = gpio_controller + 0x18;
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212 INFO("gpio_data_register = %p\n", gpio_data_register);
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213 INFO("gpio_data_direction_reg = %p\n", gpio_data_direction_register);
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215 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
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216 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
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217 * TMS/TRST/SRST high.
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219 output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
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220 *gpio_data_register = output_value;
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221 nanosleep(ep93xx_zzzz);
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224 * Configure the direction register. 1 = output, 0 = input.
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226 *gpio_data_direction_register =
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227 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
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229 nanosleep(ep93xx_zzzz);
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233 int ep93xx_quit(void)
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