flash/nor/at91samd: Use 32-bit register writes for ST-Link compat
[fw/openocd] / src / jtag / drivers / rlink_ep1_cmd.h
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 /***************************************************************************
4  *   Copyright (C) 2008 Lou Deluxe                                         *
5  *   lou.openocd012@fixit.nospammail.net                                   *
6  ***************************************************************************/
7
8 #ifndef OPENOCD_JTAG_DRIVERS_RLINK_EP1_CMD_H
9 #define OPENOCD_JTAG_DRIVERS_RLINK_EP1_CMD_H
10
11 /*
12  * Command opcodes that can be sent over endpoint 1.
13  * This codifies information provided by Rob Brown <rob@cobbleware.com>.
14  * The buffer can contain several of these, but only one which returns data.
15  * Some of these opcodes have arguments, which follow immediately.
16  * If shorter than the packet size, trailing positions should be zero-filled.
17  */
18
19 /* LED update enables:
20  *  When enabled, each LED is updated automatically.
21  *  When not enabled, each LED can be controlled manually with EP1_CMD_SET_PORTD_LEDS.
22  */
23 #define EP1_CMD_LEDUE_BOTH                              (0x05)
24 /* EP1_CMD_LEDUE_NONE has the side effect of turning the LEDs on */
25 #define EP1_CMD_LEDUE_NONE                              (0x06)
26 #define EP1_CMD_LEDUE_ERROR                             (0x17)
27 #define EP1_CMD_LEDUE_BUSY                              (0x18)
28
29 #define EP1_CMD_DTC_STOP                                (0x0b)
30 #define EP1_CMD_DTC_LOAD                                (0x0c)
31 #define EP1_CMD_DTC_CALL                                (0x0d)
32 #define EP1_CMD_SET_UPLOAD                              (0x0f)
33 #define EP1_CMD_SET_DOWNLOAD                    (0x10)
34 #define EP1_CMD_DTC_WAIT                                (0x12)
35 #define EP1_CMD_DTC_GET_STATUS                  (0x15)
36 /* a quick way to just read back one byte */
37 #define EP1_CMD_DTC_GET_CACHED_STATUS   (0x16)
38
39 /* Writes upper 2 bits (SHDN and SEL) of port D with argument */
40 #define EP1_CMD_SET_PORTD_VPP                   (0x19)
41 /* Writes lower 2 bits (BUSY and ERROR) of port D with argument */
42 #define EP1_CMD_SET_PORTD_LEDS                  (0x1a)
43
44 #define EP1_CMD_MEMORY_READ                             (0x28)
45 #define EP1_CMD_MEMORY_WRITE                    (0x29)
46 #define EP1_CMD_GET_FWREV                               (0xfe)
47 #define EP1_CMD_GET_SERIAL                              (0xff)
48
49 #endif /* OPENOCD_JTAG_DRIVERS_RLINK_EP1_CMD_H */