1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
23 #include <jtag/interface.h>
36 static uint8_t output_value;
37 static int dev_mem_fd;
38 static void *gpio_controller;
39 static volatile uint8_t *gpio_data_register;
40 static volatile uint8_t *gpio_data_direction_register;
42 /* low level command set
44 static bb_value_t ep93xx_read(void);
45 static int ep93xx_write(int tck, int tms, int tdi);
46 static int ep93xx_reset(int trst, int srst);
48 static int ep93xx_init(void);
49 static int ep93xx_quit(void);
51 struct timespec ep93xx_zzzz;
53 struct jtag_interface ep93xx_interface = {
56 .supported = DEBUG_CAP_TMS_SEQ,
57 .execute_queue = bitbang_execute_queue,
58 .transports = jtag_only,
62 .reset = ep93xx_reset,
65 static struct bitbang_interface ep93xx_bitbang = {
67 .write = ep93xx_write,
71 static bb_value_t ep93xx_read(void)
73 return (*gpio_data_register & TDO_BIT) ? BB_HIGH : BB_LOW;
76 static int ep93xx_write(int tck, int tms, int tdi)
79 output_value |= TCK_BIT;
81 output_value &= ~TCK_BIT;
84 output_value |= TMS_BIT;
86 output_value &= ~TMS_BIT;
89 output_value |= TDI_BIT;
91 output_value &= ~TDI_BIT;
93 *gpio_data_register = output_value;
94 nanosleep(&ep93xx_zzzz, NULL);
99 /* (1) assert or (0) deassert reset lines */
100 static int ep93xx_reset(int trst, int srst)
103 output_value |= TRST_BIT;
105 output_value &= ~TRST_BIT;
108 output_value |= SRST_BIT;
110 output_value &= ~SRST_BIT;
112 *gpio_data_register = output_value;
113 nanosleep(&ep93xx_zzzz, NULL);
118 static int set_gonk_mode(void)
123 syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
124 MAP_SHARED, dev_mem_fd, 0x80930000);
125 if (syscon == MAP_FAILED) {
127 return ERROR_JTAG_INIT_FAILED;
130 devicecfg = *((volatile int *)(syscon + 0x80));
131 *((volatile int *)(syscon + 0xc0)) = 0xaa;
132 *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
134 munmap(syscon, 4096);
139 static int ep93xx_init(void)
143 bitbang_interface = &ep93xx_bitbang;
145 ep93xx_zzzz.tv_sec = 0;
146 ep93xx_zzzz.tv_nsec = 10000000;
148 dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
149 if (dev_mem_fd < 0) {
151 return ERROR_JTAG_INIT_FAILED;
154 gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
155 MAP_SHARED, dev_mem_fd, 0x80840000);
156 if (gpio_controller == MAP_FAILED) {
159 return ERROR_JTAG_INIT_FAILED;
162 ret = set_gonk_mode();
163 if (ret != ERROR_OK) {
164 munmap(gpio_controller, 4096);
170 /* Use GPIO port A. */
171 gpio_data_register = gpio_controller + 0x00;
172 gpio_data_direction_register = gpio_controller + 0x10;
175 /* Use GPIO port B. */
176 gpio_data_register = gpio_controller + 0x04;
177 gpio_data_direction_register = gpio_controller + 0x14;
179 /* Use GPIO port C. */
180 gpio_data_register = gpio_controller + 0x08;
181 gpio_data_direction_register = gpio_controller + 0x18;
183 /* Use GPIO port D. */
184 gpio_data_register = gpio_controller + 0x0c;
185 gpio_data_direction_register = gpio_controller + 0x1c;
188 /* Use GPIO port C. */
189 gpio_data_register = gpio_controller + 0x08;
190 gpio_data_direction_register = gpio_controller + 0x18;
192 LOG_INFO("gpio_data_register = %p", gpio_data_register);
193 LOG_INFO("gpio_data_direction_reg = %p", gpio_data_direction_register);
195 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
196 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
197 * TMS/TRST/SRST high.
199 output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
200 *gpio_data_register = output_value;
201 nanosleep(&ep93xx_zzzz, NULL);
204 * Configure the direction register. 1 = output, 0 = input.
206 *gpio_data_direction_register =
207 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
209 nanosleep(&ep93xx_zzzz, NULL);
213 static int ep93xx_quit(void)