1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
24 /* 2014-12: Addition of the SWD protocol support is based on the initial work
25 * by Paul Fertser and modifications by Jean-Christian de Rivaz. */
32 #include <jtag/interface.h>
33 #include <jtag/commands.h>
35 /* YUK! - but this is currently a global.... */
36 extern struct jtag_interface *jtag_interface;
39 * Function bitbang_stableclocks
40 * issues a number of clock cycles while staying in a stable state.
41 * Because the TMS value required to stay in the RESET state is a 1, whereas
42 * the TMS value required to stay in any of the other stable states is a 0,
43 * this function checks the current stable state to decide on the value of TMS
46 static void bitbang_stableclocks(int num_cycles);
48 struct bitbang_interface *bitbang_interface;
50 /* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
52 * Set this to 1 and str912 reset halt will fail.
54 * If someone can submit a patch with an explanation it will be greatly
55 * appreciated, but as far as I can tell (ØH) DCLK is generated upon
56 * clk = 0 in TAP_IDLE. Good luck deducing that from the ARM documentation!
57 * The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE
58 * state". With hardware there is no such thing as *while* in a state. There
59 * are only edges. So clk => 0 is in fact a very subtle state transition that
60 * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#&
62 * For "reset halt" the last thing that happens before srst is asserted
63 * is that the breakpoint is set up. If DCLK is not wiggled one last
64 * time before the reset, then the breakpoint is not set up and
65 * "reset halt" will fail to halt.
68 #define CLOCK_IDLE() 0
70 /* The bitbang driver leaves the TCK 0 when in idle */
71 static void bitbang_end_state(tap_state_t state)
73 if (tap_is_state_stable(state))
74 tap_set_end_state(state);
76 LOG_ERROR("BUG: %i is not a valid end state", state);
81 static void bitbang_state_move(int skip)
84 uint8_t tms_scan = tap_get_tms_path(tap_get_state(), tap_get_end_state());
85 int tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
87 for (i = skip; i < tms_count; i++) {
88 tms = (tms_scan >> i) & 1;
89 bitbang_interface->write(0, tms, 0);
90 bitbang_interface->write(1, tms, 0);
92 bitbang_interface->write(CLOCK_IDLE(), tms, 0);
94 tap_set_state(tap_get_end_state());
98 * Clock a bunch of TMS (or SWDIO) transitions, to change the JTAG
99 * (or SWD) state machine.
101 static int bitbang_execute_tms(struct jtag_command *cmd)
103 unsigned num_bits = cmd->cmd.tms->num_bits;
104 const uint8_t *bits = cmd->cmd.tms->bits;
106 DEBUG_JTAG_IO("TMS: %d bits", num_bits);
109 for (unsigned i = 0; i < num_bits; i++) {
110 tms = ((bits[i/8] >> (i % 8)) & 1);
111 bitbang_interface->write(0, tms, 0);
112 bitbang_interface->write(1, tms, 0);
114 bitbang_interface->write(CLOCK_IDLE(), tms, 0);
119 static void bitbang_path_move(struct pathmove_command *cmd)
121 int num_states = cmd->num_states;
127 if (tap_state_transition(tap_get_state(), false) == cmd->path[state_count])
129 else if (tap_state_transition(tap_get_state(), true) == cmd->path[state_count])
132 LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition",
133 tap_state_name(tap_get_state()),
134 tap_state_name(cmd->path[state_count]));
138 bitbang_interface->write(0, tms, 0);
139 bitbang_interface->write(1, tms, 0);
141 tap_set_state(cmd->path[state_count]);
146 bitbang_interface->write(CLOCK_IDLE(), tms, 0);
148 tap_set_end_state(tap_get_state());
151 static void bitbang_runtest(int num_cycles)
155 tap_state_t saved_end_state = tap_get_end_state();
157 /* only do a state_move when we're not already in IDLE */
158 if (tap_get_state() != TAP_IDLE) {
159 bitbang_end_state(TAP_IDLE);
160 bitbang_state_move(0);
163 /* execute num_cycles */
164 for (i = 0; i < num_cycles; i++) {
165 bitbang_interface->write(0, 0, 0);
166 bitbang_interface->write(1, 0, 0);
168 bitbang_interface->write(CLOCK_IDLE(), 0, 0);
170 /* finish in end_state */
171 bitbang_end_state(saved_end_state);
172 if (tap_get_state() != tap_get_end_state())
173 bitbang_state_move(0);
176 static void bitbang_stableclocks(int num_cycles)
178 int tms = (tap_get_state() == TAP_RESET ? 1 : 0);
181 /* send num_cycles clocks onto the cable */
182 for (i = 0; i < num_cycles; i++) {
183 bitbang_interface->write(1, tms, 0);
184 bitbang_interface->write(0, tms, 0);
188 static void bitbang_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int scan_size)
190 tap_state_t saved_end_state = tap_get_end_state();
194 (tap_get_state() == TAP_DRSHIFT)) ||
195 (ir_scan && (tap_get_state() == TAP_IRSHIFT)))) {
197 bitbang_end_state(TAP_IRSHIFT);
199 bitbang_end_state(TAP_DRSHIFT);
201 bitbang_state_move(0);
202 bitbang_end_state(saved_end_state);
205 for (bit_cnt = 0; bit_cnt < scan_size; bit_cnt++) {
207 int tms = (bit_cnt == scan_size-1) ? 1 : 0;
209 int bytec = bit_cnt/8;
210 int bcval = 1 << (bit_cnt % 8);
212 /* if we're just reading the scan, but don't care about the output
213 * default to outputting 'low', this also makes valgrind traces more readable,
214 * as it removes the dependency on an uninitialised value
217 if ((type != SCAN_IN) && (buffer[bytec] & bcval))
220 bitbang_interface->write(0, tms, tdi);
222 if (type != SCAN_OUT)
223 val = bitbang_interface->read();
225 bitbang_interface->write(1, tms, tdi);
227 if (type != SCAN_OUT) {
229 buffer[bytec] |= bcval;
231 buffer[bytec] &= ~bcval;
235 if (tap_get_state() != tap_get_end_state()) {
236 /* we *KNOW* the above loop transitioned out of
237 * the shift state, so we skip the first state
238 * and move directly to the end state.
240 bitbang_state_move(1);
244 int bitbang_execute_queue(void)
246 struct jtag_command *cmd = jtag_command_queue; /* currently processed command */
252 if (!bitbang_interface) {
253 LOG_ERROR("BUG: Bitbang interface called, but not yet initialized");
257 /* return ERROR_OK, unless a jtag_read_buffer returns a failed check
258 * that wasn't handled by a caller-provided error handler
262 if (bitbang_interface->blink)
263 bitbang_interface->blink(1);
268 #ifdef _DEBUG_JTAG_IO_
269 LOG_DEBUG("reset trst: %i srst %i",
270 cmd->cmd.reset->trst,
271 cmd->cmd.reset->srst);
273 if ((cmd->cmd.reset->trst == 1) ||
274 (cmd->cmd.reset->srst && (jtag_get_reset_config() & RESET_SRST_PULLS_TRST)))
275 tap_set_state(TAP_RESET);
276 bitbang_interface->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
279 #ifdef _DEBUG_JTAG_IO_
280 LOG_DEBUG("runtest %i cycles, end in %s",
281 cmd->cmd.runtest->num_cycles,
282 tap_state_name(cmd->cmd.runtest->end_state));
284 bitbang_end_state(cmd->cmd.runtest->end_state);
285 bitbang_runtest(cmd->cmd.runtest->num_cycles);
288 case JTAG_STABLECLOCKS:
289 /* this is only allowed while in a stable state. A check for a stable
290 * state was done in jtag_add_clocks()
292 bitbang_stableclocks(cmd->cmd.stableclocks->num_cycles);
296 #ifdef _DEBUG_JTAG_IO_
297 LOG_DEBUG("statemove end in %s",
298 tap_state_name(cmd->cmd.statemove->end_state));
300 bitbang_end_state(cmd->cmd.statemove->end_state);
301 bitbang_state_move(0);
304 #ifdef _DEBUG_JTAG_IO_
305 LOG_DEBUG("pathmove: %i states, end in %s",
306 cmd->cmd.pathmove->num_states,
307 tap_state_name(cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]));
309 bitbang_path_move(cmd->cmd.pathmove);
312 #ifdef _DEBUG_JTAG_IO_
313 LOG_DEBUG("%s scan end in %s",
314 (cmd->cmd.scan->ir_scan) ? "IR" : "DR",
315 tap_state_name(cmd->cmd.scan->end_state));
317 bitbang_end_state(cmd->cmd.scan->end_state);
318 scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
319 type = jtag_scan_type(cmd->cmd.scan);
320 bitbang_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
321 if (jtag_read_buffer(buffer, cmd->cmd.scan) != ERROR_OK)
322 retval = ERROR_JTAG_QUEUE_FAILED;
327 #ifdef _DEBUG_JTAG_IO_
328 LOG_DEBUG("sleep %" PRIi32, cmd->cmd.sleep->us);
330 jtag_sleep(cmd->cmd.sleep->us);
333 retval = bitbang_execute_tms(cmd);
336 LOG_ERROR("BUG: unknown JTAG command type encountered");
341 if (bitbang_interface->blink)
342 bitbang_interface->blink(0);
349 static int queued_retval;
351 static int bitbang_swd_init(void)
353 LOG_DEBUG("bitbang_swd_init");
358 static void bitbang_exchange(bool rnw, uint8_t buf[], unsigned int offset, unsigned int bit_cnt)
360 LOG_DEBUG("bitbang_exchange");
363 for (unsigned int i = offset; i < bit_cnt + offset; i++) {
365 int bcval = 1 << (i % 8);
366 tdi = !rnw && (buf[bytec] & bcval);
368 bitbang_interface->write(0, 0, tdi);
371 if (bitbang_interface->swdio_read())
374 buf[bytec] &= ~bcval;
377 bitbang_interface->write(1, 0, tdi);
381 int bitbang_swd_switch_seq(struct adiv5_dap *dap, enum swd_special_seq seq)
383 LOG_DEBUG("bitbang_swd_switch_seq");
387 LOG_DEBUG("SWD line reset");
388 bitbang_exchange(false, (uint8_t *)swd_seq_line_reset, 0, swd_seq_line_reset_len);
391 LOG_DEBUG("JTAG-to-SWD");
392 bitbang_exchange(false, (uint8_t *)swd_seq_jtag_to_swd, 0, swd_seq_jtag_to_swd_len);
395 LOG_DEBUG("SWD-to-JTAG");
396 bitbang_exchange(false, (uint8_t *)swd_seq_swd_to_jtag, 0, swd_seq_swd_to_jtag_len);
399 LOG_ERROR("Sequence %d not supported", seq);
406 void bitbang_switch_to_swd(void)
408 LOG_DEBUG("bitbang_switch_to_swd");
409 bitbang_exchange(false, (uint8_t *)swd_seq_jtag_to_swd, 0, swd_seq_jtag_to_swd_len);
412 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
414 const struct swd_driver *swd = jtag_interface->swd;
417 swd->write_reg(dap, swd_cmd(false, false, DP_ABORT),
418 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
421 static void bitbang_swd_read_reg(struct adiv5_dap *dap, uint8_t cmd, uint32_t *value)
423 LOG_DEBUG("bitbang_swd_read_reg");
424 assert(cmd & SWD_CMD_RnW);
426 if (queued_retval != ERROR_OK) {
427 LOG_DEBUG("Skip bitbang_swd_read_reg because queued_retval=%d", queued_retval);
432 uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
434 cmd |= SWD_CMD_START | (1 << 7);
435 bitbang_exchange(false, &cmd, 0, 8);
437 bitbang_interface->swdio_drive(false);
438 bitbang_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3 + 32 + 1 + 1);
439 bitbang_interface->swdio_drive(true);
441 int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
442 uint32_t data = buf_get_u32(trn_ack_data_parity_trn, 1 + 3, 32);
443 int parity = buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 32, 1);
445 LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
446 ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
447 cmd & SWD_CMD_APnDP ? "AP" : "DP",
448 cmd & SWD_CMD_RnW ? "read" : "write",
449 (cmd & SWD_CMD_A32) >> 1,
454 if (parity != parity_u32(data)) {
455 LOG_DEBUG("Wrong parity detected");
456 queued_retval = ERROR_FAIL;
461 if (cmd & SWD_CMD_APnDP)
462 bitbang_exchange(true, NULL, 0, dap->memaccess_tck);
465 LOG_DEBUG("SWD_ACK_WAIT");
466 swd_clear_sticky_errors(dap);
469 LOG_DEBUG("SWD_ACK_FAULT");
473 LOG_DEBUG("No valid acknowledge: ack=%d", ack);
480 static void bitbang_swd_write_reg(struct adiv5_dap *dap, uint8_t cmd, uint32_t value)
482 LOG_DEBUG("bitbang_swd_write_reg");
483 assert(!(cmd & SWD_CMD_RnW));
485 if (queued_retval != ERROR_OK) {
486 LOG_DEBUG("Skip bitbang_swd_write_reg because queued_retval=%d", queued_retval);
491 uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
492 buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32, value);
493 buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1 + 32, 1, parity_u32(value));
495 cmd |= SWD_CMD_START | (1 << 7);
496 bitbang_exchange(false, &cmd, 0, 8);
498 bitbang_interface->swdio_drive(false);
499 bitbang_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3 + 1);
500 bitbang_interface->swdio_drive(true);
501 bitbang_exchange(false, trn_ack_data_parity_trn, 1 + 3 + 1, 32 + 1);
503 int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
504 LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
505 ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
506 cmd & SWD_CMD_APnDP ? "AP" : "DP",
507 cmd & SWD_CMD_RnW ? "read" : "write",
508 (cmd & SWD_CMD_A32) >> 1,
509 buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32));
513 if (cmd & SWD_CMD_APnDP)
514 bitbang_exchange(true, NULL, 0, dap->memaccess_tck);
517 LOG_DEBUG("SWD_ACK_WAIT");
518 swd_clear_sticky_errors(dap);
521 LOG_DEBUG("SWD_ACK_FAULT");
525 LOG_DEBUG("No valid acknowledge: ack=%d", ack);
532 static int bitbang_swd_run_queue(struct adiv5_dap *dap)
534 LOG_DEBUG("bitbang_swd_run_queue");
535 /* A transaction must be followed by another transaction or at least 8 idle cycles to
536 * ensure that data is clocked through the AP. */
537 bitbang_exchange(true, NULL, 0, 8);
539 int retval = queued_retval;
540 queued_retval = ERROR_OK;
541 LOG_DEBUG("SWD queue return value: %02x", retval);
545 const struct swd_driver bitbang_swd = {
546 .init = bitbang_swd_init,
547 .switch_seq = bitbang_swd_switch_seq,
548 .read_reg = bitbang_swd_read_reg,
549 .write_reg = bitbang_swd_write_reg,
550 .run = bitbang_swd_run_queue,