1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
9 ***************************************************************************/
11 /* 2014-12: Addition of the SWD protocol support is based on the initial work
12 * by Paul Fertser and modifications by Jean-Christian de Rivaz. */
19 #include <jtag/interface.h>
20 #include <jtag/commands.h>
23 * Function bitbang_stableclocks
24 * issues a number of clock cycles while staying in a stable state.
25 * Because the TMS value required to stay in the RESET state is a 1, whereas
26 * the TMS value required to stay in any of the other stable states is a 0,
27 * this function checks the current stable state to decide on the value of TMS
30 static int bitbang_stableclocks(int num_cycles);
32 static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk);
34 struct bitbang_interface *bitbang_interface;
36 /* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
38 * Set this to 1 and str912 reset halt will fail.
40 * If someone can submit a patch with an explanation it will be greatly
41 * appreciated, but as far as I can tell (ØH) DCLK is generated upon
42 * clk = 0 in TAP_IDLE. Good luck deducing that from the ARM documentation!
43 * The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE
44 * state". With hardware there is no such thing as *while* in a state. There
45 * are only edges. So clk => 0 is in fact a very subtle state transition that
46 * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#&
48 * For "reset halt" the last thing that happens before srst is asserted
49 * is that the breakpoint is set up. If DCLK is not wiggled one last
50 * time before the reset, then the breakpoint is not set up and
51 * "reset halt" will fail to halt.
54 #define CLOCK_IDLE() 0
56 /* The bitbang driver leaves the TCK 0 when in idle */
57 static void bitbang_end_state(tap_state_t state)
59 assert(tap_is_state_stable(state));
60 tap_set_end_state(state);
63 static int bitbang_state_move(int skip)
66 uint8_t tms_scan = tap_get_tms_path(tap_get_state(), tap_get_end_state());
67 int tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
69 for (i = skip; i < tms_count; i++) {
70 tms = (tms_scan >> i) & 1;
71 if (bitbang_interface->write(0, tms, 0) != ERROR_OK)
73 if (bitbang_interface->write(1, tms, 0) != ERROR_OK)
76 if (bitbang_interface->write(CLOCK_IDLE(), tms, 0) != ERROR_OK)
79 tap_set_state(tap_get_end_state());
84 * Clock a bunch of TMS (or SWDIO) transitions, to change the JTAG
85 * (or SWD) state machine.
87 static int bitbang_execute_tms(struct jtag_command *cmd)
89 unsigned num_bits = cmd->cmd.tms->num_bits;
90 const uint8_t *bits = cmd->cmd.tms->bits;
92 LOG_DEBUG_IO("TMS: %d bits", num_bits);
95 for (unsigned i = 0; i < num_bits; i++) {
96 tms = ((bits[i/8] >> (i % 8)) & 1);
97 if (bitbang_interface->write(0, tms, 0) != ERROR_OK)
99 if (bitbang_interface->write(1, tms, 0) != ERROR_OK)
102 if (bitbang_interface->write(CLOCK_IDLE(), tms, 0) != ERROR_OK)
108 static int bitbang_path_move(struct pathmove_command *cmd)
110 int num_states = cmd->num_states;
116 if (tap_state_transition(tap_get_state(), false) == cmd->path[state_count])
118 else if (tap_state_transition(tap_get_state(), true) == cmd->path[state_count])
121 LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition",
122 tap_state_name(tap_get_state()),
123 tap_state_name(cmd->path[state_count]));
127 if (bitbang_interface->write(0, tms, 0) != ERROR_OK)
129 if (bitbang_interface->write(1, tms, 0) != ERROR_OK)
132 tap_set_state(cmd->path[state_count]);
137 if (bitbang_interface->write(CLOCK_IDLE(), tms, 0) != ERROR_OK)
140 tap_set_end_state(tap_get_state());
144 static int bitbang_runtest(int num_cycles)
148 tap_state_t saved_end_state = tap_get_end_state();
150 /* only do a state_move when we're not already in IDLE */
151 if (tap_get_state() != TAP_IDLE) {
152 bitbang_end_state(TAP_IDLE);
153 if (bitbang_state_move(0) != ERROR_OK)
157 /* execute num_cycles */
158 for (i = 0; i < num_cycles; i++) {
159 if (bitbang_interface->write(0, 0, 0) != ERROR_OK)
161 if (bitbang_interface->write(1, 0, 0) != ERROR_OK)
164 if (bitbang_interface->write(CLOCK_IDLE(), 0, 0) != ERROR_OK)
167 /* finish in end_state */
168 bitbang_end_state(saved_end_state);
169 if (tap_get_state() != tap_get_end_state())
170 if (bitbang_state_move(0) != ERROR_OK)
176 static int bitbang_stableclocks(int num_cycles)
178 int tms = (tap_get_state() == TAP_RESET ? 1 : 0);
181 /* send num_cycles clocks onto the cable */
182 for (i = 0; i < num_cycles; i++) {
183 if (bitbang_interface->write(1, tms, 0) != ERROR_OK)
185 if (bitbang_interface->write(0, tms, 0) != ERROR_OK)
192 static int bitbang_scan(bool ir_scan, enum scan_type type, uint8_t *buffer,
195 tap_state_t saved_end_state = tap_get_end_state();
199 (tap_get_state() == TAP_DRSHIFT)) ||
200 (ir_scan && (tap_get_state() == TAP_IRSHIFT)))) {
202 bitbang_end_state(TAP_IRSHIFT);
204 bitbang_end_state(TAP_DRSHIFT);
206 if (bitbang_state_move(0) != ERROR_OK)
208 bitbang_end_state(saved_end_state);
212 for (bit_cnt = 0; bit_cnt < scan_size; bit_cnt++) {
213 int tms = (bit_cnt == scan_size-1) ? 1 : 0;
215 int bytec = bit_cnt/8;
216 int bcval = 1 << (bit_cnt % 8);
218 /* if we're just reading the scan, but don't care about the output
219 * default to outputting 'low', this also makes valgrind traces more readable,
220 * as it removes the dependency on an uninitialised value
223 if ((type != SCAN_IN) && (buffer[bytec] & bcval))
226 if (bitbang_interface->write(0, tms, tdi) != ERROR_OK)
229 if (type != SCAN_OUT) {
230 if (bitbang_interface->buf_size) {
231 if (bitbang_interface->sample() != ERROR_OK)
235 switch (bitbang_interface->read()) {
237 buffer[bytec] &= ~bcval;
240 buffer[bytec] |= bcval;
248 if (bitbang_interface->write(1, tms, tdi) != ERROR_OK)
251 if (type != SCAN_OUT && bitbang_interface->buf_size &&
252 (buffered == bitbang_interface->buf_size ||
253 bit_cnt == scan_size - 1)) {
254 for (unsigned i = bit_cnt + 1 - buffered; i <= bit_cnt; i++) {
255 switch (bitbang_interface->read_sample()) {
257 buffer[i/8] &= ~(1 << (i % 8));
260 buffer[i/8] |= 1 << (i % 8);
270 if (tap_get_state() != tap_get_end_state()) {
271 /* we *KNOW* the above loop transitioned out of
272 * the shift state, so we skip the first state
273 * and move directly to the end state.
275 if (bitbang_state_move(1) != ERROR_OK)
281 int bitbang_execute_queue(void)
283 struct jtag_command *cmd = jtag_command_queue; /* currently processed command */
289 if (!bitbang_interface) {
290 LOG_ERROR("BUG: Bitbang interface called, but not yet initialized");
294 /* return ERROR_OK, unless a jtag_read_buffer returns a failed check
295 * that wasn't handled by a caller-provided error handler
299 if (bitbang_interface->blink) {
300 if (bitbang_interface->blink(1) != ERROR_OK)
307 LOG_DEBUG_IO("runtest %i cycles, end in %s",
308 cmd->cmd.runtest->num_cycles,
309 tap_state_name(cmd->cmd.runtest->end_state));
310 bitbang_end_state(cmd->cmd.runtest->end_state);
311 if (bitbang_runtest(cmd->cmd.runtest->num_cycles) != ERROR_OK)
315 case JTAG_STABLECLOCKS:
316 /* this is only allowed while in a stable state. A check for a stable
317 * state was done in jtag_add_clocks()
319 if (bitbang_stableclocks(cmd->cmd.stableclocks->num_cycles) != ERROR_OK)
324 LOG_DEBUG_IO("statemove end in %s",
325 tap_state_name(cmd->cmd.statemove->end_state));
326 bitbang_end_state(cmd->cmd.statemove->end_state);
327 if (bitbang_state_move(0) != ERROR_OK)
331 LOG_DEBUG_IO("pathmove: %i states, end in %s",
332 cmd->cmd.pathmove->num_states,
333 tap_state_name(cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]));
334 if (bitbang_path_move(cmd->cmd.pathmove) != ERROR_OK)
338 bitbang_end_state(cmd->cmd.scan->end_state);
339 scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
340 LOG_DEBUG_IO("%s scan %d bits; end in %s",
341 (cmd->cmd.scan->ir_scan) ? "IR" : "DR",
343 tap_state_name(cmd->cmd.scan->end_state));
344 type = jtag_scan_type(cmd->cmd.scan);
345 if (bitbang_scan(cmd->cmd.scan->ir_scan, type, buffer,
346 scan_size) != ERROR_OK)
348 if (jtag_read_buffer(buffer, cmd->cmd.scan) != ERROR_OK)
349 retval = ERROR_JTAG_QUEUE_FAILED;
353 LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
354 jtag_sleep(cmd->cmd.sleep->us);
357 retval = bitbang_execute_tms(cmd);
360 LOG_ERROR("BUG: unknown JTAG command type encountered");
365 if (bitbang_interface->blink) {
366 if (bitbang_interface->blink(0) != ERROR_OK)
373 static int queued_retval;
375 static int bitbang_swd_init(void)
377 LOG_DEBUG("bitbang_swd_init");
381 static void bitbang_swd_exchange(bool rnw, uint8_t buf[], unsigned int offset, unsigned int bit_cnt)
383 LOG_DEBUG("bitbang_swd_exchange");
385 if (bitbang_interface->blink) {
386 /* FIXME: we should manage errors */
387 bitbang_interface->blink(1);
390 for (unsigned int i = offset; i < bit_cnt + offset; i++) {
392 int bcval = 1 << (i % 8);
393 int swdio = !rnw && (buf[bytec] & bcval);
395 bitbang_interface->swd_write(0, swdio);
398 if (bitbang_interface->swdio_read())
401 buf[bytec] &= ~bcval;
404 bitbang_interface->swd_write(1, swdio);
407 if (bitbang_interface->blink) {
408 /* FIXME: we should manage errors */
409 bitbang_interface->blink(0);
413 static int bitbang_swd_switch_seq(enum swd_special_seq seq)
415 LOG_DEBUG("bitbang_swd_switch_seq");
419 LOG_DEBUG("SWD line reset");
420 bitbang_swd_exchange(false, (uint8_t *)swd_seq_line_reset, 0, swd_seq_line_reset_len);
423 LOG_DEBUG("JTAG-to-SWD");
424 bitbang_swd_exchange(false, (uint8_t *)swd_seq_jtag_to_swd, 0, swd_seq_jtag_to_swd_len);
426 case JTAG_TO_DORMANT:
427 LOG_DEBUG("JTAG-to-DORMANT");
428 bitbang_swd_exchange(false, (uint8_t *)swd_seq_jtag_to_dormant, 0, swd_seq_jtag_to_dormant_len);
431 LOG_DEBUG("SWD-to-JTAG");
432 bitbang_swd_exchange(false, (uint8_t *)swd_seq_swd_to_jtag, 0, swd_seq_swd_to_jtag_len);
435 LOG_DEBUG("SWD-to-DORMANT");
436 bitbang_swd_exchange(false, (uint8_t *)swd_seq_swd_to_dormant, 0, swd_seq_swd_to_dormant_len);
439 LOG_DEBUG("DORMANT-to-SWD");
440 bitbang_swd_exchange(false, (uint8_t *)swd_seq_dormant_to_swd, 0, swd_seq_dormant_to_swd_len);
442 case DORMANT_TO_JTAG:
443 LOG_DEBUG("DORMANT-to-JTAG");
444 bitbang_swd_exchange(false, (uint8_t *)swd_seq_dormant_to_jtag, 0, swd_seq_dormant_to_jtag_len);
447 LOG_ERROR("Sequence %d not supported", seq);
454 static void swd_clear_sticky_errors(void)
456 bitbang_swd_write_reg(swd_cmd(false, false, DP_ABORT),
457 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
460 static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk)
462 LOG_DEBUG("bitbang_swd_read_reg");
463 assert(cmd & SWD_CMD_RNW);
465 if (queued_retval != ERROR_OK) {
466 LOG_DEBUG("Skip bitbang_swd_read_reg because queued_retval=%d", queued_retval);
471 uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
473 cmd |= SWD_CMD_START | SWD_CMD_PARK;
474 bitbang_swd_exchange(false, &cmd, 0, 8);
476 bitbang_interface->swdio_drive(false);
477 bitbang_swd_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3 + 32 + 1 + 1);
478 bitbang_interface->swdio_drive(true);
480 int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
481 uint32_t data = buf_get_u32(trn_ack_data_parity_trn, 1 + 3, 32);
482 int parity = buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 32, 1);
484 LOG_DEBUG("%s %s read reg %X = %08"PRIx32,
485 ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
486 cmd & SWD_CMD_APNDP ? "AP" : "DP",
487 (cmd & SWD_CMD_A32) >> 1,
490 if (ack == SWD_ACK_WAIT) {
491 swd_clear_sticky_errors();
493 } else if (ack != SWD_ACK_OK) {
494 queued_retval = swd_ack_to_error_code(ack);
498 if (parity != parity_u32(data)) {
499 LOG_ERROR("Wrong parity detected");
500 queued_retval = ERROR_FAIL;
505 if (cmd & SWD_CMD_APNDP)
506 bitbang_swd_exchange(true, NULL, 0, ap_delay_clk);
511 static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk)
513 LOG_DEBUG("bitbang_swd_write_reg");
514 assert(!(cmd & SWD_CMD_RNW));
516 if (queued_retval != ERROR_OK) {
517 LOG_DEBUG("Skip bitbang_swd_write_reg because queued_retval=%d", queued_retval);
521 /* Devices do not reply to DP_TARGETSEL write cmd, ignore received ack */
522 bool check_ack = swd_cmd_returns_ack(cmd);
524 /* init the array to silence scan-build */
525 uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)] = {0};
527 buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32, value);
528 buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1 + 32, 1, parity_u32(value));
530 cmd |= SWD_CMD_START | SWD_CMD_PARK;
531 bitbang_swd_exchange(false, &cmd, 0, 8);
533 bitbang_interface->swdio_drive(false);
534 bitbang_swd_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3 + 1);
535 bitbang_interface->swdio_drive(true);
536 bitbang_swd_exchange(false, trn_ack_data_parity_trn, 1 + 3 + 1, 32 + 1);
538 int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
540 LOG_DEBUG("%s%s %s write reg %X = %08"PRIx32,
541 check_ack ? "" : "ack ignored ",
542 ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
543 cmd & SWD_CMD_APNDP ? "AP" : "DP",
544 (cmd & SWD_CMD_A32) >> 1,
545 buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32));
548 if (ack == SWD_ACK_WAIT) {
549 swd_clear_sticky_errors();
551 } else if (ack != SWD_ACK_OK) {
552 queued_retval = swd_ack_to_error_code(ack);
557 if (cmd & SWD_CMD_APNDP)
558 bitbang_swd_exchange(true, NULL, 0, ap_delay_clk);
563 static int bitbang_swd_run_queue(void)
565 LOG_DEBUG("bitbang_swd_run_queue");
566 /* A transaction must be followed by another transaction or at least 8 idle cycles to
567 * ensure that data is clocked through the AP. */
568 bitbang_swd_exchange(true, NULL, 0, 8);
570 int retval = queued_retval;
571 queued_retval = ERROR_OK;
572 LOG_DEBUG("SWD queue return value: %02x", retval);
576 const struct swd_driver bitbang_swd = {
577 .init = bitbang_swd_init,
578 .switch_seq = bitbang_swd_switch_seq,
579 .read_reg = bitbang_swd_read_reg,
580 .write_reg = bitbang_swd_write_reg,
581 .run = bitbang_swd_run_queue,