1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2011 by Martin Schmoelzer *
5 * <martin.schmoelzer@student.tuwien.ac.at> *
6 ***************************************************************************/
13 * All information in this file was taken from the EZ-USB Technical
14 * Reference Manual, Cypress Semiconductor, 3901 North First Street
15 * San Jose, CA 95134 (www.cypress.com).
17 * The EZ-USB Technical Reference Manual is called "EZ-USB TRM" hereafter.
19 * The following bit name definitions differ from those in the EZ-USB TRM:
20 * - All lowercase characters in the EZ-USB TRM bit names have been converted
21 * to capitals (e. g. "WakeSRC" converted to "WAKESRC").
22 * - CPUCS: 8051RES is named "RES8051".
23 * - ISOCTL: Two MBZ ("Must Be Zero") bits are named "MBZ0" and "MBZ1".
24 * - I2CS: STOP and START bits are preceded by "I2C_"
25 * - INxCS, OUTxCS: the busy and stall bits are named "EPBSY" and "EPSTALL".
26 * - TOGCTL: EZ-USB TRM bit names are preceded by "TOG_".
29 /* Compiler-specific definitions of SBIT, SFR, SFRX, ... macros */
30 #include <mcs51/compiler.h>
42 /**************************************************************************
43 ************************ Special Function Registers **********************
44 ***************************************************************************/
46 /* See EZ-USB TRM, pp. A-9 - A-10 */
56 /* Bit 1 read-only, always reads '0' */
57 /* Bit 2 read-only, always reads '0' */
58 /* Bit 3 read-only, always reads '0' */
59 /* Bit 4 read-only, always reads '0' */
60 /* Bit 5 read-only, always reads '0' */
61 /* Bit 6 read-only, always reads '0' */
62 /* Bit 7 read-only, always reads '0' */
69 /* Bit 4 read-only, always reads '1' */
70 /* Bit 5 read-only, always reads '1' */
85 /* Some bits in this register share the same name in the EZ-USB TRM. Therefore,
86 * we add a '0'/'1' to distinguish them */
113 /* Bit 1 read-only, always reads '0' */
114 /* Bit 2 read-only, always reads '0' */
115 /* Bit 3 read-only, always reads '0' */
116 /* Bit 4 read-only, always reads '0' */
117 /* Bit 5 read-only, always reads '0' */
118 /* Bit 6 read-only, always reads '0' */
119 /* Bit 7 read-only, always reads '0' */
122 /* Bit 0 read-only, always reads '0' */
123 /* Bit 1 read-only, always reads '0' */
124 /* Bit 2 read-only, always reads '0' */
125 /* Bit 3 read-only, always reads '1' */
126 #define USBINT bmBit4
127 #define I2CINT bmBit5
131 /* Definition of the _XPAGE register, according to SDCC Compiler User Guide,
132 * Version 3.0.1, Chapter 4, p. 61. Also see EZ-USB TRM, p. 2-4. */
139 SBIT(RB8_0, 0x98, 2);
140 SBIT(TB8_0, 0x98, 3);
141 SBIT(REN_0, 0x98, 4);
142 SBIT(SM2_0, 0x98, 5);
143 SBIT(SM1_0, 0x98, 6);
144 SBIT(SM0_0, 0x98, 7);
166 /* Bit 7 read-only, always reads '1' */
171 SBIT(RB8_1, 0xC0, 2);
172 SBIT(TB8_1, 0xC0, 3);
173 SBIT(REN_1, 0xC0, 4);
174 SBIT(SM2_1, 0xC0, 5);
175 SBIT(SM1_1, 0xC0, 6);
176 SBIT(SM0_1, 0xC0, 7);
181 SBIT(CPRL2, 0xC8, 0);
184 SBIT(EXEN2, 0xC8, 3);
206 /* Bit 0 read-only, always reads '0' */
207 /* Bit 1 read-only, always reads '0' */
208 /* Bit 2 read-only, always reads '0' */
211 SBIT(ERESI, 0xD8, 5);
212 /* Bit 6 read-only, always reads '1' */
213 SBIT(SMOD1, 0xD8, 7);
223 /* Bit 5 read-only, always reads '1' */
224 /* Bit 6 read-only, always reads '1' */
225 /* Bit 7 read-only, always reads '1' */
235 /* Bit 5 read-only, always reads '1' */
236 /* Bit 6 read-only, always reads '1' */
237 /* Bit 7 read-only, always reads '1' */
239 /**************************************************************************
240 ***************************** XDATA Registers ****************************
241 ***************************************************************************/
243 /************************ Endpoint 0-7 Data Buffers ************************/
244 SFRX(OUT7BUF[64], 0x7B40);
245 SFRX(IN7BUF[64], 0x7B80);
246 SFRX(OUT6BUF[64], 0x7BC0);
247 SFRX(IN6BUF[64], 0x7C00);
248 SFRX(OUT5BUF[64], 0x7C40);
249 SFRX(IN5BUF[64], 0x7C80);
250 SFRX(OUT4BUF[64], 0x7CC0);
251 SFRX(IN4BUF[64], 0x7D00);
252 SFRX(OUT3BUF[64], 0x7D40);
253 SFRX(IN3BUF[64], 0x7D80);
254 SFRX(OUT2BUF[64], 0x7DC0);
255 SFRX(IN2BUF[64], 0x7E00);
256 SFRX(OUT1BUF[64], 0x7E40);
257 SFRX(IN1BUF[64], 0x7E80);
258 SFRX(OUT0BUF[64], 0x7EC0);
259 SFRX(IN0BUF[64], 0x7F00);
260 /* 0x7F40 - 0x7F5F reserved */
262 /**************************** Isochronous Data *****************************/
263 SFRX(OUT8DATA, 0x7F60);
264 SFRX(OUT9DATA, 0x7F61);
265 SFRX(OUT10DATA, 0x7F62);
266 SFRX(OUT11DATA, 0x7F63);
267 SFRX(OUT12DATA, 0x7F64);
268 SFRX(OUT13DATA, 0x7F65);
269 SFRX(OUT14DATA, 0x7F66);
270 SFRX(OUT15DATA, 0x7F67);
272 SFRX(IN8DATA, 0x7F68);
273 SFRX(IN9DATA, 0x7F69);
274 SFRX(IN10DATA, 0x7F6A);
275 SFRX(IN11DATA, 0x7F6B);
276 SFRX(IN12DATA, 0x7F6C);
277 SFRX(IN13DATA, 0x7F6D);
278 SFRX(IN14DATA, 0x7F6E);
279 SFRX(IN15DATA, 0x7F6F);
281 /************************* Isochronous Byte Counts *************************/
282 SFRX(OUT8BCH, 0x7F70);
283 SFRX(OUT8BCL, 0x7F71);
284 SFRX(OUT9BCH, 0x7F72);
285 SFRX(OUT9BCL, 0x7F73);
286 SFRX(OUT10BCH, 0x7F74);
287 SFRX(OUT10BCL, 0x7F75);
288 SFRX(OUT11BCH, 0x7F76);
289 SFRX(OUT11BCL, 0x7F77);
290 SFRX(OUT12BCH, 0x7F78);
291 SFRX(OUT12BCL, 0x7F79);
292 SFRX(OUT13BCH, 0x7F7A);
293 SFRX(OUT13BCL, 0x7F7B);
294 SFRX(OUT14BCH, 0x7F7C);
295 SFRX(OUT14BCL, 0x7F7D);
296 SFRX(OUT15BCH, 0x7F7E);
297 SFRX(OUT16BCL, 0x7F7F);
299 /****************************** CPU Registers ******************************/
301 #define RES8051 bmBit0
302 #define CLK24OE bmBit1
303 /* Bit 2 read-only, always reads '0' */
304 /* Bit 3 read-only, always reads '0' */
305 /* Bits 4...7: Chip Revision */
307 SFRX(PORTACFG, 0x7F93);
314 #define RXD0OUT bmBit6
315 #define RXD1OUT bmBit7
317 SFRX(PORTBCFG, 0x7F94);
327 SFRX(PORTCCFG, 0x7F95);
337 /*********************** Input-Output Port Registers ***********************/
428 /* 0x7F9F reserved */
430 /****************** Isochronous Control/Status Registers *******************/
431 SFRX(ISOERR, 0x7FA0);
432 #define ISO8ERR bmBit0
433 #define ISO9ERR bmBit1
434 #define ISO10ERR bmBit2
435 #define ISO11ERR bmBit3
436 #define ISO12ERR bmBit4
437 #define ISO13ERR bmBit5
438 #define ISO14ERR bmBit6
439 #define ISO15ERR bmBit7
441 SFRX(ISOCTL, 0x7FA1);
442 #define ISODISAB bmBit0
445 #define PPSTAT bmBit3
451 SFRX(ZBCOUT, 0x7FA2);
461 /* 0x7FA3 reserved */
462 /* 0x7FA4 reserved */
464 /****************************** I2C Registers ******************************/
471 #define LASTRD bmBit5
472 #define I2C_STOP bmBit6
473 #define I2C_START bmBit7
476 /* 0x7FA7 reserved */
478 /******************************* Interrupts ********************************/
480 /* Bit 0 read-only, always reads '0' */
481 /* Bit 1 read-only, always reads '0' */
487 /* Bit 7 read-only, always reads '0' */
489 SFRX(IN07IRQ, 0x7FA9);
499 SFRX(OUT07IRQ, 0x7FAA);
500 #define OUT0IR bmBit0
501 #define OUT1IR bmBit1
502 #define OUT2IR bmBit2
503 #define OUT3IR bmBit3
504 #define OUT4IR bmBit4
505 #define OUT5IR bmBit5
506 #define OUT6IR bmBit6
507 #define OUT7IR bmBit7
509 SFRX(USBIRQ, 0x7FAB);
510 #define SUDAVIR bmBit0
512 #define SUTOKIR bmBit2
513 #define SUSPIR bmBit3
514 #define URESIR bmBit4
519 SFRX(IN07IEN, 0x7FAC);
520 #define IN0IEN bmBit0
521 #define IN1IEN bmBit1
522 #define IN2IEN bmBit2
523 #define IN3IEN bmBit3
524 #define IN4IEN bmBit4
525 #define IN5IEN bmBit5
526 #define IN6IEN bmBit6
527 #define IN7IEN bmBit7
529 SFRX(OUT07IEN, 0x7FAD);
530 #define OUT0IEN bmBit0
531 #define OUT1IEN bmBit1
532 #define OUT2IEN bmBit2
533 #define OUT3IEN bmBit3
534 #define OUT4IEN bmBit4
535 #define OUT5IEN bmBit5
536 #define OUT6IEN bmBit6
537 #define OUT7IEN bmBit7
539 SFRX(USBIEN, 0x7FAE);
540 #define SUDAVIE bmBit0
542 #define SUTOKIE bmBit2
543 #define SUSPIE bmBit3
544 #define URESIE bmBit4
549 SFRX(USBBAV, 0x7FAF);
552 #define BPPULSE bmBit2
559 /* 0x7FB0 reserved */
560 /* 0x7FB1 reserved */
561 SFRX(BPADDRH, 0x7FB2);
562 SFRX(BPADDRL, 0x7FB3);
564 /****************************** Endpoints 0-7 ******************************/
566 #define EP0STALL bmBit0
568 #define IN0BSY bmBit2
569 #define OUT0BSY bmBit3
590 /* 0x7FC4 reserved */
591 SFRX(OUT0BC, 0x7FC5);
592 SFRX(OUT1CS, 0x7FC6);
593 SFRX(OUT1BC, 0x7FC7);
594 SFRX(OUT2CS, 0x7FC8);
595 SFRX(OUT2BC, 0x7FC9);
596 SFRX(OUT3CS, 0x7FCA);
597 SFRX(OUT3BC, 0x7FCB);
598 SFRX(OUT4CS, 0x7FCC);
599 SFRX(OUT4BC, 0x7FCD);
600 SFRX(OUT5CS, 0x7FCE);
601 SFRX(OUT5BC, 0x7FCF);
602 SFRX(OUT6CS, 0x7FD0);
603 SFRX(OUT6BC, 0x7FD1);
604 SFRX(OUT7CS, 0x7FD2);
605 SFRX(OUT7BC, 0x7FD3);
607 /* The INxSTALL, OUTxSTALL, INxBSY and OUTxBSY bits are the same for all
608 * INxCS/OUTxCS registers. For better readability, we define them only once */
609 #define EPSTALL bmBit0
612 /************************** Global USB Registers ***************************/
613 SFRX(SUDPTRH, 0x7FD4);
614 SFRX(SUDPTRL, 0x7FD5);
617 #define SIGRSUME bmBit0
619 #define DISCOE bmBit2
620 #define DISCON bmBit3
624 #define WAKESRC bmBit7
626 SFRX(TOGCTL, 0x7FD7);
627 #define TOG_EP0 bmBit0
628 #define TOG_EP1 bmBit1
629 #define TOG_EP2 bmBit2
630 /* Bit 3 is read-only, always reads '0' */
631 #define TOG_IO bmBit4
636 SFRX(USBFRAMEL, 0x7FD8);
637 SFRX(USBFRAMEH, 0x7FD9);
638 /* 0x7FDA reserved */
639 SFRX(FNADDR, 0x7FDB);
640 /* 0x7FDC reserved */
642 SFRX(USBPAIR, 0x7FDD);
646 #define PR2OUT bmBit3
647 #define PR4OUT bmBit4
648 #define PR6OUT bmBit5
650 #define ISOSEND0 bmBit7
652 SFRX(IN07VAL, 0x7FDE);
653 /* Bit 0 is read-only, always reads '1' */
654 #define IN1VAL bmBit1
655 #define IN2VAL bmBit2
656 #define IN3VAL bmBit3
657 #define IN4VAL bmBit4
658 #define IN5VAL bmBit5
659 #define IN6VAL bmBit6
660 #define IN7VAL bmBit7
662 SFRX(OUT07VAL, 0x7FDF);
663 /* Bit 0 is read-only, always reads '1' */
664 #define OUT1VAL bmBit1
665 #define OUT2VAL bmBit2
666 #define OUT3VAL bmBit3
667 #define OUT4VAL bmBit4
668 #define OUT5VAL bmBit5
669 #define OUT6VAL bmBit6
670 #define OUT7VAL bmBit7
672 SFRX(INISOVAL, 0x7FE0);
673 #define IN8VAL bmBit0
674 #define IN9VAL bmBit1
675 #define IN10VAL bmBit2
676 #define IN11VAL bmBit3
677 #define IN12VAL bmBit4
678 #define IN13VAL bmBit5
679 #define IN14VAL bmBit6
680 #define IN15VAL bmBit7
682 SFRX(OUTISOVAL, 0x7FE1);
683 #define OUT8VAL bmBit0
684 #define OUT9VAL bmBit1
685 #define OUT10VAL bmBit2
686 #define OUT11VAL bmBit3
687 #define OUT12VAL bmBit4
688 #define OUT13VAL bmBit5
689 #define OUT14VAL bmBit6
690 #define OUT15VAL bmBit7
692 SFRX(FASTXFR, 0x7FE2);
702 SFRX(AUTOPTRH, 0x7FE3);
703 SFRX(AUTOPTRL, 0x7FE4);
704 SFRX(AUTODATA, 0x7FE5);
705 /* 0x7FE6 reserved */
706 /* 0x7FE7 reserved */
708 /******************************* Setup Data ********************************/
709 SFRX(SETUPDAT[8], 0x7FE8);
711 /************************* Isochronous FIFO sizes **************************/
712 SFRX(OUT8ADDR, 0x7FF0);
713 SFRX(OUT9ADDR, 0x7FF1);
714 SFRX(OUT10ADDR, 0x7FF2);
715 SFRX(OUT11ADDR, 0x7FF3);
716 SFRX(OUT12ADDR, 0x7FF4);
717 SFRX(OUT13ADDR, 0x7FF5);
718 SFRX(OUT14ADDR, 0x7FF6);
719 SFRX(OUT15ADDR, 0x7FF7);
721 SFRX(IN8ADDR, 0x7FF8);
722 SFRX(IN9ADDR, 0x7FF9);
723 SFRX(IN10ADDR, 0x7FFA);
724 SFRX(IN11ADDR, 0x7FFB);
725 SFRX(IN12ADDR, 0x7FFC);
726 SFRX(IN13ADDR, 0x7FFD);
727 SFRX(IN14ADDR, 0x7FFE);
728 SFRX(IN15ADDR, 0x7FFF);