1 /***************************************************************************
2 * Copyright (C) 2011 by Martin Schmoelzer *
3 * <martin.schmoelzer@student.tuwien.ac.at> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
24 * All information in this file was taken from the EZ-USB Technical
25 * Reference Manual, Cypress Semiconductor, 3901 North First Street
26 * San Jose, CA 95134 (www.cypress.com).
28 * The EZ-USB Technical Reference Manual is called "EZ-USB TRM" hereafter.
30 * The following bit name definitions differ from those in the EZ-USB TRM:
31 * - All lowercase characters in the EZ-USB TRM bit names have been converted
32 * to capitals (e. g. "WakeSRC" converted to "WAKESRC").
33 * - CPUCS: 8051RES is named "RES8051".
34 * - ISOCTL: Two MBZ ("Must Be Zero") bits are named "MBZ0" and "MBZ1".
35 * - I2CS: STOP and START bits are preceded by "I2C_"
36 * - INxCS, OUTxCS: the busy and stall bits are named "EPBSY" and "EPSTALL".
37 * - TOGCTL: EZ-USB TRM bit names are preceded by "TOG_".
40 /* Compiler-specific definitions of SBIT, SFR, SFRX, ... macros */
41 #include <mcs51/compiler.h>
53 /**************************************************************************
54 ************************ Special Function Registers **********************
55 ***************************************************************************/
57 /* See EZ-USB TRM, pp. A-9 - A-10 */
67 /* Bit 1 read-only, always reads '0' */
68 /* Bit 2 read-only, always reads '0' */
69 /* Bit 3 read-only, always reads '0' */
70 /* Bit 4 read-only, always reads '0' */
71 /* Bit 5 read-only, always reads '0' */
72 /* Bit 6 read-only, always reads '0' */
73 /* Bit 7 read-only, always reads '0' */
80 /* Bit 4 read-only, always reads '1' */
81 /* Bit 5 read-only, always reads '1' */
96 /* Some bits in this register share the same name in the EZ-USB TRM. Therefore,
97 * we add a '0'/'1' to distinguish them */
124 /* Bit 1 read-only, always reads '0' */
125 /* Bit 2 read-only, always reads '0' */
126 /* Bit 3 read-only, always reads '0' */
127 /* Bit 4 read-only, always reads '0' */
128 /* Bit 5 read-only, always reads '0' */
129 /* Bit 6 read-only, always reads '0' */
130 /* Bit 7 read-only, always reads '0' */
133 /* Bit 0 read-only, always reads '0' */
134 /* Bit 1 read-only, always reads '0' */
135 /* Bit 2 read-only, always reads '0' */
136 /* Bit 3 read-only, always reads '1' */
137 #define USBINT bmBit4
138 #define I2CINT bmBit5
142 /* Definition of the _XPAGE register, according to SDCC Compiler User Guide,
143 * Version 3.0.1, Chapter 4, p. 61. Also see EZ-USB TRM, p. 2-4. */
150 SBIT(RB8_0, 0x98, 2);
151 SBIT(TB8_0, 0x98, 3);
152 SBIT(REN_0, 0x98, 4);
153 SBIT(SM2_0, 0x98, 5);
154 SBIT(SM1_0, 0x98, 6);
155 SBIT(SM0_0, 0x98, 7);
177 /* Bit 7 read-only, always reads '1' */
182 SBIT(RB8_1, 0xC0, 2);
183 SBIT(TB8_1, 0xC0, 3);
184 SBIT(REN_1, 0xC0, 4);
185 SBIT(SM2_1, 0xC0, 5);
186 SBIT(SM1_1, 0xC0, 6);
187 SBIT(SM0_1, 0xC0, 7);
192 SBIT(CPRL2, 0xC8, 0);
195 SBIT(EXEN2, 0xC8, 3);
217 /* Bit 0 read-only, always reads '0' */
218 /* Bit 1 read-only, always reads '0' */
219 /* Bit 2 read-only, always reads '0' */
222 SBIT(ERESI, 0xD8, 5);
223 /* Bit 6 read-only, always reads '1' */
224 SBIT(SMOD1, 0xD8, 7);
234 /* Bit 5 read-only, always reads '1' */
235 /* Bit 6 read-only, always reads '1' */
236 /* Bit 7 read-only, always reads '1' */
246 /* Bit 5 read-only, always reads '1' */
247 /* Bit 6 read-only, always reads '1' */
248 /* Bit 7 read-only, always reads '1' */
250 /**************************************************************************
251 ***************************** XDATA Registers ****************************
252 ***************************************************************************/
254 /************************ Endpoint 0-7 Data Buffers ************************/
255 SFRX(OUT7BUF[64], 0x7B40);
256 SFRX(IN7BUF[64], 0x7B80);
257 SFRX(OUT6BUF[64], 0x7BC0);
258 SFRX(IN6BUF[64], 0x7C00);
259 SFRX(OUT5BUF[64], 0x7C40);
260 SFRX(IN5BUF[64], 0x7C80);
261 SFRX(OUT4BUF[64], 0x7CC0);
262 SFRX(IN4BUF[64], 0x7D00);
263 SFRX(OUT3BUF[64], 0x7D40);
264 SFRX(IN3BUF[64], 0x7D80);
265 SFRX(OUT2BUF[64], 0x7DC0);
266 SFRX(IN2BUF[64], 0x7E00);
267 SFRX(OUT1BUF[64], 0x7E40);
268 SFRX(IN1BUF[64], 0x7E80);
269 SFRX(OUT0BUF[64], 0x7EC0);
270 SFRX(IN0BUF[64], 0x7F00);
271 /* 0x7F40 - 0x7F5F reserved */
273 /**************************** Isochronous Data *****************************/
274 SFRX(OUT8DATA, 0x7F60);
275 SFRX(OUT9DATA, 0x7F61);
276 SFRX(OUT10DATA, 0x7F62);
277 SFRX(OUT11DATA, 0x7F63);
278 SFRX(OUT12DATA, 0x7F64);
279 SFRX(OUT13DATA, 0x7F65);
280 SFRX(OUT14DATA, 0x7F66);
281 SFRX(OUT15DATA, 0x7F67);
283 SFRX(IN8DATA, 0x7F68);
284 SFRX(IN9DATA, 0x7F69);
285 SFRX(IN10DATA, 0x7F6A);
286 SFRX(IN11DATA, 0x7F6B);
287 SFRX(IN12DATA, 0x7F6C);
288 SFRX(IN13DATA, 0x7F6D);
289 SFRX(IN14DATA, 0x7F6E);
290 SFRX(IN15DATA, 0x7F6F);
292 /************************* Isochronous Byte Counts *************************/
293 SFRX(OUT8BCH, 0x7F70);
294 SFRX(OUT8BCL, 0x7F71);
295 SFRX(OUT9BCH, 0x7F72);
296 SFRX(OUT9BCL, 0x7F73);
297 SFRX(OUT10BCH, 0x7F74);
298 SFRX(OUT10BCL, 0x7F75);
299 SFRX(OUT11BCH, 0x7F76);
300 SFRX(OUT11BCL, 0x7F77);
301 SFRX(OUT12BCH, 0x7F78);
302 SFRX(OUT12BCL, 0x7F79);
303 SFRX(OUT13BCH, 0x7F7A);
304 SFRX(OUT13BCL, 0x7F7B);
305 SFRX(OUT14BCH, 0x7F7C);
306 SFRX(OUT14BCL, 0x7F7D);
307 SFRX(OUT15BCH, 0x7F7E);
308 SFRX(OUT16BCL, 0x7F7F);
310 /****************************** CPU Registers ******************************/
312 #define RES8051 bmBit0
313 #define CLK24OE bmBit1
314 /* Bit 2 read-only, always reads '0' */
315 /* Bit 3 read-only, always reads '0' */
316 /* Bits 4...7: Chip Revision */
318 SFRX(PORTACFG, 0x7F93);
325 #define RXD0OUT bmBit6
326 #define RXD1OUT bmBit7
328 SFRX(PORTBCFG, 0x7F94);
338 SFRX(PORTCCFG, 0x7F95);
348 /*********************** Input-Output Port Registers ***********************/
439 /* 0x7F9F reserved */
441 /****************** Isochronous Control/Status Registers *******************/
442 SFRX(ISOERR, 0x7FA0);
443 #define ISO8ERR bmBit0
444 #define ISO9ERR bmBit1
445 #define ISO10ERR bmBit2
446 #define ISO11ERR bmBit3
447 #define ISO12ERR bmBit4
448 #define ISO13ERR bmBit5
449 #define ISO14ERR bmBit6
450 #define ISO15ERR bmBit7
452 SFRX(ISOCTL, 0x7FA1);
453 #define ISODISAB bmBit0
456 #define PPSTAT bmBit3
462 SFRX(ZBCOUT, 0x7FA2);
472 /* 0x7FA3 reserved */
473 /* 0x7FA4 reserved */
475 /****************************** I2C Registers ******************************/
482 #define LASTRD bmBit5
483 #define I2C_STOP bmBit6
484 #define I2C_START bmBit7
487 /* 0x7FA7 reserved */
489 /******************************* Interrupts ********************************/
491 /* Bit 0 read-only, always reads '0' */
492 /* Bit 1 read-only, always reads '0' */
498 /* Bit 7 read-only, always reads '0' */
500 SFRX(IN07IRQ, 0x7FA9);
510 SFRX(OUT07IRQ, 0x7FAA);
511 #define OUT0IR bmBit0
512 #define OUT1IR bmBit1
513 #define OUT2IR bmBit2
514 #define OUT3IR bmBit3
515 #define OUT4IR bmBit4
516 #define OUT5IR bmBit5
517 #define OUT6IR bmBit6
518 #define OUT7IR bmBit7
520 SFRX(USBIRQ, 0x7FAB);
521 #define SUDAVIR bmBit0
523 #define SUTOKIR bmBit2
524 #define SUSPIR bmBit3
525 #define URESIR bmBit4
530 SFRX(IN07IEN, 0x7FAC);
531 #define IN0IEN bmBit0
532 #define IN1IEN bmBit1
533 #define IN2IEN bmBit2
534 #define IN3IEN bmBit3
535 #define IN4IEN bmBit4
536 #define IN5IEN bmBit5
537 #define IN6IEN bmBit6
538 #define IN7IEN bmBit7
540 SFRX(OUT07IEN, 0x7FAD);
541 #define OUT0IEN bmBit0
542 #define OUT1IEN bmBit1
543 #define OUT2IEN bmBit2
544 #define OUT3IEN bmBit3
545 #define OUT4IEN bmBit4
546 #define OUT5IEN bmBit5
547 #define OUT6IEN bmBit6
548 #define OUT7IEN bmBit7
550 SFRX(USBIEN, 0x7FAE);
551 #define SUDAVIE bmBit0
553 #define SUTOKIE bmBit2
554 #define SUSPIE bmBit3
555 #define URESIE bmBit4
560 SFRX(USBBAV, 0x7FAF);
563 #define BPPULSE bmBit2
570 /* 0x7FB0 reserved */
571 /* 0x7FB1 reserved */
572 SFRX(BPADDRH, 0x7FB2);
573 SFRX(BPADDRL, 0x7FB3);
575 /****************************** Endpoints 0-7 ******************************/
577 #define EP0STALL bmBit0
579 #define IN0BSY bmBit2
580 #define OUT0BSY bmBit3
601 /* 0x7FC4 reserved */
602 SFRX(OUT0BC, 0x7FC5);
603 SFRX(OUT1CS, 0x7FC6);
604 SFRX(OUT1BC, 0x7FC7);
605 SFRX(OUT2CS, 0x7FC8);
606 SFRX(OUT2BC, 0x7FC9);
607 SFRX(OUT3CS, 0x7FCA);
608 SFRX(OUT3BC, 0x7FCB);
609 SFRX(OUT4CS, 0x7FCC);
610 SFRX(OUT4BC, 0x7FCD);
611 SFRX(OUT5CS, 0x7FCE);
612 SFRX(OUT5BC, 0x7FCF);
613 SFRX(OUT6CS, 0x7FD0);
614 SFRX(OUT6BC, 0x7FD1);
615 SFRX(OUT7CS, 0x7FD2);
616 SFRX(OUT7BC, 0x7FD3);
618 /* The INxSTALL, OUTxSTALL, INxBSY and OUTxBSY bits are the same for all
619 * INxCS/OUTxCS registers. For better readability, we define them only once */
620 #define EPSTALL bmBit0
623 /************************** Global USB Registers ***************************/
624 SFRX(SUDPTRH, 0x7FD4);
625 SFRX(SUDPTRL, 0x7FD5);
628 #define SIGRSUME bmBit0
630 #define DISCOE bmBit2
631 #define DISCON bmBit3
635 #define WAKESRC bmBit7
637 SFRX(TOGCTL, 0x7FD7);
638 #define TOG_EP0 bmBit0
639 #define TOG_EP1 bmBit1
640 #define TOG_EP2 bmBit2
641 /* Bit 3 is read-only, always reads '0' */
642 #define TOG_IO bmBit4
647 SFRX(USBFRAMEL, 0x7FD8);
648 SFRX(USBFRAMEH, 0x7FD9);
649 /* 0x7FDA reserved */
650 SFRX(FNADDR, 0x7FDB);
651 /* 0x7FDC reserved */
653 SFRX(USBPAIR, 0x7FDD);
657 #define PR2OUT bmBit3
658 #define PR4OUT bmBit4
659 #define PR6OUT bmBit5
661 #define ISOSEND0 bmBit7
663 SFRX(IN07VAL, 0x7FDE);
664 /* Bit 0 is read-only, always reads '1' */
665 #define IN1VAL bmBit1
666 #define IN2VAL bmBit2
667 #define IN3VAL bmBit3
668 #define IN4VAL bmBit4
669 #define IN5VAL bmBit5
670 #define IN6VAL bmBit6
671 #define IN7VAL bmBit7
673 SFRX(OUT07VAL, 0x7FDF);
674 /* Bit 0 is read-only, always reads '1' */
675 #define OUT1VAL bmBit1
676 #define OUT2VAL bmBit2
677 #define OUT3VAL bmBit3
678 #define OUT4VAL bmBit4
679 #define OUT5VAL bmBit5
680 #define OUT6VAL bmBit6
681 #define OUT7VAL bmBit7
683 SFRX(INISOVAL, 0x7FE0);
684 #define IN8VAL bmBit0
685 #define IN9VAL bmBit1
686 #define IN10VAL bmBit2
687 #define IN11VAL bmBit3
688 #define IN12VAL bmBit4
689 #define IN13VAL bmBit5
690 #define IN14VAL bmBit6
691 #define IN15VAL bmBit7
693 SFRX(OUTISOVAL, 0x7FE1);
694 #define OUT8VAL bmBit0
695 #define OUT9VAL bmBit1
696 #define OUT10VAL bmBit2
697 #define OUT11VAL bmBit3
698 #define OUT12VAL bmBit4
699 #define OUT13VAL bmBit5
700 #define OUT14VAL bmBit6
701 #define OUT15VAL bmBit7
703 SFRX(FASTXFR, 0x7FE2);
713 SFRX(AUTOPTRH, 0x7FE3);
714 SFRX(AUTOPTRL, 0x7FE4);
715 SFRX(AUTODATA, 0x7FE5);
716 /* 0x7FE6 reserved */
717 /* 0x7FE7 reserved */
719 /******************************* Setup Data ********************************/
720 SFRX(SETUPDAT[8], 0x7FE8);
722 /************************* Isochronous FIFO sizes **************************/
723 SFRX(OUT8ADDR, 0x7FF0);
724 SFRX(OUT9ADDR, 0x7FF1);
725 SFRX(OUT10ADDR, 0x7FF2);
726 SFRX(OUT11ADDR, 0x7FF3);
727 SFRX(OUT12ADDR, 0x7FF4);
728 SFRX(OUT13ADDR, 0x7FF5);
729 SFRX(OUT14ADDR, 0x7FF6);
730 SFRX(OUT15ADDR, 0x7FF7);
732 SFRX(IN8ADDR, 0x7FF8);
733 SFRX(IN9ADDR, 0x7FF9);
734 SFRX(IN10ADDR, 0x7FFA);
735 SFRX(IN11ADDR, 0x7FFB);
736 SFRX(IN12ADDR, 0x7FFC);
737 SFRX(IN13ADDR, 0x7FFD);
738 SFRX(IN14ADDR, 0x7FFE);
739 SFRX(IN15ADDR, 0x7FFF);