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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2013 by Andes Technology                                *
   5  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   6  ***************************************************************************/
   7
   8 #ifndef OPENOCD_JTAG_AICE_AICE_USB_H
   9 #define OPENOCD_JTAG_AICE_AICE_USB_H
  10
  11 #include "aice_port.h"
  12
  13 /* AICE USB timeout value */
  14 #define AICE_USB_TIMEOUT                                5000
  15
  16 /* AICE USB buffer size */
  17 #define AICE_IN_BUFFER_SIZE                             2048
  18 #define AICE_OUT_BUFFER_SIZE                    2048
  19 #define AICE_IN_PACKETS_BUFFER_SIZE             2048
  20 #define AICE_OUT_PACKETS_BUFFER_SIZE    2048
  21 #define AICE_IN_BATCH_COMMAND_SIZE              512
  22 #define AICE_OUT_BATCH_COMMAND_SIZE             512
  23 #define AICE_IN_PACK_COMMAND_SIZE               2048
  24 #define AICE_OUT_PACK_COMMAND_SIZE              2048
  25
  26 /* Constants for AICE command READ_CTRL */
  27 #define AICE_READ_CTRL_GET_ICE_STATE            0x00
  28 #define AICE_READ_CTRL_GET_HARDWARE_VERSION     0x01
  29 #define AICE_READ_CTRL_GET_FPGA_VERSION         0x02
  30 #define AICE_READ_CTRL_GET_FIRMWARE_VERSION     0x03
  31 #define AICE_READ_CTRL_GET_JTAG_PIN_STATUS      0x04
  32 #define AICE_READ_CTRL_BATCH_BUF_INFO           0x22
  33 #define AICE_READ_CTRL_BATCH_STATUS                     0x23
  34 #define AICE_READ_CTRL_BATCH_BUF0_STATE         0x31
  35 #define AICE_READ_CTRL_BATCH_BUF4_STATE         0x39
  36 #define AICE_READ_CTRL_BATCH_BUF5_STATE         0x3b
  37
  38 /* Constants for AICE command WRITE_CTRL */
  39 #define AICE_WRITE_CTRL_TCK_CONTROL                             0x00
  40 #define AICE_WRITE_CTRL_JTAG_PIN_CONTROL                0x01
  41 #define AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS    0x02
  42 #define AICE_WRITE_CTRL_RESERVED                                0x03
  43 #define AICE_WRITE_CTRL_JTAG_PIN_STATUS                 0x04
  44 #define AICE_WRITE_CTRL_CUSTOM_DELAY                    0x0d
  45 #define AICE_WRITE_CTRL_BATCH_CTRL                              0x20
  46 #define AICE_WRITE_CTRL_BATCH_ITERATION                 0x21
  47 #define AICE_WRITE_CTRL_BATCH_DIM_SIZE                  0x22
  48 #define AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL             0x30
  49 #define AICE_WRITE_CTRL_BATCH_DATA_BUF0_CTRL    0x38
  50 #define AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL    0x3a
  51
  52 #define AICE_BATCH_COMMAND_BUFFER_0                     0x0
  53 #define AICE_BATCH_COMMAND_BUFFER_1                     0x1
  54 #define AICE_BATCH_COMMAND_BUFFER_2                     0x2
  55 #define AICE_BATCH_COMMAND_BUFFER_3                     0x3
  56 #define AICE_BATCH_DATA_BUFFER_0                        0x4
  57 #define AICE_BATCH_DATA_BUFFER_1                        0x5
  58 #define AICE_BATCH_DATA_BUFFER_2                        0x6
  59 #define AICE_BATCH_DATA_BUFFER_3                        0x7
  60
  61 /* Constants for AICE command WRITE_CTRL:TCK_CONTROL */
  62 #define AICE_TCK_CONTROL_TCK3048                0x08
  63 #define AICE_TCK_CONTROL_TCK_SCAN               0x10
  64
  65 /* Constants for AICE command WRITE_CTRL:JTAG_PIN_CONTROL */
  66 #define AICE_JTAG_PIN_CONTROL_SRST              0x01
  67 #define AICE_JTAG_PIN_CONTROL_TRST              0x02
  68 #define AICE_JTAG_PIN_CONTROL_STOP              0x04
  69 #define AICE_JTAG_PIN_CONTROL_RESTART   0x08
  70
  71 /* Constants for AICE command WRITE_CTRL:TCK_CONTROL */
  72 #define AICE_TCK_CONTROL_TCK_SCAN               0x10
  73
  74 /* Custom SRST/DBGI/TRST */
  75 #define AICE_CUSTOM_DELAY_SET_SRST              0x01
  76 #define AICE_CUSTOM_DELAY_CLEAN_SRST    0x02
  77 #define AICE_CUSTOM_DELAY_SET_DBGI              0x04
  78 #define AICE_CUSTOM_DELAY_CLEAN_DBGI    0x08
  79 #define AICE_CUSTOM_DELAY_SET_TRST              0x10
  80 #define AICE_CUSTOM_DELAY_CLEAN_TRST    0x20
  81
  82 struct aice_usb_handler_s {
  83         unsigned int usb_read_ep;
  84         unsigned int usb_write_ep;
  85         struct libusb_device_handle *usb_handle;
  86 };
  87
  88 struct cache_info {
  89         uint32_t set;
  90         uint32_t way;
  91         uint32_t line_size;
  92
  93         uint32_t log2_set;
  94         uint32_t log2_line_size;
  95 };
  96
  97 struct aice_nds32_info {
  98         uint32_t edm_version;
  99         uint32_t r0_backup;
 100         uint32_t r1_backup;
 101         uint32_t host_dtr_backup;
 102         uint32_t target_dtr_backup;
 103         uint32_t edmsw_backup;
 104         uint32_t edm_ctl_backup;
 105         bool debug_under_dex_on;
 106         bool dex_use_psw_on;
 107         bool host_dtr_valid;
 108         bool target_dtr_valid;
 109         enum nds_memory_access access_channel;
 110         enum nds_memory_select memory_select;
 111         enum aice_target_state_s core_state;
 112         bool cache_init;
 113         struct cache_info icache;
 114         struct cache_info dcache;
 115 };
 116
 117 extern struct aice_port_api_s aice_usb_api;
 118
 119 int aice_read_ctrl(uint32_t address, uint32_t *data);
 120 int aice_write_ctrl(uint32_t address, uint32_t data);
 121
 122 #endif /* OPENOCD_JTAG_AICE_AICE_USB_H */