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   1 /***************************************************************************
   2  *   Copyright (C) 2013 by Andes Technology                                *
   3  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18 #ifdef HAVE_CONFIG_H
  19 #include "config.h"
  20 #endif
  21
  22 #include <jtag/drivers/libusb_helper.h>
  23 #include <helper/log.h>
  24 #include <helper/time_support.h>
  25 #include <target/target.h>
  26 #include <jtag/jtag.h>
  27 #include <target/nds32_insn.h>
  28 #include <target/nds32_reg.h>
  29 #include "aice_usb.h"
  30
  31
  32 /* Global USB buffers */
  33 static uint8_t usb_in_buffer[AICE_IN_BUFFER_SIZE];
  34 static uint8_t usb_out_buffer[AICE_OUT_BUFFER_SIZE];
  35 static uint32_t jtag_clock;
  36 static struct aice_usb_handler_s aice_handler;
  37 /* AICE max retry times. If AICE command timeout, retry it. */
  38 static int aice_max_retry_times = 50;
  39 /* Default endian is little endian. */
  40 static enum aice_target_endian data_endian;
  41
  42 /* Constants for AICE command format length */
  43 #define AICE_FORMAT_HTDA        (3)
  44 #define AICE_FORMAT_HTDC        (7)
  45 #define AICE_FORMAT_HTDMA       (4)
  46 #define AICE_FORMAT_HTDMB       (8)
  47 #define AICE_FORMAT_HTDMC       (8)
  48 #define AICE_FORMAT_HTDMD       (12)
  49 #define AICE_FORMAT_DTHA        (6)
  50 #define AICE_FORMAT_DTHB        (2)
  51 #define AICE_FORMAT_DTHMA       (8)
  52 #define AICE_FORMAT_DTHMB       (4)
  53
  54 /* Constants for AICE command */
  55 static const uint8_t AICE_CMD_SCAN_CHAIN = 0x00;
  56 static const uint8_t AICE_CMD_T_READ_MISC = 0x20;
  57 static const uint8_t AICE_CMD_T_READ_EDMSR = 0x21;
  58 static const uint8_t AICE_CMD_T_READ_DTR = 0x22;
  59 static const uint8_t AICE_CMD_T_READ_MEM_B = 0x24;
  60 static const uint8_t AICE_CMD_T_READ_MEM_H = 0x25;
  61 static const uint8_t AICE_CMD_T_READ_MEM = 0x26;
  62 static const uint8_t AICE_CMD_T_FASTREAD_MEM = 0x27;
  63 static const uint8_t AICE_CMD_T_WRITE_MISC = 0x28;
  64 static const uint8_t AICE_CMD_T_WRITE_EDMSR     = 0x29;
  65 static const uint8_t AICE_CMD_T_WRITE_DTR = 0x2A;
  66 static const uint8_t AICE_CMD_T_WRITE_DIM = 0x2B;
  67 static const uint8_t AICE_CMD_T_WRITE_MEM_B = 0x2C;
  68 static const uint8_t AICE_CMD_T_WRITE_MEM_H = 0x2D;
  69 static const uint8_t AICE_CMD_T_WRITE_MEM = 0x2E;
  70 static const uint8_t AICE_CMD_T_FASTWRITE_MEM = 0x2F;
  71 static const uint8_t AICE_CMD_T_EXECUTE = 0x3E;
  72 static const uint8_t AICE_CMD_READ_CTRL = 0x50;
  73 static const uint8_t AICE_CMD_WRITE_CTRL = 0x51;
  74 static const uint8_t AICE_CMD_BATCH_BUFFER_READ = 0x60;
  75 static const uint8_t AICE_CMD_READ_DTR_TO_BUFFER = 0x61;
  76 static const uint8_t AICE_CMD_BATCH_BUFFER_WRITE = 0x68;
  77 static const uint8_t AICE_CMD_WRITE_DTR_FROM_BUFFER = 0x69;
  78
  79 /***************************************************************************/
  80 /* AICE commands' pack/unpack functions */
  81 static void aice_pack_htda(uint8_t cmd_code, uint8_t extra_word_length,
  82                 uint32_t address)
  83 {
  84         usb_out_buffer[0] = cmd_code;
  85         usb_out_buffer[1] = extra_word_length;
  86         usb_out_buffer[2] = (uint8_t)(address & 0xFF);
  87 }
  88
  89 static void aice_pack_htdc(uint8_t cmd_code, uint8_t extra_word_length,
  90                 uint32_t address, uint32_t word, enum aice_target_endian access_endian)
  91 {
  92         usb_out_buffer[0] = cmd_code;
  93         usb_out_buffer[1] = extra_word_length;
  94         usb_out_buffer[2] = (uint8_t)(address & 0xFF);
  95         if (access_endian == AICE_BIG_ENDIAN) {
  96                 usb_out_buffer[6] = (uint8_t)((word >> 24) & 0xFF);
  97                 usb_out_buffer[5] = (uint8_t)((word >> 16) & 0xFF);
  98                 usb_out_buffer[4] = (uint8_t)((word >> 8) & 0xFF);
  99                 usb_out_buffer[3] = (uint8_t)(word & 0xFF);
 100         } else {
 101                 usb_out_buffer[3] = (uint8_t)((word >> 24) & 0xFF);
 102                 usb_out_buffer[4] = (uint8_t)((word >> 16) & 0xFF);
 103                 usb_out_buffer[5] = (uint8_t)((word >> 8) & 0xFF);
 104                 usb_out_buffer[6] = (uint8_t)(word & 0xFF);
 105         }
 106 }
 107
 108 static void aice_pack_htdma(uint8_t cmd_code, uint8_t target_id,
 109                 uint8_t extra_word_length, uint32_t address)
 110 {
 111         usb_out_buffer[0] = cmd_code;
 112         usb_out_buffer[1] = target_id;
 113         usb_out_buffer[2] = extra_word_length;
 114         usb_out_buffer[3] = (uint8_t)(address & 0xFF);
 115 }
 116
 117 static void aice_pack_htdmb(uint8_t cmd_code, uint8_t target_id,
 118                 uint8_t extra_word_length, uint32_t address)
 119 {
 120         usb_out_buffer[0] = cmd_code;
 121         usb_out_buffer[1] = target_id;
 122         usb_out_buffer[2] = extra_word_length;
 123         usb_out_buffer[3] = 0;
 124         usb_out_buffer[4] = (uint8_t)((address >> 24) & 0xFF);
 125         usb_out_buffer[5] = (uint8_t)((address >> 16) & 0xFF);
 126         usb_out_buffer[6] = (uint8_t)((address >> 8) & 0xFF);
 127         usb_out_buffer[7] = (uint8_t)(address & 0xFF);
 128 }
 129
 130 static void aice_pack_htdmc(uint8_t cmd_code, uint8_t target_id,
 131                 uint8_t extra_word_length, uint32_t address, uint32_t word,
 132                 enum aice_target_endian access_endian)
 133 {
 134         usb_out_buffer[0] = cmd_code;
 135         usb_out_buffer[1] = target_id;
 136         usb_out_buffer[2] = extra_word_length;
 137         usb_out_buffer[3] = (uint8_t)(address & 0xFF);
 138         if (access_endian == AICE_BIG_ENDIAN) {
 139                 usb_out_buffer[7] = (uint8_t)((word >> 24) & 0xFF);
 140                 usb_out_buffer[6] = (uint8_t)((word >> 16) & 0xFF);
 141                 usb_out_buffer[5] = (uint8_t)((word >> 8) & 0xFF);
 142                 usb_out_buffer[4] = (uint8_t)(word & 0xFF);
 143         } else {
 144                 usb_out_buffer[4] = (uint8_t)((word >> 24) & 0xFF);
 145                 usb_out_buffer[5] = (uint8_t)((word >> 16) & 0xFF);
 146                 usb_out_buffer[6] = (uint8_t)((word >> 8) & 0xFF);
 147                 usb_out_buffer[7] = (uint8_t)(word & 0xFF);
 148         }
 149 }
 150
 151 static void aice_pack_htdmc_multiple_data(uint8_t cmd_code, uint8_t target_id,
 152                 uint8_t extra_word_length, uint32_t address, uint32_t *word,
 153                 uint8_t num_of_words, enum aice_target_endian access_endian)
 154 {
 155         usb_out_buffer[0] = cmd_code;
 156         usb_out_buffer[1] = target_id;
 157         usb_out_buffer[2] = extra_word_length;
 158         usb_out_buffer[3] = (uint8_t)(address & 0xFF);
 159
 160         uint8_t i;
 161         for (i = 0 ; i < num_of_words ; i++, word++) {
 162                 if (access_endian == AICE_BIG_ENDIAN) {
 163                         usb_out_buffer[7 + i * 4] = (uint8_t)((*word >> 24) & 0xFF);
 164                         usb_out_buffer[6 + i * 4] = (uint8_t)((*word >> 16) & 0xFF);
 165                         usb_out_buffer[5 + i * 4] = (uint8_t)((*word >> 8) & 0xFF);
 166                         usb_out_buffer[4 + i * 4] = (uint8_t)(*word & 0xFF);
 167                 } else {
 168                         usb_out_buffer[4 + i * 4] = (uint8_t)((*word >> 24) & 0xFF);
 169                         usb_out_buffer[5 + i * 4] = (uint8_t)((*word >> 16) & 0xFF);
 170                         usb_out_buffer[6 + i * 4] = (uint8_t)((*word >> 8) & 0xFF);
 171                         usb_out_buffer[7 + i * 4] = (uint8_t)(*word & 0xFF);
 172                 }
 173         }
 174 }
 175
 176 static void aice_pack_htdmd(uint8_t cmd_code, uint8_t target_id,
 177                 uint8_t extra_word_length, uint32_t address, uint32_t word,
 178                 enum aice_target_endian access_endian)
 179 {
 180         usb_out_buffer[0] = cmd_code;
 181         usb_out_buffer[1] = target_id;
 182         usb_out_buffer[2] = extra_word_length;
 183         usb_out_buffer[3] = 0;
 184         usb_out_buffer[4] = (uint8_t)((address >> 24) & 0xFF);
 185         usb_out_buffer[5] = (uint8_t)((address >> 16) & 0xFF);
 186         usb_out_buffer[6] = (uint8_t)((address >> 8) & 0xFF);
 187         usb_out_buffer[7] = (uint8_t)(address & 0xFF);
 188         if (access_endian == AICE_BIG_ENDIAN) {
 189                 usb_out_buffer[11] = (uint8_t)((word >> 24) & 0xFF);
 190                 usb_out_buffer[10] = (uint8_t)((word >> 16) & 0xFF);
 191                 usb_out_buffer[9] = (uint8_t)((word >> 8) & 0xFF);
 192                 usb_out_buffer[8] = (uint8_t)(word & 0xFF);
 193         } else {
 194                 usb_out_buffer[8] = (uint8_t)((word >> 24) & 0xFF);
 195                 usb_out_buffer[9] = (uint8_t)((word >> 16) & 0xFF);
 196                 usb_out_buffer[10] = (uint8_t)((word >> 8) & 0xFF);
 197                 usb_out_buffer[11] = (uint8_t)(word & 0xFF);
 198         }
 199 }
 200
 201 static void aice_pack_htdmd_multiple_data(uint8_t cmd_code, uint8_t target_id,
 202                 uint8_t extra_word_length, uint32_t address, const uint8_t *word,
 203                 enum aice_target_endian access_endian)
 204 {
 205         usb_out_buffer[0] = cmd_code;
 206         usb_out_buffer[1] = target_id;
 207         usb_out_buffer[2] = extra_word_length;
 208         usb_out_buffer[3] = 0;
 209         usb_out_buffer[4] = (uint8_t)((address >> 24) & 0xFF);
 210         usb_out_buffer[5] = (uint8_t)((address >> 16) & 0xFF);
 211         usb_out_buffer[6] = (uint8_t)((address >> 8) & 0xFF);
 212         usb_out_buffer[7] = (uint8_t)(address & 0xFF);
 213
 214         uint32_t i;
 215         /* num_of_words may be over 0xFF, so use uint32_t */
 216         uint32_t num_of_words = extra_word_length + 1;
 217
 218         for (i = 0 ; i < num_of_words ; i++, word += 4) {
 219                 if (access_endian == AICE_BIG_ENDIAN) {
 220                         usb_out_buffer[11 + i * 4] = word[3];
 221                         usb_out_buffer[10 + i * 4] = word[2];
 222                         usb_out_buffer[9 + i * 4] = word[1];
 223                         usb_out_buffer[8 + i * 4] = word[0];
 224                 } else {
 225                         usb_out_buffer[8 + i * 4] = word[3];
 226                         usb_out_buffer[9 + i * 4] = word[2];
 227                         usb_out_buffer[10 + i * 4] = word[1];
 228                         usb_out_buffer[11 + i * 4] = word[0];
 229                 }
 230         }
 231 }
 232
 233 static void aice_unpack_dtha(uint8_t *cmd_ack_code, uint8_t *extra_word_length,
 234                 uint32_t *word, enum aice_target_endian access_endian)
 235 {
 236         *cmd_ack_code = usb_in_buffer[0];
 237         *extra_word_length = usb_in_buffer[1];
 238
 239         if (access_endian == AICE_BIG_ENDIAN) {
 240                 *word = (usb_in_buffer[5] << 24) |
 241                         (usb_in_buffer[4] << 16) |
 242                         (usb_in_buffer[3] << 8) |
 243                         (usb_in_buffer[2]);
 244         } else {
 245                 *word = (usb_in_buffer[2] << 24) |
 246                         (usb_in_buffer[3] << 16) |
 247                         (usb_in_buffer[4] << 8) |
 248                         (usb_in_buffer[5]);
 249         }
 250 }
 251
 252 static void aice_unpack_dtha_multiple_data(uint8_t *cmd_ack_code,
 253                 uint8_t *extra_word_length, uint32_t *word, uint8_t num_of_words,
 254                 enum aice_target_endian access_endian)
 255 {
 256         *cmd_ack_code = usb_in_buffer[0];
 257         *extra_word_length = usb_in_buffer[1];
 258
 259         uint8_t i;
 260         for (i = 0 ; i < num_of_words ; i++, word++) {
 261                 if (access_endian == AICE_BIG_ENDIAN) {
 262                         *word = (usb_in_buffer[5 + i * 4] << 24) |
 263                                 (usb_in_buffer[4 + i * 4] << 16) |
 264                                 (usb_in_buffer[3 + i * 4] << 8) |
 265                                 (usb_in_buffer[2 + i * 4]);
 266                 } else {
 267                         *word = (usb_in_buffer[2 + i * 4] << 24) |
 268                                 (usb_in_buffer[3 + i * 4] << 16) |
 269                                 (usb_in_buffer[4 + i * 4] << 8) |
 270                                 (usb_in_buffer[5 + i * 4]);
 271                 }
 272         }
 273 }
 274
 275 static void aice_unpack_dthb(uint8_t *cmd_ack_code, uint8_t *extra_word_length)
 276 {
 277         *cmd_ack_code = usb_in_buffer[0];
 278         *extra_word_length = usb_in_buffer[1];
 279 }
 280
 281 static void aice_unpack_dthma(uint8_t *cmd_ack_code, uint8_t *target_id,
 282                 uint8_t *extra_word_length, uint32_t *word,
 283                 enum aice_target_endian access_endian)
 284 {
 285         *cmd_ack_code = usb_in_buffer[0];
 286         *target_id = usb_in_buffer[1];
 287         *extra_word_length = usb_in_buffer[2];
 288         if (access_endian == AICE_BIG_ENDIAN) {
 289                 *word = (usb_in_buffer[7] << 24) |
 290                         (usb_in_buffer[6] << 16) |
 291                         (usb_in_buffer[5] << 8) |
 292                         (usb_in_buffer[4]);
 293         } else {
 294                 *word = (usb_in_buffer[4] << 24) |
 295                         (usb_in_buffer[5] << 16) |
 296                         (usb_in_buffer[6] << 8) |
 297                         (usb_in_buffer[7]);
 298         }
 299 }
 300
 301 static void aice_unpack_dthma_multiple_data(uint8_t *cmd_ack_code,
 302                 uint8_t *target_id, uint8_t *extra_word_length, uint8_t *word,
 303                 enum aice_target_endian access_endian)
 304 {
 305         *cmd_ack_code = usb_in_buffer[0];
 306         *target_id = usb_in_buffer[1];
 307         *extra_word_length = usb_in_buffer[2];
 308         if (access_endian == AICE_BIG_ENDIAN) {
 309                 word[0] = usb_in_buffer[4];
 310                 word[1] = usb_in_buffer[5];
 311                 word[2] = usb_in_buffer[6];
 312                 word[3] = usb_in_buffer[7];
 313         } else {
 314                 word[0] = usb_in_buffer[7];
 315                 word[1] = usb_in_buffer[6];
 316                 word[2] = usb_in_buffer[5];
 317                 word[3] = usb_in_buffer[4];
 318         }
 319         word += 4;
 320
 321         uint8_t i;
 322         for (i = 0; i < *extra_word_length; i++) {
 323                 if (access_endian == AICE_BIG_ENDIAN) {
 324                         word[0] = usb_in_buffer[8 + i * 4];
 325                         word[1] = usb_in_buffer[9 + i * 4];
 326                         word[2] = usb_in_buffer[10 + i * 4];
 327                         word[3] = usb_in_buffer[11 + i * 4];
 328                 } else {
 329                         word[0] = usb_in_buffer[11 + i * 4];
 330                         word[1] = usb_in_buffer[10 + i * 4];
 331                         word[2] = usb_in_buffer[9 + i * 4];
 332                         word[3] = usb_in_buffer[8 + i * 4];
 333                 }
 334                 word += 4;
 335         }
 336 }
 337
 338 static void aice_unpack_dthmb(uint8_t *cmd_ack_code, uint8_t *target_id,
 339                 uint8_t *extra_word_length)
 340 {
 341         *cmd_ack_code = usb_in_buffer[0];
 342         *target_id = usb_in_buffer[1];
 343         *extra_word_length = usb_in_buffer[2];
 344 }
 345
 346 /***************************************************************************/
 347 /* End of AICE commands' pack/unpack functions */
 348
 349 /* calls the given usb_bulk_* function, allowing for the data to
 350  * trickle in with some timeouts  */
 351 static int usb_bulk_with_retries(
 352                         int (*f)(libusb_device_handle *, int, char *, int, int, int *),
 353                         libusb_device_handle *dev, int ep,
 354                         char *bytes, int size, int timeout, int *transferred)
 355 {
 356         int tries = 3, count = 0;
 357
 358         while (tries && (count < size)) {
 359                 int result, ret;
 360
 361                 ret = f(dev, ep, bytes + count, size - count, timeout, &result);
 362                 if (ERROR_OK == ret)
 363                         count += result;
 364                 else if ((ERROR_TIMEOUT_REACHED != ret) || !--tries)
 365                         return ret;
 366         }
 367
 368         *transferred = count;
 369         return ERROR_OK;
 370 }
 371
 372 static int wrap_usb_bulk_write(libusb_device_handle *dev, int ep,
 373                 char *buff, int size, int timeout, int *transferred)
 374 {
 375
 376         /* usb_bulk_write() takes const char *buff */
 377         jtag_libusb_bulk_write(dev, ep, buff, size, timeout, transferred);
 378
 379         return 0;
 380 }
 381
 382 static inline int usb_bulk_write_ex(libusb_device_handle *dev, int ep,
 383                 char *bytes, int size, int timeout)
 384 {
 385         int tr = 0;
 386
 387         usb_bulk_with_retries(&wrap_usb_bulk_write,
 388                         dev, ep, bytes, size, timeout, &tr);
 389         return tr;
 390 }
 391
 392 static inline int usb_bulk_read_ex(struct libusb_device_handle *dev, int ep,
 393                 char *bytes, int size, int timeout)
 394 {
 395         int tr = 0;
 396         usb_bulk_with_retries(&jtag_libusb_bulk_read,
 397                         dev, ep, bytes, size, timeout, &tr);
 398         return tr;
 399 }
 400
 401 /* Write data from out_buffer to USB. */
 402 static int aice_usb_write(uint8_t *out_buffer, int out_length)
 403 {
 404         int result;
 405
 406         if (out_length > AICE_OUT_BUFFER_SIZE) {
 407                 LOG_ERROR("aice_write illegal out_length=%i (max=%i)",
 408                                 out_length, AICE_OUT_BUFFER_SIZE);
 409                 return -1;
 410         }
 411
 412         result = usb_bulk_write_ex(aice_handler.usb_handle, aice_handler.usb_write_ep,
 413                         (char *)out_buffer, out_length, AICE_USB_TIMEOUT);
 414
 415         LOG_DEBUG_IO("aice_usb_write, out_length = %i, result = %i",
 416                         out_length, result);
 417
 418         return result;
 419 }
 420
 421 /* Read data from USB into in_buffer. */
 422 static int aice_usb_read(uint8_t *in_buffer, int expected_size)
 423 {
 424         int result = usb_bulk_read_ex(aice_handler.usb_handle, aice_handler.usb_read_ep,
 425                         (char *)in_buffer, expected_size, AICE_USB_TIMEOUT);
 426
 427         LOG_DEBUG_IO("aice_usb_read, result = %d", result);
 428
 429         return result;
 430 }
 431
 432 static uint8_t usb_out_packets_buffer[AICE_OUT_PACKETS_BUFFER_SIZE];
 433 static uint8_t usb_in_packets_buffer[AICE_IN_PACKETS_BUFFER_SIZE];
 434 static uint32_t usb_out_packets_buffer_length;
 435 static uint32_t usb_in_packets_buffer_length;
 436 static enum aice_command_mode aice_command_mode;
 437
 438 static int aice_batch_buffer_write(uint8_t buf_index, const uint8_t *word,
 439                 uint32_t num_of_words);
 440
 441 static int aice_usb_packet_flush(void)
 442 {
 443         if (usb_out_packets_buffer_length == 0)
 444                 return 0;
 445
 446         if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
 447                 LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_PACK)");
 448
 449                 if (aice_usb_write(usb_out_packets_buffer,
 450                                         usb_out_packets_buffer_length) < 0)
 451                         return ERROR_FAIL;
 452
 453                 if (aice_usb_read(usb_in_packets_buffer,
 454                                         usb_in_packets_buffer_length) < 0)
 455                         return ERROR_FAIL;
 456
 457                 usb_out_packets_buffer_length = 0;
 458                 usb_in_packets_buffer_length = 0;
 459
 460         } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
 461                 LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_BATCH)");
 462
 463                 /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */
 464                 if (aice_batch_buffer_write(AICE_BATCH_COMMAND_BUFFER_0,
 465                                 usb_out_packets_buffer,
 466                                 (usb_out_packets_buffer_length + 3) / 4) != ERROR_OK)
 467                         return ERROR_FAIL;
 468
 469                 usb_out_packets_buffer_length = 0;
 470                 usb_in_packets_buffer_length = 0;
 471
 472                 /* enable BATCH command */
 473                 aice_command_mode = AICE_COMMAND_MODE_NORMAL;
 474                 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL, 0x80000000) != ERROR_OK)
 475                         return ERROR_FAIL;
 476                 aice_command_mode = AICE_COMMAND_MODE_BATCH;
 477
 478                 /* wait 1 second (AICE bug, workaround) */
 479                 alive_sleep(1000);
 480
 481                 /* check status */
 482                 uint32_t i;
 483                 uint32_t batch_status;
 484
 485                 i = 0;
 486                 while (1) {
 487                         int retval = aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS, &batch_status);
 488                         if (retval != ERROR_OK)
 489                                 return retval;
 490
 491                         if (batch_status & 0x1)
 492                                 return ERROR_OK;
 493                         else if (batch_status & 0xE)
 494                                 return ERROR_FAIL;
 495
 496                         if ((i % 30) == 0)
 497                                 keep_alive();
 498
 499                         i++;
 500                 }
 501         }
 502
 503         return ERROR_OK;
 504 }
 505
 506 static int aice_usb_packet_append(uint8_t *out_buffer, int out_length, int in_length)
 507 {
 508         uint32_t max_packet_size = AICE_OUT_PACKETS_BUFFER_SIZE;
 509
 510         if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
 511                 max_packet_size = AICE_OUT_PACK_COMMAND_SIZE;
 512         } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
 513                 max_packet_size = AICE_OUT_BATCH_COMMAND_SIZE;
 514         } else {
 515                 /* AICE_COMMAND_MODE_NORMAL */
 516                 if (aice_usb_packet_flush() != ERROR_OK)
 517                         return ERROR_FAIL;
 518         }
 519
 520         if (usb_out_packets_buffer_length + out_length > max_packet_size)
 521                 if (aice_usb_packet_flush() != ERROR_OK) {
 522                         LOG_DEBUG("Flush usb packets failed");
 523                         return ERROR_FAIL;
 524                 }
 525
 526         LOG_DEBUG("Append usb packets 0x%02x", out_buffer[0]);
 527
 528         memcpy(usb_out_packets_buffer + usb_out_packets_buffer_length, out_buffer, out_length);
 529         usb_out_packets_buffer_length += out_length;
 530         usb_in_packets_buffer_length += in_length;
 531
 532         return ERROR_OK;
 533 }
 534
 535 /***************************************************************************/
 536 /* AICE commands */
 537 static int aice_reset_box(void)
 538 {
 539         if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS, 0x1) != ERROR_OK)
 540                 return ERROR_FAIL;
 541
 542         /* turn off FASTMODE */
 543         uint32_t pin_status;
 544         if (aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS, &pin_status)
 545                         != ERROR_OK)
 546                 return ERROR_FAIL;
 547
 548         if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS, pin_status & (~0x2))
 549                         != ERROR_OK)
 550                 return ERROR_FAIL;
 551
 552         return ERROR_OK;
 553 }
 554
 555 static int aice_scan_chain(uint32_t *id_codes, uint8_t *num_of_ids)
 556 {
 557         int retry_times = 0;
 558
 559         if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
 560                 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
 561                 aice_usb_packet_flush();
 562
 563         do {
 564                 aice_pack_htda(AICE_CMD_SCAN_CHAIN, 0x0F, 0x0);
 565
 566                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDA);
 567
 568                 LOG_DEBUG("SCAN_CHAIN, length: 0x0F");
 569
 570                 /** TODO: modify receive length */
 571                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHA);
 572                 if (AICE_FORMAT_DTHA != result) {
 573                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
 574                                         AICE_FORMAT_DTHA, result);
 575                         return ERROR_FAIL;
 576                 }
 577
 578                 uint8_t cmd_ack_code;
 579                 aice_unpack_dtha_multiple_data(&cmd_ack_code, num_of_ids, id_codes,
 580                                 0x10, AICE_LITTLE_ENDIAN);
 581
 582                 if (cmd_ack_code != AICE_CMD_SCAN_CHAIN) {
 583
 584                         if (retry_times > aice_max_retry_times) {
 585                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
 586                                                 AICE_CMD_SCAN_CHAIN, cmd_ack_code);
 587                                 return ERROR_FAIL;
 588                         }
 589
 590                         /* clear timeout and retry */
 591                         if (aice_reset_box() != ERROR_OK)
 592                                 return ERROR_FAIL;
 593
 594                         retry_times++;
 595                         continue;
 596                 }
 597
 598                 LOG_DEBUG("SCAN_CHAIN response, # of IDs: %" PRIu8, *num_of_ids);
 599
 600                 if (*num_of_ids == 0xFF) {
 601                         LOG_ERROR("No target connected");
 602                         return ERROR_FAIL;
 603                 } else if (*num_of_ids == AICE_MAX_NUM_CORE) {
 604                         LOG_INFO("The ice chain over 16 targets");
 605                 } else {
 606                         (*num_of_ids)++;
 607                 }
 608                 break;
 609         } while (1);
 610
 611         return ERROR_OK;
 612 }
 613
 614 int aice_read_ctrl(uint32_t address, uint32_t *data)
 615 {
 616         if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
 617                 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
 618                 aice_usb_packet_flush();
 619
 620         aice_pack_htda(AICE_CMD_READ_CTRL, 0, address);
 621
 622         aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDA);
 623
 624         LOG_DEBUG("READ_CTRL, address: 0x%" PRIx32, address);
 625
 626         int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHA);
 627         if (AICE_FORMAT_DTHA != result) {
 628                 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
 629                                 AICE_FORMAT_DTHA, result);
 630                 return ERROR_FAIL;
 631         }
 632
 633         uint8_t cmd_ack_code;
 634         uint8_t extra_length;
 635         aice_unpack_dtha(&cmd_ack_code, &extra_length, data, AICE_LITTLE_ENDIAN);
 636
 637         LOG_DEBUG("READ_CTRL response, data: 0x%" PRIx32, *data);
 638
 639         if (cmd_ack_code != AICE_CMD_READ_CTRL) {
 640                 LOG_ERROR("aice command error (command=0x%" PRIx32 ", response=0x%" PRIx8 ")",
 641                                 (uint32_t)AICE_CMD_READ_CTRL, cmd_ack_code);
 642                 return ERROR_FAIL;
 643         }
 644
 645         return ERROR_OK;
 646 }
 647
 648 int aice_write_ctrl(uint32_t address, uint32_t data)
 649 {
 650         if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
 651                 aice_usb_packet_flush();
 652         } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
 653                 aice_pack_htdc(AICE_CMD_WRITE_CTRL, 0, address, data, AICE_LITTLE_ENDIAN);
 654                 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDC,
 655                                 AICE_FORMAT_DTHB);
 656         }
 657
 658         aice_pack_htdc(AICE_CMD_WRITE_CTRL, 0, address, data, AICE_LITTLE_ENDIAN);
 659
 660         aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDC);
 661
 662         LOG_DEBUG("WRITE_CTRL, address: 0x%" PRIx32 ", data: 0x%" PRIx32, address, data);
 663
 664         int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHB);
 665         if (AICE_FORMAT_DTHB != result) {
 666                 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
 667                                 AICE_FORMAT_DTHB, result);
 668                 return ERROR_FAIL;
 669         }
 670
 671         uint8_t cmd_ack_code;
 672         uint8_t extra_length;
 673         aice_unpack_dthb(&cmd_ack_code, &extra_length);
 674
 675         LOG_DEBUG("WRITE_CTRL response");
 676
 677         if (cmd_ack_code != AICE_CMD_WRITE_CTRL) {
 678                 LOG_ERROR("aice command error (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
 679                                 AICE_CMD_WRITE_CTRL, cmd_ack_code);
 680                 return ERROR_FAIL;
 681         }
 682
 683         return ERROR_OK;
 684 }
 685
 686 static int aice_read_dtr(uint8_t target_id, uint32_t *data)
 687 {
 688         int retry_times = 0;
 689
 690         if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
 691                 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
 692                 aice_usb_packet_flush();
 693
 694         do {
 695                 aice_pack_htdma(AICE_CMD_T_READ_DTR, target_id, 0, 0);
 696
 697                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
 698
 699                 LOG_DEBUG("READ_DTR, COREID: %" PRIu8, target_id);
 700
 701                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
 702                 if (AICE_FORMAT_DTHMA != result) {
 703                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
 704                                         AICE_FORMAT_DTHMA, result);
 705                         return ERROR_FAIL;
 706                 }
 707
 708                 uint8_t cmd_ack_code;
 709                 uint8_t extra_length;
 710                 uint8_t res_target_id;
 711                 aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
 712                                 data, AICE_LITTLE_ENDIAN);
 713
 714                 if (cmd_ack_code == AICE_CMD_T_READ_DTR) {
 715                         LOG_DEBUG("READ_DTR response, data: 0x%" PRIx32, *data);
 716                         break;
 717                 } else {
 718
 719                         if (retry_times > aice_max_retry_times) {
 720                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
 721                                                 AICE_CMD_T_READ_DTR, cmd_ack_code);
 722                                 return ERROR_FAIL;
 723                         }
 724
 725                         /* clear timeout and retry */
 726                         if (aice_reset_box() != ERROR_OK)
 727                                 return ERROR_FAIL;
 728
 729                         retry_times++;
 730                 }
 731         } while (1);
 732
 733         return ERROR_OK;
 734 }
 735
 736 static int aice_read_dtr_to_buffer(uint8_t target_id, uint32_t buffer_idx)
 737 {
 738         int retry_times = 0;
 739
 740         if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
 741                 aice_usb_packet_flush();
 742         } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
 743                 aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER, target_id, 0, buffer_idx);
 744                 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMA,
 745                                 AICE_FORMAT_DTHMB);
 746         }
 747
 748         do {
 749                 aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER, target_id, 0, buffer_idx);
 750
 751                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
 752
 753                 LOG_DEBUG("READ_DTR_TO_BUFFER, COREID: %" PRIu8, target_id);
 754
 755                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
 756                 if (AICE_FORMAT_DTHMB != result) {
 757                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result);
 758                         return ERROR_FAIL;
 759                 }
 760
 761                 uint8_t cmd_ack_code;
 762                 uint8_t extra_length;
 763                 uint8_t res_target_id;
 764                 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
 765
 766                 if (cmd_ack_code == AICE_CMD_READ_DTR_TO_BUFFER) {
 767                         break;
 768                 } else {
 769                         if (retry_times > aice_max_retry_times) {
 770                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
 771                                                 AICE_CMD_READ_DTR_TO_BUFFER, cmd_ack_code);
 772
 773                                 return ERROR_FAIL;
 774                         }
 775
 776                         /* clear timeout and retry */
 777                         if (aice_reset_box() != ERROR_OK)
 778                                 return ERROR_FAIL;
 779
 780                         retry_times++;
 781                 }
 782         } while (1);
 783
 784         return ERROR_OK;
 785 }
 786
 787 static int aice_write_dtr(uint8_t target_id, uint32_t data)
 788 {
 789         int retry_times = 0;
 790
 791         if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
 792                 aice_usb_packet_flush();
 793         } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
 794                 aice_pack_htdmc(AICE_CMD_T_WRITE_DTR, target_id, 0, 0, data, AICE_LITTLE_ENDIAN);
 795                 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC,
 796                                 AICE_FORMAT_DTHMB);
 797         }
 798
 799         do {
 800                 aice_pack_htdmc(AICE_CMD_T_WRITE_DTR, target_id, 0, 0, data, AICE_LITTLE_ENDIAN);
 801
 802                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC);
 803
 804                 LOG_DEBUG("WRITE_DTR, COREID: %" PRIu8 ", data: 0x%" PRIx32, target_id, data);
 805
 806                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
 807                 if (AICE_FORMAT_DTHMB != result) {
 808                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result);
 809                         return ERROR_FAIL;
 810                 }
 811
 812                 uint8_t cmd_ack_code;
 813                 uint8_t extra_length;
 814                 uint8_t res_target_id;
 815                 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
 816
 817                 if (cmd_ack_code == AICE_CMD_T_WRITE_DTR) {
 818                         LOG_DEBUG("WRITE_DTR response");
 819                         break;
 820                 } else {
 821                         if (retry_times > aice_max_retry_times) {
 822                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
 823                                                 AICE_CMD_T_WRITE_DTR, cmd_ack_code);
 824
 825                                 return ERROR_FAIL;
 826                         }
 827
 828                         /* clear timeout and retry */
 829                         if (aice_reset_box() != ERROR_OK)
 830                                 return ERROR_FAIL;
 831
 832                         retry_times++;
 833                 }
 834         } while (1);
 835
 836         return ERROR_OK;
 837 }
 838
 839 static int aice_write_dtr_from_buffer(uint8_t target_id, uint32_t buffer_idx)
 840 {
 841         int retry_times = 0;
 842
 843         if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
 844                 aice_usb_packet_flush();
 845         } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
 846                 aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER, target_id, 0, buffer_idx);
 847                 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMA,
 848                                 AICE_FORMAT_DTHMB);
 849         }
 850
 851         do {
 852                 aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER, target_id, 0, buffer_idx);
 853
 854                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
 855
 856                 LOG_DEBUG("WRITE_DTR_FROM_BUFFER, COREID: %" PRIu8 "", target_id);
 857
 858                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
 859                 if (AICE_FORMAT_DTHMB != result) {
 860                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result);
 861                         return ERROR_FAIL;
 862                 }
 863
 864                 uint8_t cmd_ack_code;
 865                 uint8_t extra_length;
 866                 uint8_t res_target_id;
 867                 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
 868
 869                 if (cmd_ack_code == AICE_CMD_WRITE_DTR_FROM_BUFFER) {
 870                         break;
 871                 } else {
 872                         if (retry_times > aice_max_retry_times) {
 873                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
 874                                                 AICE_CMD_WRITE_DTR_FROM_BUFFER, cmd_ack_code);
 875
 876                                 return ERROR_FAIL;
 877                         }
 878
 879                         /* clear timeout and retry */
 880                         if (aice_reset_box() != ERROR_OK)
 881                                 return ERROR_FAIL;
 882
 883                         retry_times++;
 884                 }
 885         } while (1);
 886
 887         return ERROR_OK;
 888 }
 889
 890 static int aice_read_misc(uint8_t target_id, uint32_t address, uint32_t *data)
 891 {
 892         int retry_times = 0;
 893
 894         if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
 895                 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
 896                 aice_usb_packet_flush();
 897
 898         do {
 899                 aice_pack_htdma(AICE_CMD_T_READ_MISC, target_id, 0, address);
 900
 901                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
 902
 903                 LOG_DEBUG("READ_MISC, COREID: %" PRIu8 ", address: 0x%" PRIx32, target_id, address);
 904
 905                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
 906                 if (AICE_FORMAT_DTHMA != result) {
 907                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
 908                                         AICE_FORMAT_DTHMA, result);
 909                         return ERROR_AICE_DISCONNECT;
 910                 }
 911
 912                 uint8_t cmd_ack_code;
 913                 uint8_t extra_length;
 914                 uint8_t res_target_id;
 915                 aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
 916                                 data, AICE_LITTLE_ENDIAN);
 917
 918                 if (cmd_ack_code == AICE_CMD_T_READ_MISC) {
 919                         LOG_DEBUG("READ_MISC response, data: 0x%" PRIx32, *data);
 920                         break;
 921                 } else {
 922                         if (retry_times > aice_max_retry_times) {
 923                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
 924                                                 AICE_CMD_T_READ_MISC, cmd_ack_code);
 925                                 return ERROR_FAIL;
 926                         }
 927
 928                         /* clear timeout and retry */
 929                         if (aice_reset_box() != ERROR_OK)
 930                                 return ERROR_FAIL;
 931
 932                         retry_times++;
 933                 }
 934         } while (1);
 935
 936         return ERROR_OK;
 937 }
 938
 939 static int aice_write_misc(uint8_t target_id, uint32_t address, uint32_t data)
 940 {
 941         int retry_times = 0;
 942
 943         if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
 944                 aice_usb_packet_flush();
 945         } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
 946                 aice_pack_htdmc(AICE_CMD_T_WRITE_MISC, target_id, 0, address, data,
 947                                 AICE_LITTLE_ENDIAN);
 948                 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC,
 949                                 AICE_FORMAT_DTHMB);
 950         }
 951
 952         do {
 953                 aice_pack_htdmc(AICE_CMD_T_WRITE_MISC, target_id, 0, address,
 954                                 data, AICE_LITTLE_ENDIAN);
 955
 956                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC);
 957
 958                 LOG_DEBUG("WRITE_MISC, COREID: %" PRIu8 ", address: 0x%" PRIx32 ", data: 0x%" PRIx32,
 959                                 target_id, address, data);
 960
 961                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
 962                 if (AICE_FORMAT_DTHMB != result) {
 963                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
 964                                         AICE_FORMAT_DTHMB, result);
 965                         return ERROR_FAIL;
 966                 }
 967
 968                 uint8_t cmd_ack_code;
 969                 uint8_t extra_length;
 970                 uint8_t res_target_id;
 971                 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
 972
 973                 if (cmd_ack_code == AICE_CMD_T_WRITE_MISC) {
 974                         LOG_DEBUG("WRITE_MISC response");
 975                         break;
 976                 } else {
 977                         if (retry_times > aice_max_retry_times) {
 978                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
 979                                                 AICE_CMD_T_WRITE_MISC, cmd_ack_code);
 980
 981                                 return ERROR_FAIL;
 982                         }
 983
 984                         /* clear timeout and retry */
 985                         if (aice_reset_box() != ERROR_OK)
 986                                 return ERROR_FAIL;
 987
 988                         retry_times++;
 989                 }
 990         } while (1);
 991
 992         return ERROR_OK;
 993 }
 994
 995 static int aice_read_edmsr(uint8_t target_id, uint32_t address, uint32_t *data)
 996 {
 997         int retry_times = 0;
 998
 999         if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1000                 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
1001                 aice_usb_packet_flush();
1002
1003         do {
1004                 aice_pack_htdma(AICE_CMD_T_READ_EDMSR, target_id, 0, address);
1005
1006                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
1007
1008                 LOG_DEBUG("READ_EDMSR, COREID: %" PRIu8 ", address: 0x%" PRIx32, target_id, address);
1009
1010                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
1011                 if (AICE_FORMAT_DTHMA != result) {
1012                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1013                                         AICE_FORMAT_DTHMA, result);
1014                         return ERROR_FAIL;
1015                 }
1016
1017                 uint8_t cmd_ack_code;
1018                 uint8_t extra_length;
1019                 uint8_t res_target_id;
1020                 aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
1021                                 data, AICE_LITTLE_ENDIAN);
1022
1023                 if (cmd_ack_code == AICE_CMD_T_READ_EDMSR) {
1024                         LOG_DEBUG("READ_EDMSR response, data: 0x%" PRIx32, *data);
1025                         break;
1026                 } else {
1027                         if (retry_times > aice_max_retry_times) {
1028                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1029                                                 AICE_CMD_T_READ_EDMSR, cmd_ack_code);
1030
1031                                 return ERROR_FAIL;
1032                         }
1033
1034                         /* clear timeout and retry */
1035                         if (aice_reset_box() != ERROR_OK)
1036                                 return ERROR_FAIL;
1037
1038                         retry_times++;
1039                 }
1040         } while (1);
1041
1042         return ERROR_OK;
1043 }
1044
1045 static int aice_write_edmsr(uint8_t target_id, uint32_t address, uint32_t data)
1046 {
1047         int retry_times = 0;
1048
1049         if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
1050                 aice_usb_packet_flush();
1051         } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
1052                 aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR, target_id, 0, address, data,
1053                                 AICE_LITTLE_ENDIAN);
1054                 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC,
1055                                 AICE_FORMAT_DTHMB);
1056         }
1057
1058         do {
1059                 aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR, target_id, 0, address,
1060                                 data, AICE_LITTLE_ENDIAN);
1061
1062                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC);
1063
1064                 LOG_DEBUG("WRITE_EDMSR, COREID: %" PRIu8 ", address: 0x%" PRIx32 ", data: 0x%" PRIx32,
1065                                 target_id, address, data);
1066
1067                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1068                 if (AICE_FORMAT_DTHMB != result) {
1069                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1070                                         AICE_FORMAT_DTHMB, result);
1071                         return ERROR_FAIL;
1072                 }
1073
1074                 uint8_t cmd_ack_code;
1075                 uint8_t extra_length;
1076                 uint8_t res_target_id;
1077                 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1078
1079                 if (cmd_ack_code == AICE_CMD_T_WRITE_EDMSR) {
1080                         LOG_DEBUG("WRITE_EDMSR response");
1081                         break;
1082                 } else {
1083                         if (retry_times > aice_max_retry_times) {
1084                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1085                                                 AICE_CMD_T_WRITE_EDMSR, cmd_ack_code);
1086
1087                                 return ERROR_FAIL;
1088                         }
1089
1090                         /* clear timeout and retry */
1091                         if (aice_reset_box() != ERROR_OK)
1092                                 return ERROR_FAIL;
1093
1094                         retry_times++;
1095                 }
1096         } while (1);
1097
1098         return ERROR_OK;
1099 }
1100
1101 static int aice_switch_to_big_endian(uint32_t *word, uint8_t num_of_words)
1102 {
1103         uint32_t tmp;
1104
1105         for (uint8_t i = 0 ; i < num_of_words ; i++) {
1106                 tmp = ((word[i] >> 24) & 0x000000FF) |
1107                         ((word[i] >>  8) & 0x0000FF00) |
1108                         ((word[i] <<  8) & 0x00FF0000) |
1109                         ((word[i] << 24) & 0xFF000000);
1110                 word[i] = tmp;
1111         }
1112
1113         return ERROR_OK;
1114 }
1115
1116 static int aice_write_dim(uint8_t target_id, uint32_t *word, uint8_t num_of_words)
1117 {
1118         uint32_t big_endian_word[4];
1119         int retry_times = 0;
1120
1121         /** instruction is big-endian */
1122         memcpy(big_endian_word, word, sizeof(big_endian_word));
1123         aice_switch_to_big_endian(big_endian_word, num_of_words);
1124
1125         if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
1126                 aice_usb_packet_flush();
1127         } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
1128                 aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM, target_id,
1129                                 num_of_words - 1, 0, big_endian_word, num_of_words,
1130                                 AICE_LITTLE_ENDIAN);
1131                 return aice_usb_packet_append(usb_out_buffer,
1132                                 AICE_FORMAT_HTDMC + (num_of_words - 1) * 4,
1133                                 AICE_FORMAT_DTHMB);
1134         }
1135
1136         do {
1137                 aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM, target_id, num_of_words - 1, 0,
1138                                 big_endian_word, num_of_words, AICE_LITTLE_ENDIAN);
1139
1140                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC + (num_of_words - 1) * 4);
1141
1142                 LOG_DEBUG("WRITE_DIM, COREID: %" PRIu8
1143                                 ", data: 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32,
1144                                 target_id,
1145                                 big_endian_word[0],
1146                                 big_endian_word[1],
1147                                 big_endian_word[2],
1148                                 big_endian_word[3]);
1149
1150                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1151                 if (AICE_FORMAT_DTHMB != result) {
1152                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result);
1153                         return ERROR_FAIL;
1154                 }
1155
1156                 uint8_t cmd_ack_code;
1157                 uint8_t extra_length;
1158                 uint8_t res_target_id;
1159                 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1160
1161
1162                 if (cmd_ack_code == AICE_CMD_T_WRITE_DIM) {
1163                         LOG_DEBUG("WRITE_DIM response");
1164                         break;
1165                 } else {
1166                         if (retry_times > aice_max_retry_times) {
1167                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8
1168                                                 ", response=0x%" PRIx8 ")",
1169                                                 AICE_CMD_T_WRITE_DIM, cmd_ack_code);
1170
1171                                 return ERROR_FAIL;
1172                         }
1173
1174                         /* clear timeout and retry */
1175                         if (aice_reset_box() != ERROR_OK)
1176                                 return ERROR_FAIL;
1177
1178                         retry_times++;
1179                 }
1180         } while (1);
1181
1182         return ERROR_OK;
1183 }
1184
1185 static int aice_do_execute(uint8_t target_id)
1186 {
1187         int retry_times = 0;
1188
1189         if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
1190                 aice_usb_packet_flush();
1191         } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
1192                 aice_pack_htdmc(AICE_CMD_T_EXECUTE, target_id, 0, 0, 0, AICE_LITTLE_ENDIAN);
1193                 return aice_usb_packet_append(usb_out_buffer,
1194                                 AICE_FORMAT_HTDMC,
1195                                 AICE_FORMAT_DTHMB);
1196         }
1197
1198         do {
1199                 aice_pack_htdmc(AICE_CMD_T_EXECUTE, target_id, 0, 0, 0, AICE_LITTLE_ENDIAN);
1200
1201                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC);
1202
1203                 LOG_DEBUG("EXECUTE, COREID: %" PRIu8 "", target_id);
1204
1205                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1206                 if (AICE_FORMAT_DTHMB != result) {
1207                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1208                                         AICE_FORMAT_DTHMB, result);
1209                         return ERROR_FAIL;
1210                 }
1211
1212                 uint8_t cmd_ack_code;
1213                 uint8_t extra_length;
1214                 uint8_t res_target_id;
1215                 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1216
1217                 if (cmd_ack_code == AICE_CMD_T_EXECUTE) {
1218                         LOG_DEBUG("EXECUTE response");
1219                         break;
1220                 } else {
1221                         if (retry_times > aice_max_retry_times) {
1222                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1223                                                 AICE_CMD_T_EXECUTE, cmd_ack_code);
1224
1225                                 return ERROR_FAIL;
1226                         }
1227
1228                         /* clear timeout and retry */
1229                         if (aice_reset_box() != ERROR_OK)
1230                                 return ERROR_FAIL;
1231
1232                         retry_times++;
1233                 }
1234         } while (1);
1235
1236         return ERROR_OK;
1237 }
1238
1239 static int aice_write_mem_b(uint8_t target_id, uint32_t address, uint32_t data)
1240 {
1241         int retry_times = 0;
1242
1243         LOG_DEBUG("WRITE_MEM_B, COREID: %" PRIu8 ", ADDRESS %08" PRIx32 "  VALUE %08" PRIx32,
1244                         target_id,
1245                         address,
1246                         data);
1247
1248         if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1249                 (AICE_COMMAND_MODE_BATCH == aice_command_mode)) {
1250                 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B, target_id, 0, address,
1251                                 data & 0x000000FF, data_endian);
1252                 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD,
1253                                 AICE_FORMAT_DTHMB);
1254         } else {
1255                 do {
1256                         aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B, target_id, 0,
1257                                         address, data & 0x000000FF, data_endian);
1258                         aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD);
1259
1260                         int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1261                         if (AICE_FORMAT_DTHMB != result) {
1262                                 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result);
1263                                 return ERROR_FAIL;
1264                         }
1265
1266                         uint8_t cmd_ack_code;
1267                         uint8_t extra_length;
1268                         uint8_t res_target_id;
1269                         aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1270
1271                         if (cmd_ack_code == AICE_CMD_T_WRITE_MEM_B) {
1272                                 break;
1273                         } else {
1274                                 if (retry_times > aice_max_retry_times) {
1275                                         LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1276                                                         AICE_CMD_T_WRITE_MEM_B, cmd_ack_code);
1277
1278                                         return ERROR_FAIL;
1279                                 }
1280
1281                                 /* clear timeout and retry */
1282                                 if (aice_reset_box() != ERROR_OK)
1283                                         return ERROR_FAIL;
1284
1285                                 retry_times++;
1286                         }
1287                 } while (1);
1288         }
1289
1290         return ERROR_OK;
1291 }
1292
1293 static int aice_write_mem_h(uint8_t target_id, uint32_t address, uint32_t data)
1294 {
1295         int retry_times = 0;
1296
1297         LOG_DEBUG("WRITE_MEM_H, COREID: %" PRIu8 ", ADDRESS %08" PRIx32 "  VALUE %08" PRIx32,
1298                         target_id,
1299                         address,
1300                         data);
1301
1302         if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1303                 (AICE_COMMAND_MODE_BATCH == aice_command_mode)) {
1304                 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H, target_id, 0,
1305                                 (address >> 1) & 0x7FFFFFFF, data & 0x0000FFFF, data_endian);
1306                 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD,
1307                                 AICE_FORMAT_DTHMB);
1308         } else {
1309                 do {
1310                         aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H, target_id, 0,
1311                                         (address >> 1) & 0x7FFFFFFF, data & 0x0000FFFF, data_endian);
1312                         aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD);
1313
1314                         int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1315                         if (AICE_FORMAT_DTHMB != result) {
1316                                 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1317                                                 AICE_FORMAT_DTHMB, result);
1318                                 return ERROR_FAIL;
1319                         }
1320
1321                         uint8_t cmd_ack_code;
1322                         uint8_t extra_length;
1323                         uint8_t res_target_id;
1324                         aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1325
1326                         if (cmd_ack_code == AICE_CMD_T_WRITE_MEM_H) {
1327                                 break;
1328                         } else {
1329                                 if (retry_times > aice_max_retry_times) {
1330                                         LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1331                                                         AICE_CMD_T_WRITE_MEM_H, cmd_ack_code);
1332
1333                                         return ERROR_FAIL;
1334                                 }
1335
1336                                 /* clear timeout and retry */
1337                                 if (aice_reset_box() != ERROR_OK)
1338                                         return ERROR_FAIL;
1339
1340                                 retry_times++;
1341                         }
1342                 } while (1);
1343         }
1344
1345         return ERROR_OK;
1346 }
1347
1348 static int aice_write_mem(uint8_t target_id, uint32_t address, uint32_t data)
1349 {
1350         int retry_times = 0;
1351
1352         LOG_DEBUG("WRITE_MEM, COREID: %" PRIu8 ", ADDRESS %08" PRIx32 "  VALUE %08" PRIx32,
1353                         target_id,
1354                         address,
1355                         data);
1356
1357         if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1358                 (AICE_COMMAND_MODE_BATCH == aice_command_mode)) {
1359                 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM, target_id, 0,
1360                                 (address >> 2) & 0x3FFFFFFF, data, data_endian);
1361                 return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD,
1362                                 AICE_FORMAT_DTHMB);
1363         } else {
1364                 do {
1365                         aice_pack_htdmd(AICE_CMD_T_WRITE_MEM, target_id, 0,
1366                                         (address >> 2) & 0x3FFFFFFF, data, data_endian);
1367                         aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD);
1368
1369                         int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1370                         if (AICE_FORMAT_DTHMB != result) {
1371                                 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1372                                                 AICE_FORMAT_DTHMB, result);
1373                                 return ERROR_FAIL;
1374                         }
1375
1376                         uint8_t cmd_ack_code;
1377                         uint8_t extra_length;
1378                         uint8_t res_target_id;
1379                         aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1380
1381                         if (cmd_ack_code == AICE_CMD_T_WRITE_MEM) {
1382                                 break;
1383                         } else {
1384                                 if (retry_times > aice_max_retry_times) {
1385                                         LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1386                                                         AICE_CMD_T_WRITE_MEM, cmd_ack_code);
1387
1388                                         return ERROR_FAIL;
1389                                 }
1390
1391                                 /* clear timeout and retry */
1392                                 if (aice_reset_box() != ERROR_OK)
1393                                         return ERROR_FAIL;
1394
1395                                 retry_times++;
1396                         }
1397                 } while (1);
1398         }
1399
1400         return ERROR_OK;
1401 }
1402
1403 static int aice_fastread_mem(uint8_t target_id, uint8_t *word, uint32_t num_of_words)
1404 {
1405         int retry_times = 0;
1406
1407         if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1408                 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
1409                 aice_usb_packet_flush();
1410
1411         do {
1412                 aice_pack_htdmb(AICE_CMD_T_FASTREAD_MEM, target_id, num_of_words - 1, 0);
1413
1414                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB);
1415
1416                 LOG_DEBUG("FASTREAD_MEM, COREID: %" PRIu8 ", # of DATA %08" PRIx32,
1417                                 target_id, num_of_words);
1418
1419                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA + (num_of_words - 1) * 4);
1420                 if (result < 0) {
1421                         LOG_ERROR("aice_usb_read failed (requested=%" PRIu32 ", result=%d)",
1422                                         AICE_FORMAT_DTHMA + (num_of_words - 1) * 4, result);
1423                         return ERROR_FAIL;
1424                 }
1425
1426                 uint8_t cmd_ack_code;
1427                 uint8_t extra_length;
1428                 uint8_t res_target_id;
1429                 aice_unpack_dthma_multiple_data(&cmd_ack_code, &res_target_id,
1430                                 &extra_length, word, data_endian);
1431
1432                 if (cmd_ack_code == AICE_CMD_T_FASTREAD_MEM) {
1433                         break;
1434                 } else {
1435                         if (retry_times > aice_max_retry_times) {
1436                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1437                                                 AICE_CMD_T_FASTREAD_MEM, cmd_ack_code);
1438
1439                                 return ERROR_FAIL;
1440                         }
1441
1442                         /* clear timeout and retry */
1443                         if (aice_reset_box() != ERROR_OK)
1444                                 return ERROR_FAIL;
1445
1446                         retry_times++;
1447                 }
1448         } while (1);
1449
1450         return ERROR_OK;
1451 }
1452
1453 static int aice_fastwrite_mem(uint8_t target_id, const uint8_t *word, uint32_t num_of_words)
1454 {
1455         int retry_times = 0;
1456
1457         if (AICE_COMMAND_MODE_PACK == aice_command_mode) {
1458                 aice_usb_packet_flush();
1459         } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) {
1460                 aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM, target_id,
1461                                 num_of_words - 1, 0, word, data_endian);
1462                 return aice_usb_packet_append(usb_out_buffer,
1463                                 AICE_FORMAT_HTDMD + (num_of_words - 1) * 4,
1464                                 AICE_FORMAT_DTHMB);
1465         }
1466
1467         do {
1468                 aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM, target_id,
1469                                 num_of_words - 1, 0, word, data_endian);
1470
1471                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD + (num_of_words - 1) * 4);
1472
1473                 LOG_DEBUG("FASTWRITE_MEM, COREID: %" PRIu8 ", # of DATA %08" PRIx32,
1474                                 target_id, num_of_words);
1475
1476                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1477                 if (AICE_FORMAT_DTHMB != result) {
1478                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1479                                         AICE_FORMAT_DTHMB, result);
1480                         return ERROR_FAIL;
1481                 }
1482
1483                 uint8_t cmd_ack_code;
1484                 uint8_t extra_length;
1485                 uint8_t res_target_id;
1486                 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1487
1488                 if (cmd_ack_code == AICE_CMD_T_FASTWRITE_MEM) {
1489                         break;
1490                 } else {
1491                         if (retry_times > aice_max_retry_times) {
1492                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1493                                                 AICE_CMD_T_FASTWRITE_MEM, cmd_ack_code);
1494
1495                                 return ERROR_FAIL;
1496                         }
1497
1498                         /* clear timeout and retry */
1499                         if (aice_reset_box() != ERROR_OK)
1500                                 return ERROR_FAIL;
1501
1502                         retry_times++;
1503                 }
1504         } while (1);
1505
1506         return ERROR_OK;
1507 }
1508
1509 static int aice_read_mem_b(uint8_t target_id, uint32_t address, uint32_t *data)
1510 {
1511         int retry_times = 0;
1512
1513         if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1514                 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
1515                 aice_usb_packet_flush();
1516
1517         do {
1518                 aice_pack_htdmb(AICE_CMD_T_READ_MEM_B, target_id, 0, address);
1519
1520                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB);
1521
1522                 LOG_DEBUG("READ_MEM_B, COREID: %" PRIu8 "", target_id);
1523
1524                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
1525                 if (AICE_FORMAT_DTHMA != result) {
1526                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1527                                         AICE_FORMAT_DTHMA, result);
1528                         return ERROR_FAIL;
1529                 }
1530
1531                 uint8_t cmd_ack_code;
1532                 uint8_t extra_length;
1533                 uint8_t res_target_id;
1534                 aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
1535                                 data, data_endian);
1536
1537                 if (cmd_ack_code == AICE_CMD_T_READ_MEM_B) {
1538                         LOG_DEBUG("READ_MEM_B response, data: 0x%02" PRIx32, *data);
1539                         break;
1540                 } else {
1541                         if (retry_times > aice_max_retry_times) {
1542                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1543                                                 AICE_CMD_T_READ_MEM_B, cmd_ack_code);
1544
1545                                 return ERROR_FAIL;
1546                         }
1547
1548                         /* clear timeout and retry */
1549                         if (aice_reset_box() != ERROR_OK)
1550                                 return ERROR_FAIL;
1551
1552                         retry_times++;
1553                 }
1554         } while (1);
1555
1556         return ERROR_OK;
1557 }
1558
1559 static int aice_read_mem_h(uint8_t target_id, uint32_t address, uint32_t *data)
1560 {
1561         int retry_times = 0;
1562
1563         if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1564                 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
1565                 aice_usb_packet_flush();
1566
1567         do {
1568                 aice_pack_htdmb(AICE_CMD_T_READ_MEM_H, target_id, 0, (address >> 1) & 0x7FFFFFFF);
1569
1570                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB);
1571
1572                 LOG_DEBUG("READ_MEM_H, CORE_ID: %" PRIu8 "", target_id);
1573
1574                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
1575                 if (AICE_FORMAT_DTHMA != result) {
1576                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1577                                         AICE_FORMAT_DTHMA, result);
1578                         return ERROR_FAIL;
1579                 }
1580
1581                 uint8_t cmd_ack_code;
1582                 uint8_t extra_length;
1583                 uint8_t res_target_id;
1584                 aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
1585                                 data, data_endian);
1586
1587                 if (cmd_ack_code == AICE_CMD_T_READ_MEM_H) {
1588                         LOG_DEBUG("READ_MEM_H response, data: 0x%" PRIx32, *data);
1589                         break;
1590                 } else {
1591                         if (retry_times > aice_max_retry_times) {
1592                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1593                                                 AICE_CMD_T_READ_MEM_H, cmd_ack_code);
1594
1595                                 return ERROR_FAIL;
1596                         }
1597
1598                         /* clear timeout and retry */
1599                         if (aice_reset_box() != ERROR_OK)
1600                                 return ERROR_FAIL;
1601
1602                         retry_times++;
1603                 }
1604         } while (1);
1605
1606         return ERROR_OK;
1607 }
1608
1609 static int aice_read_mem(uint8_t target_id, uint32_t address, uint32_t *data)
1610 {
1611         int retry_times = 0;
1612
1613         if ((AICE_COMMAND_MODE_PACK == aice_command_mode) ||
1614                 (AICE_COMMAND_MODE_BATCH == aice_command_mode))
1615                 aice_usb_packet_flush();
1616
1617         do {
1618                 aice_pack_htdmb(AICE_CMD_T_READ_MEM, target_id, 0,
1619                                 (address >> 2) & 0x3FFFFFFF);
1620
1621                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB);
1622
1623                 LOG_DEBUG("READ_MEM, COREID: %" PRIu8 "", target_id);
1624
1625                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
1626                 if (AICE_FORMAT_DTHMA != result) {
1627                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1628                                         AICE_FORMAT_DTHMA, result);
1629                         return ERROR_FAIL;
1630                 }
1631
1632                 uint8_t cmd_ack_code;
1633                 uint8_t extra_length;
1634                 uint8_t res_target_id;
1635                 aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
1636                                 data, data_endian);
1637
1638                 if (cmd_ack_code == AICE_CMD_T_READ_MEM) {
1639                         LOG_DEBUG("READ_MEM response, data: 0x%" PRIx32, *data);
1640                         break;
1641                 } else {
1642                         if (retry_times > aice_max_retry_times) {
1643                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1644                                                 AICE_CMD_T_READ_MEM, cmd_ack_code);
1645
1646                                 return ERROR_FAIL;
1647                         }
1648
1649                         /* clear timeout and retry */
1650                         if (aice_reset_box() != ERROR_OK)
1651                                 return ERROR_FAIL;
1652
1653                         retry_times++;
1654                 }
1655         } while (1);
1656
1657         return ERROR_OK;
1658 }
1659
1660 static int aice_batch_buffer_read(uint8_t buf_index, uint32_t *word, uint32_t num_of_words)
1661 {
1662         int retry_times = 0;
1663
1664         do {
1665                 aice_pack_htdma(AICE_CMD_BATCH_BUFFER_READ, 0, num_of_words - 1, buf_index);
1666
1667                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
1668
1669                 LOG_DEBUG("BATCH_BUFFER_READ, # of DATA %08" PRIx32, num_of_words);
1670
1671                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA + (num_of_words - 1) * 4);
1672                 if (result < 0) {
1673                         LOG_ERROR("aice_usb_read failed (requested=%" PRIu32 ", result=%d)",
1674                                         AICE_FORMAT_DTHMA + (num_of_words - 1) * 4, result);
1675                         return ERROR_FAIL;
1676                 }
1677
1678                 uint8_t cmd_ack_code;
1679                 uint8_t extra_length;
1680                 uint8_t res_target_id;
1681                 aice_unpack_dthma_multiple_data(&cmd_ack_code, &res_target_id,
1682                                 &extra_length, (uint8_t *)word, data_endian);
1683
1684                 if (cmd_ack_code == AICE_CMD_BATCH_BUFFER_READ) {
1685                         break;
1686                 } else {
1687                         if (retry_times > aice_max_retry_times) {
1688                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1689                                                 AICE_CMD_BATCH_BUFFER_READ, cmd_ack_code);
1690
1691                                 return ERROR_FAIL;
1692                         }
1693
1694                         /* clear timeout and retry */
1695                         if (aice_reset_box() != ERROR_OK)
1696                                 return ERROR_FAIL;
1697
1698                         retry_times++;
1699                 }
1700         } while (1);
1701
1702         return ERROR_OK;
1703 }
1704
1705 int aice_batch_buffer_write(uint8_t buf_index, const uint8_t *word, uint32_t num_of_words)
1706 {
1707         int retry_times = 0;
1708
1709         if (num_of_words == 0)
1710                 return ERROR_OK;
1711
1712         do {
1713                 /* only pack AICE_CMD_BATCH_BUFFER_WRITE command header */
1714                 aice_pack_htdmc(AICE_CMD_BATCH_BUFFER_WRITE, 0, num_of_words - 1, buf_index,
1715                                 0, data_endian);
1716
1717                 /* use append instead of pack */
1718                 memcpy(usb_out_buffer + 4, word, num_of_words * 4);
1719
1720                 aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC + (num_of_words - 1) * 4);
1721
1722                 LOG_DEBUG("BATCH_BUFFER_WRITE, # of DATA %08" PRIx32, num_of_words);
1723
1724                 int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
1725                 if (AICE_FORMAT_DTHMB != result) {
1726                         LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1727                                         AICE_FORMAT_DTHMB, result);
1728                         return ERROR_FAIL;
1729                 }
1730
1731                 uint8_t cmd_ack_code;
1732                 uint8_t extra_length;
1733                 uint8_t res_target_id;
1734                 aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
1735
1736                 if (cmd_ack_code == AICE_CMD_BATCH_BUFFER_WRITE) {
1737                         break;
1738                 } else {
1739                         if (retry_times > aice_max_retry_times) {
1740                                 LOG_ERROR("aice command timeout (command=0x%" PRIx8 ", response=0x%" PRIx8 ")",
1741                                                 AICE_CMD_BATCH_BUFFER_WRITE, cmd_ack_code);
1742
1743                                 return ERROR_FAIL;
1744                         }
1745
1746                         /* clear timeout and retry */
1747                         if (aice_reset_box() != ERROR_OK)
1748                                 return ERROR_FAIL;
1749
1750                         retry_times++;
1751                 }
1752         } while (1);
1753
1754         return ERROR_OK;
1755 }
1756
1757 /***************************************************************************/
1758 /* End of AICE commands */
1759
1760 typedef int (*read_mem_func_t)(uint32_t coreid, uint32_t address, uint32_t *data);
1761 typedef int (*write_mem_func_t)(uint32_t coreid, uint32_t address, uint32_t data);
1762
1763 static struct aice_nds32_info core_info[AICE_MAX_NUM_CORE];
1764 static uint8_t total_num_of_core;
1765
1766 static char *custom_srst_script;
1767 static char *custom_trst_script;
1768 static char *custom_restart_script;
1769 static uint32_t aice_count_to_check_dbger = 30;
1770
1771 static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val);
1772 static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val);
1773
1774 static int check_suppressed_exception(uint32_t coreid, uint32_t dbger_value)
1775 {
1776         uint32_t ir4_value = 0;
1777         uint32_t ir6_value = 0;
1778         /* the default value of handling_suppressed_exception is false */
1779         static bool handling_suppressed_exception;
1780
1781         if (handling_suppressed_exception)
1782                 return ERROR_OK;
1783
1784         if ((dbger_value & NDS_DBGER_ALL_SUPRS_EX) == NDS_DBGER_ALL_SUPRS_EX) {
1785                 LOG_ERROR("<-- TARGET WARNING! Exception is detected and suppressed. -->");
1786                 handling_suppressed_exception = true;
1787
1788                 aice_read_reg(coreid, IR4, &ir4_value);
1789                 /* Clear IR6.SUPRS_EXC, IR6.IMP_EXC */
1790                 aice_read_reg(coreid, IR6, &ir6_value);
1791                 /*
1792                  * For MCU version(MSC_CFG.MCU == 1) like V3m
1793                  *  | SWID[30:16] | Reserved[15:10] | SUPRS_EXC[9]  | IMP_EXC[8]
1794                  *  |VECTOR[7:5] | INST[4] | Exc Type[3:0] |
1795                  *
1796                  * For non-MCU version(MSC_CFG.MCU == 0) like V3
1797                  *  | SWID[30:16] | Reserved[15:14] | SUPRS_EXC[13] | IMP_EXC[12]
1798                  *  | VECTOR[11:5] | INST[4] | Exc Type[3:0] |
1799                  */
1800                 LOG_INFO("EVA: 0x%08" PRIx32, ir4_value);
1801                 LOG_INFO("ITYPE: 0x%08" PRIx32, ir6_value);
1802
1803                 ir6_value = ir6_value & (~0x300); /* for MCU */
1804                 ir6_value = ir6_value & (~0x3000); /* for non-MCU */
1805                 aice_write_reg(coreid, IR6, ir6_value);
1806
1807                 handling_suppressed_exception = false;
1808         }
1809
1810         return ERROR_OK;
1811 }
1812
1813 static int check_privilege(uint32_t coreid, uint32_t dbger_value)
1814 {
1815         if ((dbger_value & NDS_DBGER_ILL_SEC_ACC) == NDS_DBGER_ILL_SEC_ACC) {
1816                 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege "
1817                                 "to execute the debug operations. -->");
1818
1819                 /* Clear DBGER.ILL_SEC_ACC */
1820                 if (aice_write_misc(coreid, NDS_EDM_MISC_DBGER,
1821                                         NDS_DBGER_ILL_SEC_ACC) != ERROR_OK)
1822                         return ERROR_FAIL;
1823         }
1824
1825         return ERROR_OK;
1826 }
1827
1828 static int aice_check_dbger(uint32_t coreid, uint32_t expect_status)
1829 {
1830         uint32_t i = 0;
1831         uint32_t value_dbger = 0;
1832
1833         while (1) {
1834                 aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &value_dbger);
1835
1836                 if ((value_dbger & expect_status) == expect_status) {
1837                         if (ERROR_OK != check_suppressed_exception(coreid, value_dbger))
1838                                 return ERROR_FAIL;
1839                         if (ERROR_OK != check_privilege(coreid, value_dbger))
1840                                 return ERROR_FAIL;
1841                         return ERROR_OK;
1842                 }
1843
1844                 if ((i % 30) == 0)
1845                         keep_alive();
1846
1847                 int64_t then = 0;
1848                 if (i == aice_count_to_check_dbger)
1849                         then = timeval_ms();
1850                 if (i >= aice_count_to_check_dbger) {
1851                         if ((timeval_ms() - then) > 1000) {
1852                                 LOG_ERROR("Timeout (1000ms) waiting for $DBGER status "
1853                                                 "being 0x%08" PRIx32, expect_status);
1854                                 return ERROR_FAIL;
1855                         }
1856                 }
1857                 i++;
1858         }
1859
1860         return ERROR_FAIL;
1861 }
1862
1863 static int aice_execute_dim(uint32_t coreid, uint32_t *insts, uint8_t n_inst)
1864 {
1865         /** fill DIM */
1866         if (aice_write_dim(coreid, insts, n_inst) != ERROR_OK)
1867                 return ERROR_FAIL;
1868
1869         /** clear DBGER.DPED */
1870         if (aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_DPED) != ERROR_OK)
1871                 return ERROR_FAIL;
1872
1873         /** execute DIM */
1874         if (aice_do_execute(coreid) != ERROR_OK)
1875                 return ERROR_FAIL;
1876
1877         /** read DBGER.DPED */
1878         if (aice_check_dbger(coreid, NDS_DBGER_DPED) != ERROR_OK) {
1879                 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly: "
1880                                 "0x%08" PRIx32 "0x%08" PRIx32 "0x%08" PRIx32 "0x%08" PRIx32 ". -->",
1881                                 insts[0],
1882                                 insts[1],
1883                                 insts[2],
1884                                 insts[3]);
1885                 return ERROR_FAIL;
1886         }
1887
1888         return ERROR_OK;
1889 }
1890
1891 static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val)
1892 {
1893         LOG_DEBUG("aice_read_reg, reg_no: 0x%08" PRIx32, num);
1894
1895         uint32_t instructions[4]; /** execute instructions in DIM */
1896
1897         if (NDS32_REG_TYPE_GPR == nds32_reg_type(num)) { /* general registers */
1898                 instructions[0] = MTSR_DTR(num);
1899                 instructions[1] = DSB;
1900                 instructions[2] = NOP;
1901                 instructions[3] = BEQ_MINUS_12;
1902         } else if (NDS32_REG_TYPE_SPR == nds32_reg_type(num)) { /* user special registers */
1903                 instructions[0] = MFUSR_G0(0, nds32_reg_sr_index(num));
1904                 instructions[1] = MTSR_DTR(0);
1905                 instructions[2] = DSB;
1906                 instructions[3] = BEQ_MINUS_12;
1907         } else if (NDS32_REG_TYPE_AUMR == nds32_reg_type(num)) { /* audio registers */
1908                 if ((CB_CTL <= num) && (num <= CBE3)) {
1909                         instructions[0] = AMFAR2(0, nds32_reg_sr_index(num));
1910                         instructions[1] = MTSR_DTR(0);
1911                         instructions[2] = DSB;
1912                         instructions[3] = BEQ_MINUS_12;
1913                 } else {
1914                         instructions[0] = AMFAR(0, nds32_reg_sr_index(num));
1915                         instructions[1] = MTSR_DTR(0);
1916                         instructions[2] = DSB;
1917                         instructions[3] = BEQ_MINUS_12;
1918                 }
1919         } else if (NDS32_REG_TYPE_FPU == nds32_reg_type(num)) { /* fpu registers */
1920                 if (FPCSR == num) {
1921                         instructions[0] = FMFCSR;
1922                         instructions[1] = MTSR_DTR(0);
1923                         instructions[2] = DSB;
1924                         instructions[3] = BEQ_MINUS_12;
1925                 } else if (FPCFG == num) {
1926                         instructions[0] = FMFCFG;
1927                         instructions[1] = MTSR_DTR(0);
1928                         instructions[2] = DSB;
1929                         instructions[3] = BEQ_MINUS_12;
1930                 } else {
1931                         if (FS0 <= num && num <= FS31) { /* single precision */
1932                                 instructions[0] = FMFSR(0, nds32_reg_sr_index(num));
1933                                 instructions[1] = MTSR_DTR(0);
1934                                 instructions[2] = DSB;
1935                                 instructions[3] = BEQ_MINUS_12;
1936                         } else if (FD0 <= num && num <= FD31) { /* double precision */
1937                                 instructions[0] = FMFDR(0, nds32_reg_sr_index(num));
1938                                 instructions[1] = MTSR_DTR(0);
1939                                 instructions[2] = DSB;
1940                                 instructions[3] = BEQ_MINUS_12;
1941                         }
1942                 }
1943         } else { /* system registers */
1944                 instructions[0] = MFSR(0, nds32_reg_sr_index(num));
1945                 instructions[1] = MTSR_DTR(0);
1946                 instructions[2] = DSB;
1947                 instructions[3] = BEQ_MINUS_12;
1948         }
1949
1950         aice_execute_dim(coreid, instructions, 4);
1951
1952         uint32_t value_edmsw = 0;
1953         aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw);
1954         if (value_edmsw & NDS_EDMSW_WDV)
1955                 aice_read_dtr(coreid, val);
1956         else {
1957                 LOG_ERROR("<-- TARGET ERROR! The debug target failed to update "
1958                                 "the DTR register. -->");
1959                 return ERROR_FAIL;
1960         }
1961
1962         return ERROR_OK;
1963 }
1964
1965 static int aice_usb_read_reg(uint32_t coreid, uint32_t num, uint32_t *val)
1966 {
1967         LOG_DEBUG("aice_usb_read_reg");
1968
1969         if (num == R0) {
1970                 *val = core_info[coreid].r0_backup;
1971         } else if (num == R1) {
1972                 *val = core_info[coreid].r1_backup;
1973         } else if (num == DR41) {
1974                 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
1975                  * As user wants to read these registers, OpenOCD should return
1976                  * the backup values, instead of reading the real values.
1977                  * As user wants to write these registers, OpenOCD should write
1978                  * to the backup values, instead of writing to real registers. */
1979                 *val = core_info[coreid].edmsw_backup;
1980         } else if (num == DR42) {
1981                 *val = core_info[coreid].edm_ctl_backup;
1982         } else if ((core_info[coreid].target_dtr_valid == true) && (num == DR43)) {
1983                 *val = core_info[coreid].target_dtr_backup;
1984         } else {
1985                 if (ERROR_OK != aice_read_reg(coreid, num, val))
1986                         *val = 0xBBADBEEF;
1987         }
1988
1989         return ERROR_OK;
1990 }
1991
1992 static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val)
1993 {
1994         LOG_DEBUG("aice_write_reg, reg_no: 0x%08" PRIx32 ", value: 0x%08" PRIx32, num, val);
1995
1996         uint32_t instructions[4]; /** execute instructions in DIM */
1997         uint32_t value_edmsw = 0;
1998
1999         aice_write_dtr(coreid, val);
2000         aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw);
2001         if (0 == (value_edmsw & NDS_EDMSW_RDV)) {
2002                 LOG_ERROR("<-- TARGET ERROR! AICE failed to write to the DTR register. -->");
2003                 return ERROR_FAIL;
2004         }
2005
2006         if (NDS32_REG_TYPE_GPR == nds32_reg_type(num)) { /* general registers */
2007                 instructions[0] = MFSR_DTR(num);
2008                 instructions[1] = DSB;
2009                 instructions[2] = NOP;
2010                 instructions[3] = BEQ_MINUS_12;
2011         } else if (NDS32_REG_TYPE_SPR == nds32_reg_type(num)) { /* user special registers */
2012                 instructions[0] = MFSR_DTR(0);
2013                 instructions[1] = MTUSR_G0(0, nds32_reg_sr_index(num));
2014                 instructions[2] = DSB;
2015                 instructions[3] = BEQ_MINUS_12;
2016         } else if (NDS32_REG_TYPE_AUMR == nds32_reg_type(num)) { /* audio registers */
2017                 if ((CB_CTL <= num) && (num <= CBE3)) {
2018                         instructions[0] = MFSR_DTR(0);
2019                         instructions[1] = AMTAR2(0, nds32_reg_sr_index(num));
2020                         instructions[2] = DSB;
2021                         instructions[3] = BEQ_MINUS_12;
2022                 } else {
2023                         instructions[0] = MFSR_DTR(0);
2024                         instructions[1] = AMTAR(0, nds32_reg_sr_index(num));
2025                         instructions[2] = DSB;
2026                         instructions[3] = BEQ_MINUS_12;
2027                 }
2028         } else if (NDS32_REG_TYPE_FPU == nds32_reg_type(num)) { /* fpu registers */
2029                 if (FPCSR == num) {
2030                         instructions[0] = MFSR_DTR(0);
2031                         instructions[1] = FMTCSR;
2032                         instructions[2] = DSB;
2033                         instructions[3] = BEQ_MINUS_12;
2034                 } else if (FPCFG == num) {
2035                         /* FPCFG is readonly */
2036                 } else {
2037                         if (FS0 <= num && num <= FS31) { /* single precision */
2038                                 instructions[0] = MFSR_DTR(0);
2039                                 instructions[1] = FMTSR(0, nds32_reg_sr_index(num));
2040                                 instructions[2] = DSB;
2041                                 instructions[3] = BEQ_MINUS_12;
2042                         } else if (FD0 <= num && num <= FD31) { /* double precision */
2043                                 instructions[0] = MFSR_DTR(0);
2044                                 instructions[1] = FMTDR(0, nds32_reg_sr_index(num));
2045                                 instructions[2] = DSB;
2046                                 instructions[3] = BEQ_MINUS_12;
2047                         }
2048                 }
2049         } else {
2050                 instructions[0] = MFSR_DTR(0);
2051                 instructions[1] = MTSR(0, nds32_reg_sr_index(num));
2052                 instructions[2] = DSB;
2053                 instructions[3] = BEQ_MINUS_12;
2054         }
2055
2056         return aice_execute_dim(coreid, instructions, 4);
2057 }
2058
2059 static int aice_usb_write_reg(uint32_t coreid, uint32_t num, uint32_t val)
2060 {
2061         LOG_DEBUG("aice_usb_write_reg");
2062
2063         if (num == R0)
2064                 core_info[coreid].r0_backup = val;
2065         else if (num == R1)
2066                 core_info[coreid].r1_backup = val;
2067         else if (num == DR42)
2068                 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
2069                  * As user wants to read these registers, OpenOCD should return
2070                  * the backup values, instead of reading the real values.
2071                  * As user wants to write these registers, OpenOCD should write
2072                  * to the backup values, instead of writing to real registers. */
2073                 core_info[coreid].edm_ctl_backup = val;
2074         else if ((core_info[coreid].target_dtr_valid == true) && (num == DR43))
2075                 core_info[coreid].target_dtr_backup = val;
2076         else
2077                 return aice_write_reg(coreid, num, val);
2078
2079         return ERROR_OK;
2080 }
2081
2082 static int aice_usb_open(struct aice_port_param_s *param)
2083 {
2084         const uint16_t vids[] = { param->vid, 0 };
2085         const uint16_t pids[] = { param->pid, 0 };
2086         struct libusb_device_handle *devh;
2087
2088         if (jtag_libusb_open(vids, pids, NULL, &devh, NULL) != ERROR_OK)
2089                 return ERROR_FAIL;
2090
2091         /* BE ***VERY CAREFUL*** ABOUT MAKING CHANGES IN THIS
2092          * AREA!!!!!!!!!!!  The behavior of libusb is not completely
2093          * consistent across Windows, Linux, and Mac OS X platforms.
2094          * The actions taken in the following compiler conditionals may
2095          * not agree with published documentation for libusb, but were
2096          * found to be necessary through trials and tribulations.  Even
2097          * little tweaks can break one or more platforms, so if you do
2098          * make changes test them carefully on all platforms before
2099          * committing them!
2100          */
2101
2102 #if IS_WIN32 == 0
2103
2104         libusb_reset_device(devh);
2105
2106 #if IS_DARWIN == 0
2107
2108         int timeout = 5;
2109         /* reopen jlink after usb_reset
2110          * on win32 this may take a second or two to re-enumerate */
2111         int retval;
2112         while ((retval = jtag_libusb_open(vids, pids, NULL, &devh, NULL)) != ERROR_OK) {
2113                 usleep(1000);
2114                 timeout--;
2115                 if (!timeout)
2116                         break;
2117         }
2118         if (ERROR_OK != retval)
2119                 return ERROR_FAIL;
2120 #endif
2121
2122 #endif
2123
2124         /* usb_set_configuration required under win32 */
2125         libusb_set_configuration(devh, 0);
2126         libusb_claim_interface(devh, 0);
2127
2128         unsigned int aice_read_ep;
2129         unsigned int aice_write_ep;
2130
2131         jtag_libusb_choose_interface(devh, &aice_read_ep, &aice_write_ep, -1, -1, -1, LIBUSB_TRANSFER_TYPE_BULK);
2132         LOG_DEBUG("aice_read_ep=0x%x, aice_write_ep=0x%x", aice_read_ep, aice_write_ep);
2133
2134         aice_handler.usb_read_ep = aice_read_ep;
2135         aice_handler.usb_write_ep = aice_write_ep;
2136         aice_handler.usb_handle = devh;
2137
2138         return ERROR_OK;
2139 }
2140
2141 static int aice_usb_read_reg_64(uint32_t coreid, uint32_t num, uint64_t *val)
2142 {
2143         LOG_DEBUG("aice_usb_read_reg_64, %s", nds32_reg_simple_name(num));
2144
2145         uint32_t value;
2146         uint32_t high_value;
2147
2148         if (ERROR_OK != aice_read_reg(coreid, num, &value))
2149                 value = 0xBBADBEEF;
2150
2151         aice_read_reg(coreid, R1, &high_value);
2152
2153         LOG_DEBUG("low: 0x%08" PRIx32 ", high: 0x%08" PRIx32 "\n", value, high_value);
2154
2155         if (data_endian == AICE_BIG_ENDIAN)
2156                 *val = (((uint64_t)high_value) << 32) | value;
2157         else
2158                 *val = (((uint64_t)value) << 32) | high_value;
2159
2160         return ERROR_OK;
2161 }
2162
2163 static int aice_usb_write_reg_64(uint32_t coreid, uint32_t num, uint64_t val)
2164 {
2165         uint32_t value;
2166         uint32_t high_value;
2167
2168         if (data_endian == AICE_BIG_ENDIAN) {
2169                 value = val & 0xFFFFFFFF;
2170                 high_value = (val >> 32) & 0xFFFFFFFF;
2171         } else {
2172                 high_value = val & 0xFFFFFFFF;
2173                 value = (val >> 32) & 0xFFFFFFFF;
2174         }
2175
2176         LOG_DEBUG("aice_usb_write_reg_64, %s, low: 0x%08" PRIx32 ", high: 0x%08" PRIx32 "\n",
2177                         nds32_reg_simple_name(num), value, high_value);
2178
2179         aice_write_reg(coreid, R1, high_value);
2180         return aice_write_reg(coreid, num, value);
2181 }
2182
2183 static int aice_get_version_info(void)
2184 {
2185         uint32_t hardware_version;
2186         uint32_t firmware_version;
2187         uint32_t fpga_version;
2188
2189         if (aice_read_ctrl(AICE_READ_CTRL_GET_HARDWARE_VERSION, &hardware_version) != ERROR_OK)
2190                 return ERROR_FAIL;
2191
2192         if (aice_read_ctrl(AICE_READ_CTRL_GET_FIRMWARE_VERSION, &firmware_version) != ERROR_OK)
2193                 return ERROR_FAIL;
2194
2195         if (aice_read_ctrl(AICE_READ_CTRL_GET_FPGA_VERSION, &fpga_version) != ERROR_OK)
2196                 return ERROR_FAIL;
2197
2198         LOG_INFO("AICE version: hw_ver = 0x%" PRIx32 ", fw_ver = 0x%" PRIx32 ", fpga_ver = 0x%" PRIx32,
2199                         hardware_version, firmware_version, fpga_version);
2200
2201         return ERROR_OK;
2202 }
2203
2204 #define LINE_BUFFER_SIZE 1024
2205
2206 static int aice_execute_custom_script(const char *script)
2207 {
2208         FILE *script_fd;
2209         char line_buffer[LINE_BUFFER_SIZE];
2210         char *op_str;
2211         char *reset_str;
2212         uint32_t delay;
2213         uint32_t write_ctrl_value;
2214         bool set_op;
2215
2216         script_fd = fopen(script, "r");
2217         if (script_fd == NULL) {
2218                 return ERROR_FAIL;
2219         } else {
2220                 while (fgets(line_buffer, LINE_BUFFER_SIZE, script_fd) != NULL) {
2221                         /* execute operations */
2222                         set_op = false;
2223                         op_str = strstr(line_buffer, "set");
2224                         if (op_str != NULL) {
2225                                 set_op = true;
2226                                 goto get_reset_type;
2227                         }
2228
2229                         op_str = strstr(line_buffer, "clear");
2230                         if (op_str == NULL)
2231                                 continue;
2232 get_reset_type:
2233                         reset_str = strstr(op_str, "srst");
2234                         if (reset_str != NULL) {
2235                                 if (set_op)
2236                                         write_ctrl_value = AICE_CUSTOM_DELAY_SET_SRST;
2237                                 else
2238                                         write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_SRST;
2239                                 goto get_delay;
2240                         }
2241                         reset_str = strstr(op_str, "dbgi");
2242                         if (reset_str != NULL) {
2243                                 if (set_op)
2244                                         write_ctrl_value = AICE_CUSTOM_DELAY_SET_DBGI;
2245                                 else
2246                                         write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_DBGI;
2247                                 goto get_delay;
2248                         }
2249                         reset_str = strstr(op_str, "trst");
2250                         if (reset_str != NULL) {
2251                                 if (set_op)
2252                                         write_ctrl_value = AICE_CUSTOM_DELAY_SET_TRST;
2253                                 else
2254                                         write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_TRST;
2255                                 goto get_delay;
2256                         }
2257                         continue;
2258 get_delay:
2259                         /* get delay */
2260                         delay = strtoul(reset_str + 4, NULL, 0);
2261                         write_ctrl_value |= (delay << 16);
2262
2263                         if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY,
2264                                                 write_ctrl_value) != ERROR_OK) {
2265                                 fclose(script_fd);
2266                                 return ERROR_FAIL;
2267                         }
2268                 }
2269                 fclose(script_fd);
2270         }
2271
2272         return ERROR_OK;
2273 }
2274
2275 static int aice_usb_set_clock(int set_clock)
2276 {
2277         if (set_clock & AICE_TCK_CONTROL_TCK_SCAN) {
2278                 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL,
2279                                         AICE_TCK_CONTROL_TCK_SCAN) != ERROR_OK)
2280                         return ERROR_FAIL;
2281
2282                 /* Read out TCK_SCAN clock value */
2283                 uint32_t scan_clock;
2284                 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE, &scan_clock) != ERROR_OK)
2285                         return ERROR_FAIL;
2286
2287                 scan_clock &= 0x0F;
2288
2289                 uint32_t scan_base_freq;
2290                 if (scan_clock & 0x8)
2291                         scan_base_freq = 48000; /* 48 MHz */
2292                 else
2293                         scan_base_freq = 30000; /* 30 MHz */
2294
2295                 uint32_t set_base_freq;
2296                 if (set_clock & 0x8)
2297                         set_base_freq = 48000;
2298                 else
2299                         set_base_freq = 30000;
2300
2301                 uint32_t set_freq;
2302                 uint32_t scan_freq;
2303                 set_freq = set_base_freq >> (set_clock & 0x7);
2304                 scan_freq = scan_base_freq >> (scan_clock & 0x7);
2305
2306                 if (scan_freq < set_freq) {
2307                         LOG_ERROR("User specifies higher jtag clock than TCK_SCAN clock");
2308                         return ERROR_FAIL;
2309                 }
2310         }
2311
2312         if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL, set_clock) != ERROR_OK)
2313                 return ERROR_FAIL;
2314
2315         uint32_t check_speed;
2316         if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE, &check_speed) != ERROR_OK)
2317                 return ERROR_FAIL;
2318
2319         if (((int)check_speed & 0x0F) != set_clock) {
2320                 LOG_ERROR("Set jtag clock failed");
2321                 return ERROR_FAIL;
2322         }
2323
2324         return ERROR_OK;
2325 }
2326
2327 static int aice_edm_init(uint32_t coreid)
2328 {
2329         aice_write_edmsr(coreid, NDS_EDM_SR_DIMBR, 0xFFFF0000);
2330         aice_write_misc(coreid, NDS_EDM_MISC_DIMIR, 0);
2331
2332         /* unconditionally try to turn on V3_EDM_MODE */
2333         uint32_t edm_ctl_value;
2334         aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL, &edm_ctl_value);
2335         aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value | 0x00000040);
2336
2337         /* clear DBGER */
2338         aice_write_misc(coreid, NDS_EDM_MISC_DBGER,
2339                         NDS_DBGER_DPED | NDS_DBGER_CRST | NDS_DBGER_AT_MAX);
2340
2341         /* get EDM version */
2342         uint32_t value_edmcfg;
2343         aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CFG, &value_edmcfg);
2344         core_info[coreid].edm_version = (value_edmcfg >> 16) & 0xFFFF;
2345
2346         return ERROR_OK;
2347 }
2348
2349 static bool is_v2_edm(uint32_t coreid)
2350 {
2351         if ((core_info[coreid].edm_version & 0x1000) == 0)
2352                 return true;
2353         else
2354                 return false;
2355 }
2356
2357 static int aice_init_edm_registers(uint32_t coreid, bool clear_dex_use_psw)
2358 {
2359         /* enable DEH_SEL & MAX_STOP & V3_EDM_MODE & DBGI_MASK */
2360         uint32_t host_edm_ctl = core_info[coreid].edm_ctl_backup | 0xA000004F;
2361         if (clear_dex_use_psw)
2362                 /* After entering debug mode, OpenOCD may set
2363                  * DEX_USE_PSW accidentally through backup value
2364                  * of target EDM_CTL.
2365                  * So, clear DEX_USE_PSW by force. */
2366                 host_edm_ctl &= ~(0x40000000);
2367
2368         LOG_DEBUG("aice_init_edm_registers - EDM_CTL: 0x%08" PRIx32, host_edm_ctl);
2369
2370         int result = aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, host_edm_ctl);
2371
2372         return result;
2373 }
2374
2375 /**
2376  * EDM_CTL will be modified by OpenOCD as debugging. OpenOCD has the
2377  * responsibility to keep EDM_CTL untouched after debugging.
2378  *
2379  * There are two scenarios to consider:
2380  * 1. single step/running as debugging (running under debug session)
2381  * 2. detached from gdb (exit debug session)
2382  *
2383  * So, we need to bakcup EDM_CTL before halted and restore it after
2384  * running. The difference of these two scenarios is EDM_CTL.DEH_SEL
2385  * is on for scenario 1, and off for scenario 2.
2386  */
2387 static int aice_backup_edm_registers(uint32_t coreid)
2388 {
2389         int result = aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL,
2390                         &core_info[coreid].edm_ctl_backup);
2391
2392         /* To call aice_backup_edm_registers() after DEX on, DEX_USE_PSW
2393          * may be not correct.  (For example, hit breakpoint, then backup
2394          * EDM_CTL. EDM_CTL.DEX_USE_PSW will be cleared.)  Because debug
2395          * interrupt will clear DEX_USE_PSW, DEX_USE_PSW is always off after
2396          * DEX is on.  It only backups correct value before OpenOCD issues DBGI.
2397          * (Backup EDM_CTL, then issue DBGI actively (refer aice_usb_halt())) */
2398         if (core_info[coreid].edm_ctl_backup & 0x40000000)
2399                 core_info[coreid].dex_use_psw_on = true;
2400         else
2401                 core_info[coreid].dex_use_psw_on = false;
2402
2403         LOG_DEBUG("aice_backup_edm_registers - EDM_CTL: 0x%08" PRIx32 ", DEX_USE_PSW: %s",
2404                         core_info[coreid].edm_ctl_backup,
2405                         core_info[coreid].dex_use_psw_on ? "on" : "off");
2406
2407         return result;
2408 }
2409
2410 static int aice_restore_edm_registers(uint32_t coreid)
2411 {
2412         LOG_DEBUG("aice_restore_edm_registers -");
2413
2414         /* set DEH_SEL, because target still under EDM control */
2415         int result = aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL,
2416                         core_info[coreid].edm_ctl_backup | 0x80000000);
2417
2418         return result;
2419 }
2420
2421 static int aice_backup_tmp_registers(uint32_t coreid)
2422 {
2423         LOG_DEBUG("backup_tmp_registers -");
2424
2425         /* backup target DTR first(if the target DTR is valid) */
2426         uint32_t value_edmsw = 0;
2427         aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw);
2428         core_info[coreid].edmsw_backup = value_edmsw;
2429         if (value_edmsw & 0x1) { /* EDMSW.WDV == 1 */
2430                 aice_read_dtr(coreid, &core_info[coreid].target_dtr_backup);
2431                 core_info[coreid].target_dtr_valid = true;
2432
2433                 LOG_DEBUG("Backup target DTR: 0x%08" PRIx32, core_info[coreid].target_dtr_backup);
2434         } else {
2435                 core_info[coreid].target_dtr_valid = false;
2436         }
2437
2438         /* Target DTR has been backup, then backup $R0 and $R1 */
2439         aice_read_reg(coreid, R0, &core_info[coreid].r0_backup);
2440         aice_read_reg(coreid, R1, &core_info[coreid].r1_backup);
2441
2442         /* backup host DTR(if the host DTR is valid) */
2443         if (value_edmsw & 0x2) { /* EDMSW.RDV == 1*/
2444                 /* read out host DTR and write into target DTR, then use aice_read_edmsr to
2445                  * read out */
2446                 uint32_t instructions[4] = {
2447                         MFSR_DTR(R0), /* R0 has already been backup */
2448                         DSB,
2449                         MTSR_DTR(R0),
2450                         BEQ_MINUS_12
2451                 };
2452                 aice_execute_dim(coreid, instructions, 4);
2453
2454                 aice_read_dtr(coreid, &core_info[coreid].host_dtr_backup);
2455                 core_info[coreid].host_dtr_valid = true;
2456
2457                 LOG_DEBUG("Backup host DTR: 0x%08" PRIx32, core_info[coreid].host_dtr_backup);
2458         } else {
2459                 core_info[coreid].host_dtr_valid = false;
2460         }
2461
2462         LOG_DEBUG("r0: 0x%08" PRIx32 ", r1: 0x%08" PRIx32,
2463                         core_info[coreid].r0_backup, core_info[coreid].r1_backup);
2464
2465         return ERROR_OK;
2466 }
2467
2468 static int aice_restore_tmp_registers(uint32_t coreid)
2469 {
2470         LOG_DEBUG("restore_tmp_registers - r0: 0x%08" PRIx32 ", r1: 0x%08" PRIx32,
2471                         core_info[coreid].r0_backup, core_info[coreid].r1_backup);
2472
2473         if (core_info[coreid].target_dtr_valid) {
2474                 uint32_t instructions[4] = {
2475                         SETHI(R0, core_info[coreid].target_dtr_backup >> 12),
2476                         ORI(R0, R0, core_info[coreid].target_dtr_backup & 0x00000FFF),
2477                         NOP,
2478                         BEQ_MINUS_12
2479                 };
2480                 aice_execute_dim(coreid, instructions, 4);
2481
2482                 instructions[0] = MTSR_DTR(R0);
2483                 instructions[1] = DSB;
2484                 instructions[2] = NOP;
2485                 instructions[3] = BEQ_MINUS_12;
2486                 aice_execute_dim(coreid, instructions, 4);
2487
2488                 LOG_DEBUG("Restore target DTR: 0x%08" PRIx32, core_info[coreid].target_dtr_backup);
2489         }
2490
2491         aice_write_reg(coreid, R0, core_info[coreid].r0_backup);
2492         aice_write_reg(coreid, R1, core_info[coreid].r1_backup);
2493
2494         if (core_info[coreid].host_dtr_valid) {
2495                 aice_write_dtr(coreid, core_info[coreid].host_dtr_backup);
2496
2497                 LOG_DEBUG("Restore host DTR: 0x%08" PRIx32, core_info[coreid].host_dtr_backup);
2498         }
2499
2500         return ERROR_OK;
2501 }
2502
2503 static int aice_open_device(struct aice_port_param_s *param)
2504 {
2505         if (ERROR_OK != aice_usb_open(param))
2506                 return ERROR_FAIL;
2507
2508         if (ERROR_FAIL == aice_get_version_info()) {
2509                 LOG_ERROR("Cannot get AICE version!");
2510                 return ERROR_FAIL;
2511         }
2512
2513         LOG_INFO("AICE initialization started");
2514
2515         /* attempt to reset Andes EDM */
2516         if (ERROR_FAIL == aice_reset_box()) {
2517                 LOG_ERROR("Cannot initial AICE box!");
2518                 return ERROR_FAIL;
2519         }
2520
2521         return ERROR_OK;
2522 }
2523
2524 static int aice_usb_set_jtag_clock(uint32_t a_clock)
2525 {
2526         jtag_clock = a_clock;
2527
2528         if (ERROR_OK != aice_usb_set_clock(a_clock)) {
2529                 LOG_ERROR("Cannot set AICE JTAG clock!");
2530                 return ERROR_FAIL;
2531         }
2532
2533         return ERROR_OK;
2534 }
2535
2536 static int aice_usb_close(void)
2537 {
2538         jtag_libusb_close(aice_handler.usb_handle);
2539
2540         free(custom_srst_script);
2541         free(custom_trst_script);
2542         free(custom_restart_script);
2543         return ERROR_OK;
2544 }
2545
2546 static int aice_core_init(uint32_t coreid)
2547 {
2548         core_info[coreid].access_channel = NDS_MEMORY_ACC_CPU;
2549         core_info[coreid].memory_select = NDS_MEMORY_SELECT_AUTO;
2550         core_info[coreid].core_state = AICE_TARGET_UNKNOWN;
2551
2552         return ERROR_OK;
2553 }
2554
2555 static int aice_usb_idcode(uint32_t *idcode, uint8_t *num_of_idcode)
2556 {
2557         int retval;
2558
2559         retval = aice_scan_chain(idcode, num_of_idcode);
2560         if (ERROR_OK == retval) {
2561                 for (int i = 0; i < *num_of_idcode; i++) {
2562                         aice_core_init(i);
2563                         aice_edm_init(i);
2564                 }
2565                 total_num_of_core = *num_of_idcode;
2566         }
2567
2568         return retval;
2569 }
2570
2571 static int aice_usb_halt(uint32_t coreid)
2572 {
2573         if (core_info[coreid].core_state == AICE_TARGET_HALTED) {
2574                 LOG_DEBUG("aice_usb_halt check halted");
2575                 return ERROR_OK;
2576         }
2577
2578         LOG_DEBUG("aice_usb_halt");
2579
2580         /** backup EDM registers */
2581         aice_backup_edm_registers(coreid);
2582         /** init EDM for host debugging */
2583         /** no need to clear dex_use_psw, because dbgi will clear it */
2584         aice_init_edm_registers(coreid, false);
2585
2586         /** Clear EDM_CTL.DBGIM & EDM_CTL.DBGACKM */
2587         uint32_t edm_ctl_value = 0;
2588         aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL, &edm_ctl_value);
2589         if (edm_ctl_value & 0x3)
2590                 aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value & ~(0x3));
2591
2592         uint32_t dbger = 0;
2593         uint32_t acc_ctl_value = 0;
2594
2595         core_info[coreid].debug_under_dex_on = false;
2596         aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &dbger);
2597
2598         if (dbger & NDS_DBGER_AT_MAX)
2599                 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level. -->");
2600
2601         if (dbger & NDS_DBGER_DEX) {
2602                 if (is_v2_edm(coreid) == false) {
2603                         /** debug 'debug mode'. use force_debug to issue dbgi */
2604                         aice_read_misc(coreid, NDS_EDM_MISC_ACC_CTL, &acc_ctl_value);
2605                         acc_ctl_value |= 0x8;
2606                         aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL, acc_ctl_value);
2607                         core_info[coreid].debug_under_dex_on = true;
2608
2609                         aice_write_misc(coreid, NDS_EDM_MISC_EDM_CMDR, 0);
2610                         /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2611                         if (dbger & NDS_DBGER_AT_MAX)
2612                                 aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_AT_MAX);
2613                 }
2614         } else {
2615                 /** Issue DBGI normally */
2616                 aice_write_misc(coreid, NDS_EDM_MISC_EDM_CMDR, 0);
2617                 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2618                 if (dbger & NDS_DBGER_AT_MAX)
2619                         aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_AT_MAX);
2620         }
2621
2622         if (aice_check_dbger(coreid, NDS_DBGER_DEX) != ERROR_OK) {
2623                 LOG_ERROR("<-- TARGET ERROR! Unable to stop the debug target through DBGI. -->");
2624                 return ERROR_FAIL;
2625         }
2626
2627         if (core_info[coreid].debug_under_dex_on) {
2628                 if (core_info[coreid].dex_use_psw_on == false) {
2629                         /* under debug 'debug mode', force $psw to 'debug mode' bahavior */
2630                         /* !!!NOTICE!!! this is workaround for debug 'debug mode'.
2631                          * it is only for debugging 'debug exception handler' purpose.
2632                          * after openocd detaches from target, target behavior is
2633                          * undefined. */
2634                         uint32_t ir0_value = 0;
2635                         uint32_t debug_mode_ir0_value;
2636                         aice_read_reg(coreid, IR0, &ir0_value);
2637                         debug_mode_ir0_value = ir0_value | 0x408; /* turn on DEX, set POM = 1 */
2638                         debug_mode_ir0_value &= ~(0x000000C1); /* turn off DT/IT/GIE */
2639                         aice_write_reg(coreid, IR0, debug_mode_ir0_value);
2640                 }
2641         }
2642
2643         /** set EDM_CTL.DBGIM & EDM_CTL.DBGACKM after halt */
2644         if (edm_ctl_value & 0x3)
2645                 aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value);
2646
2647         /* backup r0 & r1 */
2648         aice_backup_tmp_registers(coreid);
2649         core_info[coreid].core_state = AICE_TARGET_HALTED;
2650
2651         return ERROR_OK;
2652 }
2653
2654 static int aice_usb_state(uint32_t coreid, enum aice_target_state_s *state)
2655 {
2656         uint32_t dbger_value;
2657         uint32_t ice_state;
2658
2659         int result = aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &dbger_value);
2660
2661         if (ERROR_AICE_TIMEOUT == result) {
2662                 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE, &ice_state) != ERROR_OK) {
2663                         LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2664                         return ERROR_FAIL;
2665                 }
2666
2667                 if ((ice_state & 0x20) == 0) {
2668                         LOG_ERROR("<-- TARGET ERROR! Target is disconnected with AICE. -->");
2669                         return ERROR_FAIL;
2670                 } else {
2671                         return ERROR_FAIL;
2672                 }
2673         } else if (ERROR_AICE_DISCONNECT == result) {
2674                 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2675                 return ERROR_FAIL;
2676         }
2677
2678         if ((dbger_value & NDS_DBGER_ILL_SEC_ACC) == NDS_DBGER_ILL_SEC_ACC) {
2679                 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege. -->");
2680
2681                 /* Clear ILL_SEC_ACC */
2682                 aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_ILL_SEC_ACC);
2683
2684                 *state = AICE_TARGET_RUNNING;
2685                 core_info[coreid].core_state = AICE_TARGET_RUNNING;
2686         } else if ((dbger_value & NDS_DBGER_AT_MAX) == NDS_DBGER_AT_MAX) {
2687                 /* Issue DBGI to exit cpu stall */
2688                 aice_usb_halt(coreid);
2689
2690                 /* Read OIPC to find out the trigger point */
2691                 uint32_t ir11_value;
2692                 aice_read_reg(coreid, IR11, &ir11_value);
2693
2694                 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level; "
2695                                 "CPU is stalled at 0x%08" PRIx32 " for debugging. -->", ir11_value);
2696
2697                 *state = AICE_TARGET_HALTED;
2698         } else if ((dbger_value & NDS_DBGER_CRST) == NDS_DBGER_CRST) {
2699                 LOG_DEBUG("DBGER.CRST is on.");
2700
2701                 *state = AICE_TARGET_RESET;
2702                 core_info[coreid].core_state = AICE_TARGET_RUNNING;
2703
2704                 /* Clear CRST */
2705                 aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_CRST);
2706         } else if ((dbger_value & NDS_DBGER_DEX) == NDS_DBGER_DEX) {
2707                 if (AICE_TARGET_RUNNING == core_info[coreid].core_state) {
2708                         /* enter debug mode, init EDM registers */
2709                         /* backup EDM registers */
2710                         aice_backup_edm_registers(coreid);
2711                         /* init EDM for host debugging */
2712                         aice_init_edm_registers(coreid, true);
2713                         aice_backup_tmp_registers(coreid);
2714                         core_info[coreid].core_state = AICE_TARGET_HALTED;
2715                 } else if (AICE_TARGET_UNKNOWN == core_info[coreid].core_state) {
2716                         /* debug 'debug mode', use force debug to halt core */
2717                         aice_usb_halt(coreid);
2718                 }
2719                 *state = AICE_TARGET_HALTED;
2720         } else {
2721                 *state = AICE_TARGET_RUNNING;
2722                 core_info[coreid].core_state = AICE_TARGET_RUNNING;
2723         }
2724
2725         return ERROR_OK;
2726 }
2727
2728 static int aice_usb_reset(void)
2729 {
2730         if (aice_reset_box() != ERROR_OK)
2731                 return ERROR_FAIL;
2732
2733         /* issue TRST */
2734         if (custom_trst_script == NULL) {
2735                 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL,
2736                                         AICE_JTAG_PIN_CONTROL_TRST) != ERROR_OK)
2737                         return ERROR_FAIL;
2738         } else {
2739                 /* custom trst operations */
2740                 if (aice_execute_custom_script(custom_trst_script) != ERROR_OK)
2741                         return ERROR_FAIL;
2742         }
2743
2744         if (aice_usb_set_clock(jtag_clock) != ERROR_OK)
2745                 return ERROR_FAIL;
2746
2747         return ERROR_OK;
2748 }
2749
2750 static int aice_issue_srst(uint32_t coreid)
2751 {
2752         LOG_DEBUG("aice_issue_srst");
2753
2754         /* After issuing srst, target will be running. So we need to restore EDM_CTL. */
2755         aice_restore_edm_registers(coreid);
2756
2757         if (custom_srst_script == NULL) {
2758                 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL,
2759                                         AICE_JTAG_PIN_CONTROL_SRST) != ERROR_OK)
2760                         return ERROR_FAIL;
2761         } else {
2762                 /* custom srst operations */
2763                 if (aice_execute_custom_script(custom_srst_script) != ERROR_OK)
2764                         return ERROR_FAIL;
2765         }
2766
2767         /* wait CRST infinitely */
2768         uint32_t dbger_value;
2769         int i = 0;
2770         while (1) {
2771                 if (aice_read_misc(coreid,
2772                                         NDS_EDM_MISC_DBGER, &dbger_value) != ERROR_OK)
2773                         return ERROR_FAIL;
2774
2775                 if (dbger_value & NDS_DBGER_CRST)
2776                         break;
2777
2778                 if ((i % 30) == 0)
2779                         keep_alive();
2780                 i++;
2781         }
2782
2783         core_info[coreid].host_dtr_valid = false;
2784         core_info[coreid].target_dtr_valid = false;
2785
2786         core_info[coreid].core_state = AICE_TARGET_RUNNING;
2787         return ERROR_OK;
2788 }
2789
2790 static int aice_issue_reset_hold(uint32_t coreid)
2791 {
2792         LOG_DEBUG("aice_issue_reset_hold");
2793
2794         /* set no_dbgi_pin to 0 */
2795         uint32_t pin_status;
2796         aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS, &pin_status);
2797         if (pin_status & 0x4)
2798                 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS, pin_status & (~0x4));
2799
2800         /* issue restart */
2801         if (custom_restart_script == NULL) {
2802                 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL,
2803                                         AICE_JTAG_PIN_CONTROL_RESTART) != ERROR_OK)
2804                         return ERROR_FAIL;
2805         } else {
2806                 /* custom restart operations */
2807                 if (aice_execute_custom_script(custom_restart_script) != ERROR_OK)
2808                         return ERROR_FAIL;
2809         }
2810
2811         if (aice_check_dbger(coreid, NDS_DBGER_CRST | NDS_DBGER_DEX) == ERROR_OK) {
2812                 aice_backup_tmp_registers(coreid);
2813                 core_info[coreid].core_state = AICE_TARGET_HALTED;
2814
2815                 return ERROR_OK;
2816         } else {
2817                 /* set no_dbgi_pin to 1 */
2818                 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS, pin_status | 0x4);
2819
2820                 /* issue restart again */
2821                 if (custom_restart_script == NULL) {
2822                         if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL,
2823                                                 AICE_JTAG_PIN_CONTROL_RESTART) != ERROR_OK)
2824                                 return ERROR_FAIL;
2825                 } else {
2826                         /* custom restart operations */
2827                         if (aice_execute_custom_script(custom_restart_script) != ERROR_OK)
2828                                 return ERROR_FAIL;
2829                 }
2830
2831                 if (aice_check_dbger(coreid, NDS_DBGER_CRST | NDS_DBGER_DEX) == ERROR_OK) {
2832                         aice_backup_tmp_registers(coreid);
2833                         core_info[coreid].core_state = AICE_TARGET_HALTED;
2834
2835                         return ERROR_OK;
2836                 }
2837
2838                 /* do software reset-and-hold */
2839                 aice_issue_srst(coreid);
2840                 aice_usb_halt(coreid);
2841
2842                 uint32_t value_ir3;
2843                 aice_read_reg(coreid, IR3, &value_ir3);
2844                 aice_write_reg(coreid, PC, value_ir3 & 0xFFFF0000);
2845         }
2846
2847         return ERROR_FAIL;
2848 }
2849
2850 static int aice_issue_reset_hold_multi(void)
2851 {
2852         uint32_t write_ctrl_value = 0;
2853
2854         /* set SRST */
2855         write_ctrl_value = AICE_CUSTOM_DELAY_SET_SRST;
2856         write_ctrl_value |= (0x200 << 16);
2857         if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY,
2858                                 write_ctrl_value) != ERROR_OK)
2859                 return ERROR_FAIL;
2860
2861         for (uint8_t i = 0 ; i < total_num_of_core ; i++)
2862                 aice_write_misc(i, NDS_EDM_MISC_EDM_CMDR, 0);
2863
2864         /* clear SRST */
2865         write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_SRST;
2866         write_ctrl_value |= (0x200 << 16);
2867         if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY,
2868                                 write_ctrl_value) != ERROR_OK)
2869                 return ERROR_FAIL;
2870
2871         for (uint8_t i = 0; i < total_num_of_core; i++)
2872                 aice_edm_init(i);
2873
2874         return ERROR_FAIL;
2875 }
2876
2877 static int aice_usb_assert_srst(uint32_t coreid, enum aice_srst_type_s srst)
2878 {
2879         if ((AICE_SRST != srst) && (AICE_RESET_HOLD != srst))
2880                 return ERROR_FAIL;
2881
2882         /* clear DBGER */
2883         if (aice_write_misc(coreid, NDS_EDM_MISC_DBGER,
2884                                 NDS_DBGER_CLEAR_ALL) != ERROR_OK)
2885                 return ERROR_FAIL;
2886
2887         int result = ERROR_OK;
2888         if (AICE_SRST == srst)
2889                 result = aice_issue_srst(coreid);
2890         else {
2891                 if (1 == total_num_of_core)
2892                         result = aice_issue_reset_hold(coreid);
2893                 else
2894                         result = aice_issue_reset_hold_multi();
2895         }
2896
2897         /* Clear DBGER.CRST after reset to avoid 'core-reset checking' errors.
2898          * assert_srst is user-intentional reset behavior, so we could
2899          * clear DBGER.CRST safely.
2900          */
2901         if (aice_write_misc(coreid,
2902                                 NDS_EDM_MISC_DBGER, NDS_DBGER_CRST) != ERROR_OK)
2903                 return ERROR_FAIL;
2904
2905         return result;
2906 }
2907
2908 static int aice_usb_run(uint32_t coreid)
2909 {
2910         LOG_DEBUG("aice_usb_run");
2911
2912         uint32_t dbger_value;
2913         if (aice_read_misc(coreid,
2914                                 NDS_EDM_MISC_DBGER, &dbger_value) != ERROR_OK)
2915                 return ERROR_FAIL;
2916
2917         if ((dbger_value & NDS_DBGER_DEX) != NDS_DBGER_DEX) {
2918                 LOG_WARNING("<-- TARGET WARNING! The debug target exited "
2919                                 "the debug mode unexpectedly. -->");
2920                 return ERROR_FAIL;
2921         }
2922
2923         /* restore r0 & r1 before free run */
2924         aice_restore_tmp_registers(coreid);
2925         core_info[coreid].core_state = AICE_TARGET_RUNNING;
2926
2927         /* clear DBGER */
2928         aice_write_misc(coreid, NDS_EDM_MISC_DBGER,
2929                         NDS_DBGER_CLEAR_ALL);
2930
2931         /** restore EDM registers */
2932         /** OpenOCD should restore EDM_CTL **before** to exit debug state.
2933          *  Otherwise, following instruction will read wrong EDM_CTL value.
2934          *
2935          *  pc -> mfsr $p0, EDM_CTL (single step)
2936          *        slli $p0, $p0, 1
2937          *        slri $p0, $p0, 31
2938          */
2939         aice_restore_edm_registers(coreid);
2940
2941         /** execute instructions in DIM */
2942         uint32_t instructions[4] = {
2943                 NOP,
2944                 NOP,
2945                 NOP,
2946                 IRET
2947         };
2948         int result = aice_execute_dim(coreid, instructions, 4);
2949
2950         return result;
2951 }
2952
2953 static int aice_usb_step(uint32_t coreid)
2954 {
2955         LOG_DEBUG("aice_usb_step");
2956
2957         uint32_t ir0_value;
2958         uint32_t ir0_reg_num;
2959
2960         if (is_v2_edm(coreid) == true)
2961                 /* V2 EDM will push interrupt stack as debug exception */
2962                 ir0_reg_num = IR1;
2963         else
2964                 ir0_reg_num = IR0;
2965
2966         /** enable HSS */
2967         aice_read_reg(coreid, ir0_reg_num, &ir0_value);
2968         if ((ir0_value & 0x800) == 0) {
2969                 /** set PSW.HSS */
2970                 ir0_value |= (0x01 << 11);
2971                 aice_write_reg(coreid, ir0_reg_num, ir0_value);
2972         }
2973
2974         if (ERROR_FAIL == aice_usb_run(coreid))
2975                 return ERROR_FAIL;
2976
2977         int i = 0;
2978         enum aice_target_state_s state;
2979         while (1) {
2980                 /* read DBGER */
2981                 if (aice_usb_state(coreid, &state) != ERROR_OK)
2982                         return ERROR_FAIL;
2983
2984                 if (AICE_TARGET_HALTED == state)
2985                         break;
2986
2987                 int64_t then = 0;
2988                 if (i == 30)
2989                         then = timeval_ms();
2990
2991                 if (i >= 30) {
2992                         if ((timeval_ms() - then) > 1000)
2993                                 LOG_WARNING("Timeout (1000ms) waiting for halt to complete");
2994
2995                         return ERROR_FAIL;
2996                 }
2997                 i++;
2998         }
2999
3000         /** disable HSS */
3001         aice_read_reg(coreid, ir0_reg_num, &ir0_value);
3002         ir0_value &= ~(0x01 << 11);
3003         aice_write_reg(coreid, ir0_reg_num, ir0_value);
3004
3005         return ERROR_OK;
3006 }
3007
3008 static int aice_usb_read_mem_b_bus(uint32_t coreid, uint32_t address, uint32_t *data)
3009 {
3010         return aice_read_mem_b(coreid, address, data);
3011 }
3012
3013 static int aice_usb_read_mem_h_bus(uint32_t coreid, uint32_t address, uint32_t *data)
3014 {
3015         return aice_read_mem_h(coreid, address, data);
3016 }
3017
3018 static int aice_usb_read_mem_w_bus(uint32_t coreid, uint32_t address, uint32_t *data)
3019 {
3020         return aice_read_mem(coreid, address, data);
3021 }
3022
3023 static int aice_usb_read_mem_b_dim(uint32_t coreid, uint32_t address, uint32_t *data)
3024 {
3025         uint32_t value;
3026         uint32_t instructions[4] = {
3027                 LBI_BI(R1, R0),
3028                 MTSR_DTR(R1),
3029                 DSB,
3030                 BEQ_MINUS_12
3031         };
3032
3033         aice_execute_dim(coreid, instructions, 4);
3034
3035         aice_read_dtr(coreid, &value);
3036         *data = value & 0xFF;
3037
3038         return ERROR_OK;
3039 }
3040
3041 static int aice_usb_read_mem_h_dim(uint32_t coreid, uint32_t address, uint32_t *data)
3042 {
3043         uint32_t value;
3044         uint32_t instructions[4] = {
3045                 LHI_BI(R1, R0),
3046                 MTSR_DTR(R1),
3047                 DSB,
3048                 BEQ_MINUS_12
3049         };
3050
3051         aice_execute_dim(coreid, instructions, 4);
3052
3053         aice_read_dtr(coreid, &value);
3054         *data = value & 0xFFFF;
3055
3056         return ERROR_OK;
3057 }
3058
3059 static int aice_usb_read_mem_w_dim(uint32_t coreid, uint32_t address, uint32_t *data)
3060 {
3061         uint32_t instructions[4] = {
3062                 LWI_BI(R1, R0),
3063                 MTSR_DTR(R1),
3064                 DSB,
3065                 BEQ_MINUS_12
3066         };
3067
3068         aice_execute_dim(coreid, instructions, 4);
3069
3070         aice_read_dtr(coreid, data);
3071
3072         return ERROR_OK;
3073 }
3074
3075 static int aice_usb_set_address_dim(uint32_t coreid, uint32_t address)
3076 {
3077         uint32_t instructions[4] = {
3078                 SETHI(R0, address >> 12),
3079                 ORI(R0, R0, address & 0x00000FFF),
3080                 NOP,
3081                 BEQ_MINUS_12
3082         };
3083
3084         return aice_execute_dim(coreid, instructions, 4);
3085 }
3086
3087 static int aice_usb_read_memory_unit(uint32_t coreid, uint32_t addr, uint32_t size,
3088                 uint32_t count, uint8_t *buffer)
3089 {
3090         LOG_DEBUG("aice_usb_read_memory_unit, addr: 0x%08" PRIx32
3091                         ", size: %" PRIu32 ", count: %" PRIu32 "",
3092                         addr, size, count);
3093
3094         if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
3095                 aice_usb_set_address_dim(coreid, addr);
3096
3097         uint32_t value;
3098         size_t i;
3099         read_mem_func_t read_mem_func;
3100
3101         switch (size) {
3102                 case 1:
3103                         if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
3104                                 read_mem_func = aice_usb_read_mem_b_bus;
3105                         else
3106                                 read_mem_func = aice_usb_read_mem_b_dim;
3107
3108                         for (i = 0; i < count; i++) {
3109                                 read_mem_func(coreid, addr, &value);
3110                                 *buffer++ = (uint8_t)value;
3111                                 addr++;
3112                         }
3113                         break;
3114                 case 2:
3115                         if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
3116                                 read_mem_func = aice_usb_read_mem_h_bus;
3117                         else
3118                                 read_mem_func = aice_usb_read_mem_h_dim;
3119
3120                         for (i = 0; i < count; i++) {
3121                                 read_mem_func(coreid, addr, &value);
3122                                 uint16_t svalue = value;
3123                                 memcpy(buffer, &svalue, sizeof(uint16_t));
3124                                 buffer += 2;
3125                                 addr += 2;
3126                         }
3127                         break;
3128                 case 4:
3129                         if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
3130                                 read_mem_func = aice_usb_read_mem_w_bus;
3131                         else
3132                                 read_mem_func = aice_usb_read_mem_w_dim;
3133
3134                         for (i = 0; i < count; i++) {
3135                                 read_mem_func(coreid, addr, &value);
3136                                 memcpy(buffer, &value, sizeof(uint32_t));
3137                                 buffer += 4;
3138                                 addr += 4;
3139                         }
3140                         break;
3141         }
3142
3143         return ERROR_OK;
3144 }
3145
3146 static int aice_usb_write_mem_b_bus(uint32_t coreid, uint32_t address, uint32_t data)
3147 {
3148         return aice_write_mem_b(coreid, address, data);
3149 }
3150
3151 static int aice_usb_write_mem_h_bus(uint32_t coreid, uint32_t address, uint32_t data)
3152 {
3153         return aice_write_mem_h(coreid, address, data);
3154 }
3155
3156 static int aice_usb_write_mem_w_bus(uint32_t coreid, uint32_t address, uint32_t data)
3157 {
3158         return aice_write_mem(coreid, address, data);
3159 }
3160
3161 static int aice_usb_write_mem_b_dim(uint32_t coreid, uint32_t address, uint32_t data)
3162 {
3163         uint32_t instructions[4] = {
3164                 MFSR_DTR(R1),
3165                 SBI_BI(R1, R0),
3166                 DSB,
3167                 BEQ_MINUS_12
3168         };
3169
3170         aice_write_dtr(coreid, data & 0xFF);
3171         aice_execute_dim(coreid, instructions, 4);
3172
3173         return ERROR_OK;
3174 }
3175
3176 static int aice_usb_write_mem_h_dim(uint32_t coreid, uint32_t address, uint32_t data)
3177 {
3178         uint32_t instructions[4] = {
3179                 MFSR_DTR(R1),
3180                 SHI_BI(R1, R0),
3181                 DSB,
3182                 BEQ_MINUS_12
3183         };
3184
3185         aice_write_dtr(coreid, data & 0xFFFF);
3186         aice_execute_dim(coreid, instructions, 4);
3187
3188         return ERROR_OK;
3189 }
3190
3191 static int aice_usb_write_mem_w_dim(uint32_t coreid, uint32_t address, uint32_t data)
3192 {
3193         uint32_t instructions[4] = {
3194                 MFSR_DTR(R1),
3195                 SWI_BI(R1, R0),
3196                 DSB,
3197                 BEQ_MINUS_12
3198         };
3199
3200         aice_write_dtr(coreid, data);
3201         aice_execute_dim(coreid, instructions, 4);
3202
3203         return ERROR_OK;
3204 }
3205
3206 static int aice_usb_write_memory_unit(uint32_t coreid, uint32_t addr, uint32_t size,
3207                 uint32_t count, const uint8_t *buffer)
3208 {
3209         LOG_DEBUG("aice_usb_write_memory_unit, addr: 0x%08" PRIx32
3210                         ", size: %" PRIu32 ", count: %" PRIu32 "",
3211                         addr, size, count);
3212
3213         if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
3214                 aice_usb_set_address_dim(coreid, addr);
3215
3216         size_t i;
3217         write_mem_func_t write_mem_func;
3218
3219         switch (size) {
3220                 case 1:
3221                         if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
3222                                 write_mem_func = aice_usb_write_mem_b_bus;
3223                         else
3224                                 write_mem_func = aice_usb_write_mem_b_dim;
3225
3226                         for (i = 0; i < count; i++) {
3227                                 write_mem_func(coreid, addr, *buffer);
3228                                 buffer++;
3229                                 addr++;
3230                         }
3231                         break;
3232                 case 2:
3233                         if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
3234                                 write_mem_func = aice_usb_write_mem_h_bus;
3235                         else
3236                                 write_mem_func = aice_usb_write_mem_h_dim;
3237
3238                         for (i = 0; i < count; i++) {
3239                                 uint16_t value;
3240                                 memcpy(&value, buffer, sizeof(uint16_t));
3241
3242                                 write_mem_func(coreid, addr, value);
3243                                 buffer += 2;
3244                                 addr += 2;
3245                         }
3246                         break;
3247                 case 4:
3248                         if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
3249                                 write_mem_func = aice_usb_write_mem_w_bus;
3250                         else
3251                                 write_mem_func = aice_usb_write_mem_w_dim;
3252
3253                         for (i = 0; i < count; i++) {
3254                                 uint32_t value;
3255                                 memcpy(&value, buffer, sizeof(uint32_t));
3256
3257                                 write_mem_func(coreid, addr, value);
3258                                 buffer += 4;
3259                                 addr += 4;
3260                         }
3261                         break;
3262         }
3263
3264         return ERROR_OK;
3265 }
3266
3267 static int aice_bulk_read_mem(uint32_t coreid, uint32_t addr, uint32_t count,
3268                 uint8_t *buffer)
3269 {
3270         uint32_t packet_size;
3271
3272         while (count > 0) {
3273                 packet_size = (count >= 0x100) ? 0x100 : count;
3274
3275                 /** set address */
3276                 addr &= 0xFFFFFFFC;
3277                 if (aice_write_misc(coreid, NDS_EDM_MISC_SBAR, addr) != ERROR_OK)
3278                         return ERROR_FAIL;
3279
3280                 if (aice_fastread_mem(coreid, buffer,
3281                                         packet_size) != ERROR_OK)
3282                         return ERROR_FAIL;
3283
3284                 buffer += (packet_size * 4);
3285                 addr += (packet_size * 4);
3286                 count -= packet_size;
3287         }
3288
3289         return ERROR_OK;
3290 }
3291
3292 static int aice_bulk_write_mem(uint32_t coreid, uint32_t addr, uint32_t count,
3293                 const uint8_t *buffer)
3294 {
3295         uint32_t packet_size;
3296
3297         while (count > 0) {
3298                 packet_size = (count >= 0x100) ? 0x100 : count;
3299
3300                 /** set address */
3301                 addr &= 0xFFFFFFFC;
3302                 if (aice_write_misc(coreid, NDS_EDM_MISC_SBAR, addr | 1) != ERROR_OK)
3303                         return ERROR_FAIL;
3304
3305                 if (aice_fastwrite_mem(coreid, buffer,
3306                                         packet_size) != ERROR_OK)
3307                         return ERROR_FAIL;
3308
3309                 buffer += (packet_size * 4);
3310                 addr += (packet_size * 4);
3311                 count -= packet_size;
3312         }
3313
3314         return ERROR_OK;
3315 }
3316
3317 static int aice_usb_bulk_read_mem(uint32_t coreid, uint32_t addr,
3318                 uint32_t length, uint8_t *buffer)
3319 {
3320         LOG_DEBUG("aice_usb_bulk_read_mem, addr: 0x%08" PRIx32 ", length: 0x%08" PRIx32, addr, length);
3321
3322         int retval;
3323
3324         if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
3325                 aice_usb_set_address_dim(coreid, addr);
3326
3327         if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
3328                 retval = aice_usb_read_memory_unit(coreid, addr, 4, length / 4, buffer);
3329         else
3330                 retval = aice_bulk_read_mem(coreid, addr, length / 4, buffer);
3331
3332         return retval;
3333 }
3334
3335 static int aice_usb_bulk_write_mem(uint32_t coreid, uint32_t addr,
3336                 uint32_t length, const uint8_t *buffer)
3337 {
3338         LOG_DEBUG("aice_usb_bulk_write_mem, addr: 0x%08" PRIx32 ", length: 0x%08" PRIx32, addr, length);
3339
3340         int retval;
3341
3342         if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
3343                 aice_usb_set_address_dim(coreid, addr);
3344
3345         if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
3346                 retval = aice_usb_write_memory_unit(coreid, addr, 4, length / 4, buffer);
3347         else
3348                 retval = aice_bulk_write_mem(coreid, addr, length / 4, buffer);
3349
3350         return retval;
3351 }
3352
3353 static int aice_usb_read_debug_reg(uint32_t coreid, uint32_t addr, uint32_t *val)
3354 {
3355         if (AICE_TARGET_HALTED == core_info[coreid].core_state) {
3356                 if (NDS_EDM_SR_EDMSW == addr) {
3357                         *val = core_info[coreid].edmsw_backup;
3358                 } else if (NDS_EDM_SR_EDM_DTR == addr) {
3359                         if (core_info[coreid].target_dtr_valid) {
3360                                 /* if EDM_DTR has read out, clear it. */
3361                                 *val = core_info[coreid].target_dtr_backup;
3362                                 core_info[coreid].edmsw_backup &= (~0x1);
3363                                 core_info[coreid].target_dtr_valid = false;
3364                         } else {
3365                                 *val = 0;
3366                         }
3367                 }
3368         }
3369
3370         return aice_read_edmsr(coreid, addr, val);
3371 }
3372
3373 static int aice_usb_write_debug_reg(uint32_t coreid, uint32_t addr, const uint32_t val)
3374 {
3375         if (AICE_TARGET_HALTED == core_info[coreid].core_state) {
3376                 if (NDS_EDM_SR_EDM_DTR == addr) {
3377                         core_info[coreid].host_dtr_backup = val;
3378                         core_info[coreid].edmsw_backup |= 0x2;
3379                         core_info[coreid].host_dtr_valid = true;
3380                 }
3381         }
3382
3383         return aice_write_edmsr(coreid, addr, val);
3384 }
3385
3386 static int aice_usb_memory_access(uint32_t coreid, enum nds_memory_access channel)
3387 {
3388         LOG_DEBUG("aice_usb_memory_access, access channel: %u", channel);
3389
3390         core_info[coreid].access_channel = channel;
3391
3392         return ERROR_OK;
3393 }
3394
3395 static int aice_usb_memory_mode(uint32_t coreid, enum nds_memory_select mem_select)
3396 {
3397         if (core_info[coreid].memory_select == mem_select)
3398                 return ERROR_OK;
3399
3400         LOG_DEBUG("aice_usb_memory_mode, memory select: %u", mem_select);
3401
3402         core_info[coreid].memory_select = mem_select;
3403
3404         if (NDS_MEMORY_SELECT_AUTO != core_info[coreid].memory_select)
3405                 aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL,
3406                                 core_info[coreid].memory_select - 1);
3407         else
3408                 aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL,
3409                                 NDS_MEMORY_SELECT_MEM - 1);
3410
3411         return ERROR_OK;
3412 }
3413
3414 static int aice_usb_read_tlb(uint32_t coreid, target_addr_t virtual_address,
3415                 target_addr_t *physical_address)
3416 {
3417         LOG_DEBUG("aice_usb_read_tlb, virtual address: 0x%08" TARGET_PRIxADDR, virtual_address);
3418
3419         uint32_t instructions[4];
3420         uint32_t probe_result;
3421         uint32_t value_mr3;
3422         uint32_t value_mr4;
3423         uint32_t access_page_size;
3424         uint32_t virtual_offset;
3425         uint32_t physical_page_number;
3426
3427         aice_write_dtr(coreid, virtual_address);
3428
3429         /* probe TLB first */
3430         instructions[0] = MFSR_DTR(R0);
3431         instructions[1] = TLBOP_TARGET_PROBE(R1, R0);
3432         instructions[2] = DSB;
3433         instructions[3] = BEQ_MINUS_12;
3434         aice_execute_dim(coreid, instructions, 4);
3435
3436         aice_read_reg(coreid, R1, &probe_result);
3437
3438         if (probe_result & 0x80000000)
3439                 return ERROR_FAIL;
3440
3441         /* read TLB entry */
3442         aice_write_dtr(coreid, probe_result & 0x7FF);
3443
3444         /* probe TLB first */
3445         instructions[0] = MFSR_DTR(R0);
3446         instructions[1] = TLBOP_TARGET_READ(R0);
3447         instructions[2] = DSB;
3448         instructions[3] = BEQ_MINUS_12;
3449         aice_execute_dim(coreid, instructions, 4);
3450
3451         /* TODO: it should backup mr3, mr4 */
3452         aice_read_reg(coreid, MR3, &value_mr3);
3453         aice_read_reg(coreid, MR4, &value_mr4);
3454
3455         access_page_size = value_mr4 & 0xF;
3456         if (0 == access_page_size) { /* 4K page */
3457                 virtual_offset = virtual_address & 0x00000FFF;
3458                 physical_page_number = value_mr3 & 0xFFFFF000;
3459         } else if (1 == access_page_size) { /* 8K page */
3460                 virtual_offset = virtual_address & 0x00001FFF;
3461                 physical_page_number = value_mr3 & 0xFFFFE000;
3462         } else if (5 == access_page_size) { /* 1M page */
3463                 virtual_offset = virtual_address & 0x000FFFFF;
3464                 physical_page_number = value_mr3 & 0xFFF00000;
3465         } else {
3466                 return ERROR_FAIL;
3467         }
3468
3469         *physical_address = physical_page_number | virtual_offset;
3470
3471         return ERROR_OK;
3472 }
3473
3474 static int aice_usb_init_cache(uint32_t coreid)
3475 {
3476         LOG_DEBUG("aice_usb_init_cache");
3477
3478         uint32_t value_cr1;
3479         uint32_t value_cr2;
3480
3481         aice_read_reg(coreid, CR1, &value_cr1);
3482         aice_read_reg(coreid, CR2, &value_cr2);
3483
3484         struct cache_info *icache = &core_info[coreid].icache;
3485
3486         icache->set = value_cr1 & 0x7;
3487         icache->log2_set = icache->set + 6;
3488         icache->set = 64 << icache->set;
3489         icache->way = ((value_cr1 >> 3) & 0x7) + 1;
3490         icache->line_size = (value_cr1 >> 6) & 0x7;
3491         if (icache->line_size != 0) {
3492                 icache->log2_line_size = icache->line_size + 2;
3493                 icache->line_size = 8 << (icache->line_size - 1);
3494         } else {
3495                 icache->log2_line_size = 0;
3496         }
3497
3498         LOG_DEBUG("\ticache set: %" PRIu32 ", way: %" PRIu32 ", line size: %" PRIu32 ", "
3499                         "log2(set): %" PRIu32 ", log2(line_size): %" PRIu32 "",
3500                         icache->set, icache->way, icache->line_size,
3501                         icache->log2_set, icache->log2_line_size);
3502
3503         struct cache_info *dcache = &core_info[coreid].dcache;
3504
3505         dcache->set = value_cr2 & 0x7;
3506         dcache->log2_set = dcache->set + 6;
3507         dcache->set = 64 << dcache->set;
3508         dcache->way = ((value_cr2 >> 3) & 0x7) + 1;
3509         dcache->line_size = (value_cr2 >> 6) & 0x7;
3510         if (dcache->line_size != 0) {
3511                 dcache->log2_line_size = dcache->line_size + 2;
3512                 dcache->line_size = 8 << (dcache->line_size - 1);
3513         } else {
3514                 dcache->log2_line_size = 0;
3515         }
3516
3517         LOG_DEBUG("\tdcache set: %" PRIu32 ", way: %" PRIu32 ", line size: %" PRIu32 ", "
3518                         "log2(set): %" PRIu32 ", log2(line_size): %" PRIu32 "",
3519                         dcache->set, dcache->way, dcache->line_size,
3520                         dcache->log2_set, dcache->log2_line_size);
3521
3522         core_info[coreid].cache_init = true;
3523
3524         return ERROR_OK;
3525 }
3526
3527 static int aice_usb_dcache_inval_all(uint32_t coreid)
3528 {
3529         LOG_DEBUG("aice_usb_dcache_inval_all");
3530
3531         uint32_t set_index;
3532         uint32_t way_index;
3533         uint32_t cache_index;
3534         uint32_t instructions[4];
3535
3536         instructions[0] = MFSR_DTR(R0);
3537         instructions[1] = L1D_IX_INVAL(R0);
3538         instructions[2] = DSB;
3539         instructions[3] = BEQ_MINUS_12;
3540
3541         struct cache_info *dcache = &core_info[coreid].dcache;
3542
3543         for (set_index = 0; set_index < dcache->set; set_index++) {
3544                 for (way_index = 0; way_index < dcache->way; way_index++) {
3545                         cache_index = (way_index << (dcache->log2_set + dcache->log2_line_size)) |
3546                                 (set_index << dcache->log2_line_size);
3547
3548                         if (ERROR_OK != aice_write_dtr(coreid, cache_index))
3549                                 return ERROR_FAIL;
3550
3551                         if (ERROR_OK != aice_execute_dim(coreid, instructions, 4))
3552                                 return ERROR_FAIL;
3553                 }
3554         }
3555
3556         return ERROR_OK;
3557 }
3558
3559 static int aice_usb_dcache_va_inval(uint32_t coreid, uint32_t address)
3560 {
3561         LOG_DEBUG("aice_usb_dcache_va_inval");
3562
3563         uint32_t instructions[4];
3564
3565         aice_write_dtr(coreid, address);
3566
3567         instructions[0] = MFSR_DTR(R0);
3568         instructions[1] = L1D_VA_INVAL(R0);
3569         instructions[2] = DSB;
3570         instructions[3] = BEQ_MINUS_12;
3571
3572         return aice_execute_dim(coreid, instructions, 4);
3573 }
3574
3575 static int aice_usb_dcache_wb_all(uint32_t coreid)
3576 {
3577         LOG_DEBUG("aice_usb_dcache_wb_all");
3578
3579         uint32_t set_index;
3580         uint32_t way_index;
3581         uint32_t cache_index;
3582         uint32_t instructions[4];
3583
3584         instructions[0] = MFSR_DTR(R0);
3585         instructions[1] = L1D_IX_WB(R0);
3586         instructions[2] = DSB;
3587         instructions[3] = BEQ_MINUS_12;
3588
3589         struct cache_info *dcache = &core_info[coreid].dcache;
3590
3591         for (set_index = 0; set_index < dcache->set; set_index++) {
3592                 for (way_index = 0; way_index < dcache->way; way_index++) {
3593                         cache_index = (way_index << (dcache->log2_set + dcache->log2_line_size)) |
3594                                 (set_index << dcache->log2_line_size);
3595
3596                         if (ERROR_OK != aice_write_dtr(coreid, cache_index))
3597                                 return ERROR_FAIL;
3598
3599                         if (ERROR_OK != aice_execute_dim(coreid, instructions, 4))
3600                                 return ERROR_FAIL;
3601                 }
3602         }
3603
3604         return ERROR_OK;
3605 }
3606
3607 static int aice_usb_dcache_va_wb(uint32_t coreid, uint32_t address)
3608 {
3609         LOG_DEBUG("aice_usb_dcache_va_wb");
3610
3611         uint32_t instructions[4];
3612
3613         aice_write_dtr(coreid, address);
3614
3615         instructions[0] = MFSR_DTR(R0);
3616         instructions[1] = L1D_VA_WB(R0);
3617         instructions[2] = DSB;
3618         instructions[3] = BEQ_MINUS_12;
3619
3620         return aice_execute_dim(coreid, instructions, 4);
3621 }
3622
3623 static int aice_usb_icache_inval_all(uint32_t coreid)
3624 {
3625         LOG_DEBUG("aice_usb_icache_inval_all");
3626
3627         uint32_t set_index;
3628         uint32_t way_index;
3629         uint32_t cache_index;
3630         uint32_t instructions[4];
3631
3632         instructions[0] = MFSR_DTR(R0);
3633         instructions[1] = L1I_IX_INVAL(R0);
3634         instructions[2] = ISB;
3635         instructions[3] = BEQ_MINUS_12;
3636
3637         struct cache_info *icache = &core_info[coreid].icache;
3638
3639         for (set_index = 0; set_index < icache->set; set_index++) {
3640                 for (way_index = 0; way_index < icache->way; way_index++) {
3641                         cache_index = (way_index << (icache->log2_set + icache->log2_line_size)) |
3642                                 (set_index << icache->log2_line_size);
3643
3644                         if (ERROR_OK != aice_write_dtr(coreid, cache_index))
3645                                 return ERROR_FAIL;
3646
3647                         if (ERROR_OK != aice_execute_dim(coreid, instructions, 4))
3648                                 return ERROR_FAIL;
3649                 }
3650         }
3651
3652         return ERROR_OK;
3653 }
3654
3655 static int aice_usb_icache_va_inval(uint32_t coreid, uint32_t address)
3656 {
3657         LOG_DEBUG("aice_usb_icache_va_inval");
3658
3659         uint32_t instructions[4];
3660
3661         aice_write_dtr(coreid, address);
3662
3663         instructions[0] = MFSR_DTR(R0);
3664         instructions[1] = L1I_VA_INVAL(R0);
3665         instructions[2] = ISB;
3666         instructions[3] = BEQ_MINUS_12;
3667
3668         return aice_execute_dim(coreid, instructions, 4);
3669 }
3670
3671 static int aice_usb_cache_ctl(uint32_t coreid, uint32_t subtype, uint32_t address)
3672 {
3673         LOG_DEBUG("aice_usb_cache_ctl");
3674
3675         int result;
3676
3677         if (core_info[coreid].cache_init == false)
3678                 aice_usb_init_cache(coreid);
3679
3680         switch (subtype) {
3681                 case AICE_CACHE_CTL_L1D_INVALALL:
3682                         result = aice_usb_dcache_inval_all(coreid);
3683                         break;
3684                 case AICE_CACHE_CTL_L1D_VA_INVAL:
3685                         result = aice_usb_dcache_va_inval(coreid, address);
3686                         break;
3687                 case AICE_CACHE_CTL_L1D_WBALL:
3688                         result = aice_usb_dcache_wb_all(coreid);
3689                         break;
3690                 case AICE_CACHE_CTL_L1D_VA_WB:
3691                         result = aice_usb_dcache_va_wb(coreid, address);
3692                         break;
3693                 case AICE_CACHE_CTL_L1I_INVALALL:
3694                         result = aice_usb_icache_inval_all(coreid);
3695                         break;
3696                 case AICE_CACHE_CTL_L1I_VA_INVAL:
3697                         result = aice_usb_icache_va_inval(coreid, address);
3698                         break;
3699                 default:
3700                         result = ERROR_FAIL;
3701                         break;
3702         }
3703
3704         return result;
3705 }
3706
3707 static int aice_usb_set_retry_times(uint32_t a_retry_times)
3708 {
3709         aice_max_retry_times = a_retry_times;
3710         return ERROR_OK;
3711 }
3712
3713 static int aice_usb_program_edm(uint32_t coreid, char *command_sequence)
3714 {
3715         char *command_str;
3716         char *reg_name_0;
3717         char *reg_name_1;
3718         uint32_t data_value;
3719         int i;
3720
3721         /* init strtok() */
3722         command_str = strtok(command_sequence, ";");
3723         if (command_str == NULL)
3724                 return ERROR_OK;
3725
3726         do {
3727                 i = 0;
3728                 /* process one command */
3729                 while (command_str[i] == ' ' ||
3730                                 command_str[i] == '\n' ||
3731                                 command_str[i] == '\r' ||
3732                                 command_str[i] == '\t')
3733                         i++;
3734
3735                 /* skip ' ', '\r', '\n', '\t' */
3736                 command_str = command_str + i;
3737
3738                 if (strncmp(command_str, "write_misc", 10) == 0) {
3739                         reg_name_0 = strstr(command_str, "gen_port0");
3740                         reg_name_1 = strstr(command_str, "gen_port1");
3741
3742                         if (reg_name_0 != NULL) {
3743                                 data_value = strtoul(reg_name_0 + 9, NULL, 0);
3744
3745                                 if (aice_write_misc(coreid,
3746                                                         NDS_EDM_MISC_GEN_PORT0, data_value) != ERROR_OK)
3747                                         return ERROR_FAIL;
3748
3749                         } else if (reg_name_1 != NULL) {
3750                                 data_value = strtoul(reg_name_1 + 9, NULL, 0);
3751
3752                                 if (aice_write_misc(coreid,
3753                                                         NDS_EDM_MISC_GEN_PORT1, data_value) != ERROR_OK)
3754                                         return ERROR_FAIL;
3755                         } else {
3756                                 LOG_ERROR("program EDM, unsupported misc register: %s", command_str);
3757                         }
3758                 } else {
3759                         LOG_ERROR("program EDM, unsupported command: %s", command_str);
3760                 }
3761
3762                 /* update command_str */
3763                 command_str = strtok(NULL, ";");
3764
3765         } while (command_str != NULL);
3766
3767         return ERROR_OK;
3768 }
3769
3770 static int aice_usb_set_command_mode(enum aice_command_mode command_mode)
3771 {
3772         int retval = ERROR_OK;
3773
3774         /* flush usb_packets_buffer as users change mode */
3775         retval = aice_usb_packet_flush();
3776
3777         if (AICE_COMMAND_MODE_BATCH == command_mode) {
3778                 /* reset batch buffer */
3779                 aice_command_mode = AICE_COMMAND_MODE_NORMAL;
3780                 retval = aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL, 0x40000);
3781         }
3782
3783         aice_command_mode = command_mode;
3784
3785         return retval;
3786 }
3787
3788 static int aice_usb_execute(uint32_t coreid, uint32_t *instructions,
3789                 uint32_t instruction_num)
3790 {
3791         uint32_t i, j;
3792         uint8_t current_instruction_num;
3793         uint32_t dim_instructions[4] = {NOP, NOP, NOP, BEQ_MINUS_12};
3794
3795         /* To execute 4 instructions as a special case */
3796         if (instruction_num == 4)
3797                 return aice_execute_dim(coreid, instructions, 4);
3798
3799         for (i = 0 ; i < instruction_num ; i += 3) {
3800                 if (instruction_num - i < 3) {
3801                         current_instruction_num = instruction_num - i;
3802                         for (j = current_instruction_num ; j < 3 ; j++)
3803                                 dim_instructions[j] = NOP;
3804                 } else {
3805                         current_instruction_num = 3;
3806                 }
3807
3808                 memcpy(dim_instructions, instructions + i,
3809                                 current_instruction_num * sizeof(uint32_t));
3810
3811                 /** fill DIM */
3812                 if (aice_write_dim(coreid,
3813                                         dim_instructions,
3814                                         4) != ERROR_OK)
3815                         return ERROR_FAIL;
3816
3817                 /** clear DBGER.DPED */
3818                 if (aice_write_misc(coreid,
3819                                         NDS_EDM_MISC_DBGER, NDS_DBGER_DPED) != ERROR_OK)
3820                         return ERROR_FAIL;
3821
3822                 /** execute DIM */
3823                 if (aice_do_execute(coreid) != ERROR_OK)
3824                         return ERROR_FAIL;
3825
3826                 /** check DBGER.DPED */
3827                 if (aice_check_dbger(coreid, NDS_DBGER_DPED) != ERROR_OK) {
3828
3829                         LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly:"
3830                                         "0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 ". -->",
3831                                         dim_instructions[0],
3832                                         dim_instructions[1],
3833                                         dim_instructions[2],
3834                                         dim_instructions[3]);
3835                         return ERROR_FAIL;
3836                 }
3837         }
3838
3839         return ERROR_OK;
3840 }
3841
3842 static int aice_usb_set_custom_srst_script(const char *script)
3843 {
3844         custom_srst_script = strdup(script);
3845
3846         return ERROR_OK;
3847 }
3848
3849 static int aice_usb_set_custom_trst_script(const char *script)
3850 {
3851         custom_trst_script = strdup(script);
3852
3853         return ERROR_OK;
3854 }
3855
3856 static int aice_usb_set_custom_restart_script(const char *script)
3857 {
3858         custom_restart_script = strdup(script);
3859
3860         return ERROR_OK;
3861 }
3862
3863 static int aice_usb_set_count_to_check_dbger(uint32_t count_to_check)
3864 {
3865         aice_count_to_check_dbger = count_to_check;
3866
3867         return ERROR_OK;
3868 }
3869
3870 static int aice_usb_set_data_endian(uint32_t coreid,
3871                 enum aice_target_endian target_data_endian)
3872 {
3873         data_endian = target_data_endian;
3874
3875         return ERROR_OK;
3876 }
3877
3878 static int fill_profiling_batch_commands(uint32_t coreid, uint32_t reg_no)
3879 {
3880         uint32_t dim_instructions[4];
3881
3882         aice_usb_set_command_mode(AICE_COMMAND_MODE_BATCH);
3883
3884         /* halt */
3885         if (aice_write_misc(coreid, NDS_EDM_MISC_EDM_CMDR, 0) != ERROR_OK)
3886                 return ERROR_FAIL;
3887
3888         /* backup $r0 */
3889         dim_instructions[0] = MTSR_DTR(0);
3890         dim_instructions[1] = DSB;
3891         dim_instructions[2] = NOP;
3892         dim_instructions[3] = BEQ_MINUS_12;
3893         if (aice_write_dim(coreid, dim_instructions, 4) != ERROR_OK)
3894                 return ERROR_FAIL;
3895         aice_read_dtr_to_buffer(coreid, AICE_BATCH_DATA_BUFFER_0);
3896
3897         /* get samples */
3898         if (NDS32_REG_TYPE_GPR == nds32_reg_type(reg_no)) {
3899                 /* general registers */
3900                 dim_instructions[0] = MTSR_DTR(reg_no);
3901                 dim_instructions[1] = DSB;
3902                 dim_instructions[2] = NOP;
3903                 dim_instructions[3] = BEQ_MINUS_12;
3904         } else if (NDS32_REG_TYPE_SPR == nds32_reg_type(reg_no)) {
3905                 /* user special registers */
3906                 dim_instructions[0] = MFUSR_G0(0, nds32_reg_sr_index(reg_no));
3907                 dim_instructions[1] = MTSR_DTR(0);
3908                 dim_instructions[2] = DSB;
3909                 dim_instructions[3] = BEQ_MINUS_12;
3910         } else { /* system registers */
3911                 dim_instructions[0] = MFSR(0, nds32_reg_sr_index(reg_no));
3912                 dim_instructions[1] = MTSR_DTR(0);
3913                 dim_instructions[2] = DSB;
3914                 dim_instructions[3] = BEQ_MINUS_12;
3915         }
3916         if (aice_write_dim(coreid, dim_instructions, 4) != ERROR_OK)
3917                 return ERROR_FAIL;
3918         aice_read_dtr_to_buffer(coreid, AICE_BATCH_DATA_BUFFER_1);
3919
3920         /* restore $r0 */
3921         aice_write_dtr_from_buffer(coreid, AICE_BATCH_DATA_BUFFER_0);
3922         dim_instructions[0] = MFSR_DTR(0);
3923         dim_instructions[1] = DSB;
3924         dim_instructions[2] = NOP;
3925         dim_instructions[3] = IRET;  /* free run */
3926         if (aice_write_dim(coreid, dim_instructions, 4) != ERROR_OK)
3927                 return ERROR_FAIL;
3928
3929         aice_command_mode = AICE_COMMAND_MODE_NORMAL;
3930
3931         /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */
3932         if (aice_batch_buffer_write(AICE_BATCH_COMMAND_BUFFER_0,
3933                                 usb_out_packets_buffer,
3934                                 (usb_out_packets_buffer_length + 3) / 4) != ERROR_OK)
3935                 return ERROR_FAIL;
3936
3937         usb_out_packets_buffer_length = 0;
3938         usb_in_packets_buffer_length = 0;
3939
3940         return ERROR_OK;
3941 }
3942
3943 static int aice_usb_profiling(uint32_t coreid, uint32_t interval, uint32_t iteration,
3944                 uint32_t reg_no, uint32_t *samples, uint32_t *num_samples)
3945 {
3946         uint32_t iteration_count;
3947         uint32_t this_iteration;
3948         int retval = ERROR_OK;
3949         const uint32_t MAX_ITERATION = 250;
3950
3951         *num_samples = 0;
3952
3953         /* init DIM size */
3954         if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DIM_SIZE, 4) != ERROR_OK)
3955                 return ERROR_FAIL;
3956
3957         /* Use AICE_BATCH_DATA_BUFFER_0 to read/write $DTR.
3958          * Set it to circular buffer */
3959         if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF0_CTRL, 0xC0000) != ERROR_OK)
3960                 return ERROR_FAIL;
3961
3962         fill_profiling_batch_commands(coreid, reg_no);
3963
3964         iteration_count = 0;
3965         while (iteration_count < iteration) {
3966                 if (iteration - iteration_count < MAX_ITERATION)
3967                         this_iteration = iteration - iteration_count;
3968                 else
3969                         this_iteration = MAX_ITERATION;
3970
3971                 /* set number of iterations */
3972                 uint32_t val_iteration;
3973                 val_iteration = interval << 16 | this_iteration;
3974                 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_ITERATION,
3975                                         val_iteration) != ERROR_OK) {
3976                         retval = ERROR_FAIL;
3977                         goto end_profiling;
3978                 }
3979
3980                 /* init AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL to store $PC */
3981                 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL,
3982                                         0x40000) != ERROR_OK) {
3983                         retval = ERROR_FAIL;
3984                         goto end_profiling;
3985                 }
3986
3987                 aice_usb_run(coreid);
3988
3989                 /* enable BATCH command */
3990                 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL,
3991                                         0x80000000) != ERROR_OK) {
3992                         aice_usb_halt(coreid);
3993                         retval = ERROR_FAIL;
3994                         goto end_profiling;
3995                 }
3996
3997                 /* wait a while (AICE bug, workaround) */
3998                 alive_sleep(this_iteration);
3999
4000                 /* check status */
4001                 uint32_t i;
4002                 uint32_t batch_status = 0;
4003
4004                 i = 0;
4005                 while (1) {
4006                         aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS, &batch_status);
4007
4008                         if (batch_status & 0x1) {
4009                                 break;
4010                         } else if (batch_status & 0xE) {
4011                                 aice_usb_halt(coreid);
4012                                 retval = ERROR_FAIL;
4013                                 goto end_profiling;
4014                         }
4015
4016                         if ((i % 30) == 0)
4017                                 keep_alive();
4018
4019                         i++;
4020                 }
4021
4022                 aice_usb_halt(coreid);
4023
4024                 /* get samples from batch data buffer */
4025                 if (aice_batch_buffer_read(AICE_BATCH_DATA_BUFFER_1,
4026                                         samples + iteration_count, this_iteration) != ERROR_OK) {
4027                         retval = ERROR_FAIL;
4028                         goto end_profiling;
4029                 }
4030
4031                 iteration_count += this_iteration;
4032         }
4033
4034 end_profiling:
4035         *num_samples = iteration_count;
4036
4037         return retval;
4038 }
4039
4040 /** */
4041 struct aice_port_api_s aice_usb_api = {
4042         /** */
4043         .open = aice_open_device,
4044         /** */
4045         .close = aice_usb_close,
4046         /** */
4047         .idcode = aice_usb_idcode,
4048         /** */
4049         .state = aice_usb_state,
4050         /** */
4051         .reset = aice_usb_reset,
4052         /** */
4053         .assert_srst = aice_usb_assert_srst,
4054         /** */
4055         .run = aice_usb_run,
4056         /** */
4057         .halt = aice_usb_halt,
4058         /** */
4059         .step = aice_usb_step,
4060         /** */
4061         .read_reg = aice_usb_read_reg,
4062         /** */
4063         .write_reg = aice_usb_write_reg,
4064         /** */
4065         .read_reg_64 = aice_usb_read_reg_64,
4066         /** */
4067         .write_reg_64 = aice_usb_write_reg_64,
4068         /** */
4069         .read_mem_unit = aice_usb_read_memory_unit,
4070         /** */
4071         .write_mem_unit = aice_usb_write_memory_unit,
4072         /** */
4073         .read_mem_bulk = aice_usb_bulk_read_mem,
4074         /** */
4075         .write_mem_bulk = aice_usb_bulk_write_mem,
4076         /** */
4077         .read_debug_reg = aice_usb_read_debug_reg,
4078         /** */
4079         .write_debug_reg = aice_usb_write_debug_reg,
4080         /** */
4081         .set_jtag_clock = aice_usb_set_jtag_clock,
4082         /** */
4083         .memory_access = aice_usb_memory_access,
4084         /** */
4085         .memory_mode = aice_usb_memory_mode,
4086         /** */
4087         .read_tlb = aice_usb_read_tlb,
4088         /** */
4089         .cache_ctl = aice_usb_cache_ctl,
4090         /** */
4091         .set_retry_times = aice_usb_set_retry_times,
4092         /** */
4093         .program_edm = aice_usb_program_edm,
4094         /** */
4095         .set_command_mode = aice_usb_set_command_mode,
4096         /** */
4097         .execute = aice_usb_execute,
4098         /** */
4099         .set_custom_srst_script = aice_usb_set_custom_srst_script,
4100         /** */
4101         .set_custom_trst_script = aice_usb_set_custom_trst_script,
4102         /** */
4103         .set_custom_restart_script = aice_usb_set_custom_restart_script,
4104         /** */
4105         .set_count_to_check_dbger = aice_usb_set_count_to_check_dbger,
4106         /** */
4107         .set_data_endian = aice_usb_set_data_endian,
4108         /** */
4109         .profiling = aice_usb_profiling,
4110 };