1 /***************************************************************************
2 * Copyright (C) 2013 by Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
19 #ifndef OPENOCD_JTAG_AICE_AICE_PORT_H
20 #define OPENOCD_JTAG_AICE_AICE_PORT_H
22 #include <target/nds32_edm.h>
24 #define AICE_MAX_NUM_CORE (0x10)
26 #define ERROR_AICE_DISCONNECT (-200)
27 #define ERROR_AICE_TIMEOUT (-201)
29 enum aice_target_state_s {
36 AICE_TARGET_DEBUG_RUNNING,
39 enum aice_srst_type_s {
41 AICE_RESET_HOLD = 0x8,
44 enum aice_target_endian {
45 AICE_LITTLE_ENDIAN = 0,
76 AICE_SET_COMMAND_MODE,
78 AICE_SET_CUSTOM_SRST_SCRIPT,
79 AICE_SET_CUSTOM_TRST_SCRIPT,
80 AICE_SET_CUSTOM_RESTART_SCRIPT,
81 AICE_SET_COUNT_TO_CHECK_DBGER,
91 enum aice_cache_ctl_type {
92 AICE_CACHE_CTL_L1D_INVALALL = 0,
93 AICE_CACHE_CTL_L1D_VA_INVAL,
94 AICE_CACHE_CTL_L1D_WBALL,
95 AICE_CACHE_CTL_L1D_VA_WB,
96 AICE_CACHE_CTL_L1I_INVALALL,
97 AICE_CACHE_CTL_L1I_VA_INVAL,
100 enum aice_command_mode {
101 AICE_COMMAND_MODE_NORMAL,
102 AICE_COMMAND_MODE_PACK,
103 AICE_COMMAND_MODE_BATCH,
106 struct aice_port_param_s {
108 const char *device_desc;
123 const struct aice_port *port;
127 extern struct aice_port_api_s aice_usb_layout_api;
130 struct aice_port_api_s {
132 int (*open)(struct aice_port_param_s *param);
138 int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
140 int (*set_jtag_clock)(uint32_t a_clock);
142 int (*assert_srst)(uint32_t coreid, enum aice_srst_type_s srst);
144 int (*run)(uint32_t coreid);
146 int (*halt)(uint32_t coreid);
148 int (*step)(uint32_t coreid);
150 int (*read_reg)(uint32_t coreid, uint32_t num, uint32_t *val);
152 int (*write_reg)(uint32_t coreid, uint32_t num, uint32_t val);
154 int (*read_reg_64)(uint32_t coreid, uint32_t num, uint64_t *val);
156 int (*write_reg_64)(uint32_t coreid, uint32_t num, uint64_t val);
158 int (*read_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
159 uint32_t count, uint8_t *buffer);
161 int (*write_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
162 uint32_t count, const uint8_t *buffer);
164 int (*read_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
167 int (*write_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
168 const uint8_t *buffer);
170 int (*read_debug_reg)(uint32_t coreid, uint32_t addr, uint32_t *val);
172 int (*write_debug_reg)(uint32_t coreid, uint32_t addr, const uint32_t val);
175 int (*state)(uint32_t coreid, enum aice_target_state_s *state);
178 int (*memory_access)(uint32_t coreid, enum nds_memory_access a_access);
180 int (*memory_mode)(uint32_t coreid, enum nds_memory_select mem_select);
183 int (*read_tlb)(uint32_t coreid, target_addr_t virtual_address, target_addr_t *physical_address);
186 int (*cache_ctl)(uint32_t coreid, uint32_t subtype, uint32_t address);
189 int (*set_retry_times)(uint32_t a_retry_times);
192 int (*program_edm)(uint32_t coreid, char *command_sequence);
195 int (*set_command_mode)(enum aice_command_mode command_mode);
198 int (*execute)(uint32_t coreid, uint32_t *instructions, uint32_t instruction_num);
201 int (*set_custom_srst_script)(const char *script);
204 int (*set_custom_trst_script)(const char *script);
207 int (*set_custom_restart_script)(const char *script);
210 int (*set_count_to_check_dbger)(uint32_t count_to_check);
213 int (*set_data_endian)(uint32_t coreid, enum aice_target_endian target_data_endian);
216 int (*profiling)(uint32_t coreid, uint32_t interval, uint32_t iteration,
217 uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
220 #define AICE_PORT_UNKNOWN 0
221 #define AICE_PORT_AICE_USB 1
222 #define AICE_PORT_AICE_PIPE 2
231 struct aice_port_api_s *const api;
235 const struct aice_port *aice_port_get_list(void);
237 #endif /* OPENOCD_JTAG_AICE_AICE_PORT_H */