1 /***************************************************************************
2 * Copyright (C) 2013 by Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
23 #include <target/nds32_edm.h>
25 #define ERROR_AICE_DISCONNECT (-200)
26 #define ERROR_AICE_TIMEOUT (-201)
28 enum aice_target_state_s {
35 AICE_TARGET_DEBUG_RUNNING,
38 enum aice_srst_type_s {
40 AICE_RESET_HOLD = 0x8,
43 enum aice_target_endian {
44 AICE_LITTLE_ENDIAN = 0,
76 AICE_SET_COMMAND_MODE,
78 AICE_SET_CUSTOM_SRST_SCRIPT,
79 AICE_SET_CUSTOM_TRST_SCRIPT,
80 AICE_SET_CUSTOM_RESTART_SCRIPT,
81 AICE_SET_COUNT_TO_CHECK_DBGER,
91 enum aice_cache_ctl_type {
92 AICE_CACHE_CTL_L1D_INVALALL = 0,
93 AICE_CACHE_CTL_L1D_VA_INVAL,
94 AICE_CACHE_CTL_L1D_WBALL,
95 AICE_CACHE_CTL_L1D_VA_WB,
96 AICE_CACHE_CTL_L1I_INVALALL,
97 AICE_CACHE_CTL_L1I_VA_INVAL,
100 enum aice_command_mode {
101 AICE_COMMAND_MODE_NORMAL,
102 AICE_COMMAND_MODE_PACK,
103 AICE_COMMAND_MODE_BATCH,
106 struct aice_port_param_s {
121 struct aice_port_param_s param;
123 const struct aice_port *port;
125 uint32_t retry_times;
127 uint32_t count_to_check_dbger;
131 extern struct aice_port_api_s aice_usb_layout_api;
134 struct aice_port_api_s {
136 int (*open)(struct aice_port_param_s *param);
142 int (*assert_srst)(enum aice_srst_type_s srst);
150 int (*read_reg)(uint32_t num, uint32_t *val);
152 int (*write_reg)(uint32_t num, uint32_t val);
154 int (*read_reg_64)(uint32_t num, uint64_t *val);
156 int (*write_reg_64)(uint32_t num, uint64_t val);
158 int (*read_mem_unit)(uint32_t addr, uint32_t size, uint32_t count,
161 int (*write_mem_unit)(uint32_t addr, uint32_t size, uint32_t count,
162 const uint8_t *buffer);
164 int (*read_mem_bulk)(uint32_t addr, uint32_t length,
167 int (*write_mem_bulk)(uint32_t addr, uint32_t length,
168 const uint8_t *buffer);
170 int (*read_debug_reg)(uint32_t addr, uint32_t *val);
172 int (*write_debug_reg)(uint32_t addr, const uint32_t val);
175 int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
177 int (*state)(enum aice_target_state_s *state);
180 int (*set_jtag_clock)(uint32_t a_clock);
182 int (*select_target)(uint32_t target_id);
185 int (*memory_access)(enum nds_memory_access a_access);
187 int (*memory_mode)(enum nds_memory_select mem_select);
190 int (*read_tlb)(uint32_t virtual_address, uint32_t *physical_address);
193 int (*cache_ctl)(uint32_t subtype, uint32_t address);
196 int (*set_retry_times)(uint32_t a_retry_times);
199 int (*program_edm)(char *command_sequence);
202 int (*set_command_mode)(enum aice_command_mode command_mode);
205 int (*execute)(uint32_t *instructions, uint32_t instruction_num);
208 int (*set_custom_srst_script)(const char *script);
211 int (*set_custom_trst_script)(const char *script);
214 int (*set_custom_restart_script)(const char *script);
217 int (*set_count_to_check_dbger)(uint32_t count_to_check);
220 int (*set_data_endian)(enum aice_target_endian target_data_endian);
223 #define AICE_PORT_UNKNOWN 0
224 #define AICE_PORT_AICE_USB 1
225 #define AICE_PORT_AICE_PIPE 2
234 struct aice_port_api_s *api;
238 const struct aice_port *aice_port_get_list(void);