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   1 /***************************************************************************
   2  *   (c) Copyright 2007, 2008 by Christopher Kilgour                       *
   3  *   techie |_at_| whiterocker |_dot_| com                                 *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include "log.h"
  26 #include "tms470.h"
  27 #include <string.h>
  28 #include <unistd.h>
  29
  30 int tms470_register_commands(struct command_context_s *cmd_ctx);
  31 int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  32 int tms470_erase(struct flash_bank_s *bank, int first, int last);
  33 int tms470_protect(struct flash_bank_s *bank, int set, int first, int last);
  34 int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count);
  35 int tms470_probe(struct flash_bank_s *bank);
  36 int tms470_auto_probe(struct flash_bank_s *bank);
  37 int tms470_erase_check(struct flash_bank_s *bank);
  38 int tms470_protect_check(struct flash_bank_s *bank);
  39 int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size);
  40
  41 flash_driver_t tms470_flash = {
  42         .name = "tms470",
  43         .register_commands = tms470_register_commands,
  44         .flash_bank_command = tms470_flash_bank_command,
  45         .erase = tms470_erase,
  46         .protect = tms470_protect,
  47         .write = tms470_write,
  48         .probe = tms470_probe,
  49         .auto_probe = tms470_auto_probe,
  50         .erase_check = tms470_erase_check,
  51         .protect_check = tms470_protect_check,
  52         .info = tms470_info
  53 };
  54
  55 /* ----------------------------------------------------------------------
  56                       Internal Support, Helpers
  57    ---------------------------------------------------------------------- */
  58
  59 const flash_sector_t TMS470R1A256_SECTORS[] = {
  60         {0x00000000, 0x00002000, -1, -1},
  61         {0x00002000, 0x00002000, -1, -1},
  62         {0x00004000, 0x00002000, -1, -1},
  63         {0x00006000, 0x00002000, -1, -1},
  64         {0x00008000, 0x00008000, -1, -1},
  65         {0x00010000, 0x00008000, -1, -1},
  66         {0x00018000, 0x00008000, -1, -1},
  67         {0x00020000, 0x00008000, -1, -1},
  68         {0x00028000, 0x00008000, -1, -1},
  69         {0x00030000, 0x00008000, -1, -1},
  70         {0x00038000, 0x00002000, -1, -1},
  71         {0x0003A000, 0x00002000, -1, -1},
  72         {0x0003C000, 0x00002000, -1, -1},
  73         {0x0003E000, 0x00002000, -1, -1},
  74 };
  75
  76 #define TMS470R1A256_NUM_SECTORS \
  77   (sizeof(TMS470R1A256_SECTORS)/sizeof(TMS470R1A256_SECTORS[0]))
  78
  79 const flash_sector_t TMS470R1A288_BANK0_SECTORS[] = {
  80         {0x00000000, 0x00002000, -1, -1},
  81         {0x00002000, 0x00002000, -1, -1},
  82         {0x00004000, 0x00002000, -1, -1},
  83         {0x00006000, 0x00002000, -1, -1},
  84 };
  85
  86 #define TMS470R1A288_BANK0_NUM_SECTORS \
  87   (sizeof(TMS470R1A288_BANK0_SECTORS)/sizeof(TMS470R1A288_BANK0_SECTORS[0]))
  88
  89 const flash_sector_t TMS470R1A288_BANK1_SECTORS[] = {
  90         {0x00040000, 0x00010000, -1, -1},
  91         {0x00050000, 0x00010000, -1, -1},
  92         {0x00060000, 0x00010000, -1, -1},
  93         {0x00070000, 0x00010000, -1, -1},
  94 };
  95
  96 #define TMS470R1A288_BANK1_NUM_SECTORS \
  97   (sizeof(TMS470R1A288_BANK1_SECTORS)/sizeof(TMS470R1A288_BANK1_SECTORS[0]))
  98
  99 /* ---------------------------------------------------------------------- */
 100
 101 int tms470_read_part_info(struct flash_bank_s *bank)
 102 {
 103         tms470_flash_bank_t *tms470_info = bank->driver_priv;
 104         target_t *target = bank->target;
 105         u32 device_ident_reg;
 106         u32 silicon_version;
 107         u32 technology_family;
 108         u32 rom_flash;
 109         u32 part_number;
 110         char *part_name;
 111
 112         /* we shall not rely on the caller in this test, this function allocates memory,
 113            thus and executing the code more than once may cause memory leak */
 114         if (tms470_info->device_ident_reg)
 115           return ERROR_OK;
 116
 117         /* read and parse the device identification register */
 118         target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
 119
 120         INFO("device_ident_reg=0x%08x", device_ident_reg);
 121
 122         if ((device_ident_reg & 7) == 0)
 123         {
 124                 WARNING("Cannot identify target as a TMS470 family.");
 125                 return ERROR_FLASH_OPERATION_FAILED;
 126         }
 127
 128         silicon_version = (device_ident_reg >> 12) & 0xF;
 129         technology_family = (device_ident_reg >> 11) & 1;
 130         rom_flash = (device_ident_reg >> 10) & 1;
 131         part_number = (device_ident_reg >> 3) & 0x7f;
 132
 133         /*
 134          * If the part number is known, determine if the flash bank is valid
 135          * based on the base address being within the known flash bank
 136          * ranges.  Then fixup/complete the remaining fields of the flash
 137          * bank structure.
 138          */
 139         switch (part_number)
 140         {
 141         case 0x0a:
 142                 part_name = "TMS470R1A256";
 143
 144                 if (bank->base >= 0x00040000)
 145                 {
 146                         ERROR("No %s flash bank contains base address 0x%08x.", part_name, bank->base);
 147                         return ERROR_FLASH_OPERATION_FAILED;
 148                 }
 149                 tms470_info->ordinal = 0;
 150                 bank->base = 0x00000000;
 151                 bank->size = 256 * 1024;
 152                 bank->num_sectors = TMS470R1A256_NUM_SECTORS;
 153                 bank->sectors = malloc(sizeof(TMS470R1A256_SECTORS));
 154                 if (!bank->sectors)
 155                 {
 156                         return ERROR_FLASH_OPERATION_FAILED;
 157                 }
 158                 (void)memcpy(bank->sectors, TMS470R1A256_SECTORS, sizeof(TMS470R1A256_SECTORS));
 159                 break;
 160
 161         case 0x2b:
 162                 part_name = "TMS470R1A288";
 163
 164                 if ((bank->base >= 0x00000000) && (bank->base < 0x00008000))
 165                 {
 166                         tms470_info->ordinal = 0;
 167                         bank->base = 0x00000000;
 168                         bank->size = 32 * 1024;
 169                         bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS;
 170                         bank->sectors = malloc(sizeof(TMS470R1A288_BANK0_SECTORS));
 171                         if (!bank->sectors)
 172                         {
 173                                 return ERROR_FLASH_OPERATION_FAILED;
 174                         }
 175                         (void)memcpy(bank->sectors, TMS470R1A288_BANK0_SECTORS, sizeof(TMS470R1A288_BANK0_SECTORS));
 176                 }
 177                 else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000))
 178                 {
 179                         tms470_info->ordinal = 1;
 180                         bank->base = 0x00040000;
 181                         bank->size = 256 * 1024;
 182                         bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS;
 183                         bank->sectors = malloc(sizeof(TMS470R1A288_BANK1_SECTORS));
 184                         if (!bank->sectors)
 185                         {
 186                                 return ERROR_FLASH_OPERATION_FAILED;
 187                         }
 188                         (void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS, sizeof(TMS470R1A288_BANK1_SECTORS));
 189                 }
 190                 else
 191                 {
 192                         ERROR("No %s flash bank contains base address 0x%08x.", part_name, bank->base);
 193                         return ERROR_FLASH_OPERATION_FAILED;
 194                 }
 195                 break;
 196
 197         default:
 198                 WARNING("Could not identify part 0x%02x as a member of the TMS470 family.", part_number);
 199                 return ERROR_FLASH_OPERATION_FAILED;
 200         }
 201
 202         /* turn off memory selects */
 203         target_write_u32(target, 0xFFFFFFE4, 0x00000000);
 204         target_write_u32(target, 0xFFFFFFE0, 0x00000000);
 205
 206         bank->chip_width = 32;
 207         bank->bus_width = 32;
 208
 209         INFO("Identified %s, ver=%d, core=%s, nvmem=%s.", part_name, silicon_version, (technology_family ? "1.8v" : "3.3v"), (rom_flash ? "rom" : "flash"));
 210
 211         tms470_info->device_ident_reg = device_ident_reg;
 212         tms470_info->silicon_version = silicon_version;
 213         tms470_info->technology_family = technology_family;
 214         tms470_info->rom_flash = rom_flash;
 215         tms470_info->part_number = part_number;
 216         tms470_info->part_name = part_name;
 217
 218         /*
 219          * Disable reset on address access violation.
 220          */
 221         target_write_u32(target, 0xFFFFFFE0, 0x00004007);
 222
 223         return ERROR_OK;
 224 }
 225
 226 /* ---------------------------------------------------------------------- */
 227
 228 u32 keysSet = 0;
 229 u32 flashKeys[4];
 230
 231 int tms470_handle_flash_keyset_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 232 {
 233         if (argc > 4)
 234         {
 235                 command_print(cmd_ctx, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
 236                 return ERROR_INVALID_ARGUMENTS;
 237         }
 238         else if (argc == 4)
 239         {
 240                 int i;
 241
 242                 for (i = 0; i < 4; i++)
 243                 {
 244                         int start = (0 == strncmp(args[i], "0x", 2)) ? 2 : 0;
 245
 246                         if (1 != sscanf(&args[i][start], "%x", &flashKeys[i]))
 247                         {
 248                                 command_print(cmd_ctx, "could not process flash key %s", args[i]);
 249                                 ERROR("could not process flash key %s", args[i]);
 250                                 return ERROR_INVALID_ARGUMENTS;
 251                         }
 252                 }
 253
 254                 keysSet = 1;
 255         }
 256         else if (argc != 0)
 257         {
 258                 command_print(cmd_ctx, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
 259                 return ERROR_INVALID_ARGUMENTS;
 260         }
 261
 262         if (keysSet)
 263         {
 264                 command_print(cmd_ctx, "using flash keys 0x%08x, 0x%08x, 0x%08x, 0x%08x", flashKeys[0], flashKeys[1], flashKeys[2], flashKeys[3]);
 265         }
 266         else
 267         {
 268                 command_print(cmd_ctx, "flash keys not set");
 269         }
 270
 271         return ERROR_OK;
 272 }
 273
 274 const u32 FLASH_KEYS_ALL_ONES[] = { 0xFFFFFFFF, 0xFFFFFFFF,
 275         0xFFFFFFFF, 0xFFFFFFFF,
 276 };
 277
 278 const u32 FLASH_KEYS_ALL_ZEROS[] = { 0x00000000, 0x00000000,
 279         0x00000000, 0x00000000,
 280 };
 281
 282 const u32 FLASH_KEYS_MIX1[] = { 0xf0fff0ff, 0xf0fff0ff,
 283         0xf0fff0ff, 0xf0fff0ff
 284 };
 285
 286 const u32 FLASH_KEYS_MIX2[] = { 0x0000ffff, 0x0000ffff,
 287         0x0000ffff, 0x0000ffff
 288 };
 289
 290 /* ---------------------------------------------------------------------- */
 291
 292 int oscMHz = 12;
 293
 294 int tms470_handle_osc_megahertz_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 295 {
 296         if (argc > 1)
 297         {
 298                 command_print(cmd_ctx, "tms470 osc_megahertz <MHz>");
 299                 return ERROR_INVALID_ARGUMENTS;
 300         }
 301         else if (argc == 1)
 302         {
 303                 sscanf(args[0], "%d", &oscMHz);
 304         }
 305
 306         if (oscMHz <= 0)
 307         {
 308                 ERROR("osc_megahertz must be positive and non-zero!");
 309                 command_print(cmd_ctx, "osc_megahertz must be positive and non-zero!");
 310                 oscMHz = 12;
 311                 return ERROR_INVALID_ARGUMENTS;
 312         }
 313
 314         command_print(cmd_ctx, "osc_megahertz=%d", oscMHz);
 315
 316         return ERROR_OK;
 317 }
 318
 319 /* ---------------------------------------------------------------------- */
 320
 321 int plldis = 0;
 322
 323 int tms470_handle_plldis_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 324 {
 325         if (argc > 1)
 326         {
 327                 command_print(cmd_ctx, "tms470 plldis <0|1>");
 328                 return ERROR_INVALID_ARGUMENTS;
 329         }
 330         else if (argc == 1)
 331         {
 332                 sscanf(args[0], "%d", &plldis);
 333                 plldis = plldis ? 1 : 0;
 334         }
 335
 336         command_print(cmd_ctx, "plldis=%d", plldis);
 337
 338         return ERROR_OK;
 339 }
 340
 341 /* ---------------------------------------------------------------------- */
 342
 343 int tms470_check_flash_unlocked(target_t * target)
 344 {
 345         u32 fmbbusy;
 346
 347         target_read_u32(target, 0xFFE89C08, &fmbbusy);
 348         INFO("tms470 fmbbusy=0x%08x -> %s", fmbbusy, fmbbusy & 0x8000 ? "unlocked" : "LOCKED");
 349         return fmbbusy & 0x8000 ? ERROR_OK : ERROR_FLASH_OPERATION_FAILED;
 350 }
 351
 352 /* ---------------------------------------------------------------------- */
 353
 354 int tms470_try_flash_keys(target_t * target, const u32 * key_set)
 355 {
 356         u32 glbctrl, fmmstat;
 357         int retval = ERROR_FLASH_OPERATION_FAILED;
 358
 359         /* set GLBCTRL.4  */
 360         target_read_u32(target, 0xFFFFFFDC, &glbctrl);
 361         target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
 362
 363         /* only perform the key match when 3VSTAT is clear */
 364         target_read_u32(target, 0xFFE8BC0C, &fmmstat);
 365         if (!(fmmstat & 0x08))
 366         {
 367                 unsigned i;
 368                 u32 fmbptr, fmbac2, orig_fmregopt;
 369
 370                 target_write_u32(target, 0xFFE8BC04, fmmstat & ~0x07);
 371
 372                 /* wait for pump ready */
 373                 do
 374                 {
 375                         target_read_u32(target, 0xFFE8A814, &fmbptr);
 376                         usleep(1000);
 377                 }
 378                 while (!(fmbptr & 0x0200));
 379
 380                 /* force max wait states */
 381                 target_read_u32(target, 0xFFE88004, &fmbac2);
 382                 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
 383
 384                 /* save current access mode, force normal read mode */
 385                 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
 386                 target_write_u32(target, 0xFFE89C00, 0x00);
 387
 388                 for (i = 0; i < 4; i++)
 389                 {
 390                         u32 tmp;
 391
 392                         /* There is no point displaying the value of tmp, it is
 393                          * filtered by the chip.  The purpose of this read is to
 394                          * prime the unlocking logic rather than read out the value.
 395                          */
 396                         target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
 397
 398                         INFO("tms470 writing fmpkey=0x%08x", key_set[i]);
 399                         target_write_u32(target, 0xFFE89C0C, key_set[i]);
 400                 }
 401
 402                 if (ERROR_OK == tms470_check_flash_unlocked(target))
 403                 {
 404                         /*
 405                          * There seems to be a side-effect of reading the FMPKEY
 406                          * register in that it re-enables the protection.  So we
 407                          * re-enable it.
 408                          */
 409                         for (i = 0; i < 4; i++)
 410                         {
 411                                 u32 tmp;
 412
 413                                 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
 414                                 target_write_u32(target, 0xFFE89C0C, key_set[i]);
 415                         }
 416                         retval = ERROR_OK;
 417                 }
 418
 419                 /* restore settings */
 420                 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
 421                 target_write_u32(target, 0xFFE88004, fmbac2);
 422         }
 423
 424         /* clear config bit */
 425         target_write_u32(target, 0xFFFFFFDC, glbctrl);
 426
 427         return retval;
 428 }
 429
 430 /* ---------------------------------------------------------------------- */
 431
 432 int tms470_unlock_flash(struct flash_bank_s *bank)
 433 {
 434         target_t *target = bank->target;
 435         const u32 *p_key_sets[5];
 436         unsigned i, key_set_count;
 437
 438         if (keysSet)
 439         {
 440                 p_key_sets[0] = flashKeys;
 441                 p_key_sets[1] = FLASH_KEYS_ALL_ONES;
 442                 p_key_sets[2] = FLASH_KEYS_ALL_ZEROS;
 443                 p_key_sets[3] = FLASH_KEYS_MIX1;
 444                 p_key_sets[4] = FLASH_KEYS_MIX2;
 445         }
 446         else
 447         {
 448                 key_set_count = 4;
 449                 p_key_sets[0] = FLASH_KEYS_ALL_ONES;
 450                 p_key_sets[1] = FLASH_KEYS_ALL_ZEROS;
 451                 p_key_sets[2] = FLASH_KEYS_MIX1;
 452                 p_key_sets[3] = FLASH_KEYS_MIX2;
 453         }
 454
 455         for (i = 0; i < key_set_count; i++)
 456         {
 457                 if (tms470_try_flash_keys(target, p_key_sets[i]) == ERROR_OK)
 458                 {
 459                         INFO("tms470 flash is unlocked");
 460                         return ERROR_OK;
 461                 }
 462         }
 463
 464         WARNING("tms470 could not unlock flash memory protection level 2");
 465         return ERROR_FLASH_OPERATION_FAILED;
 466 }
 467
 468 /* ---------------------------------------------------------------------- */
 469
 470 int tms470_flash_initialize_internal_state_machine(struct flash_bank_s *bank)
 471 {
 472         u32 fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
 473         target_t *target = bank->target;
 474         tms470_flash_bank_t *tms470_info = bank->driver_priv;
 475         int result = ERROR_OK;
 476
 477         /*
 478          * Select the desired bank to be programmed by writing BANK[2:0] of
 479          * FMMAC2.
 480          */
 481         target_read_u32(target, 0xFFE8BC04, &fmmac2);
 482         fmmac2 &= ~0x0007;
 483         fmmac2 |= (tms470_info->ordinal & 7);
 484         target_write_u32(target, 0xFFE8BC04, fmmac2);
 485         DEBUG("set fmmac2=0x%04x", fmmac2);
 486
 487         /*
 488          * Disable level 1 sector protection by setting bit 15 of FMMAC1.
 489          */
 490         target_read_u32(target, 0xFFE8BC00, &fmmac1);
 491         fmmac1 |= 0x8000;
 492         target_write_u32(target, 0xFFE8BC00, fmmac1);
 493         DEBUG("set fmmac1=0x%04x", fmmac1);
 494
 495         /*
 496          * FMTCREG=0x2fc0;
 497          */
 498         target_write_u32(target, 0xFFE8BC10, 0x2fc0);
 499         DEBUG("set fmtcreg=0x2fc0");
 500
 501         /*
 502          * MAXPP=50
 503          */
 504         target_write_u32(target, 0xFFE8A07C, 50);
 505         DEBUG("set fmmaxpp=50");
 506
 507         /*
 508          * MAXCP=0xf000+2000
 509          */
 510         target_write_u32(target, 0xFFE8A084, 0xf000 + 2000);
 511         DEBUG("set fmmaxcp=0x%04x", 0xf000 + 2000);
 512
 513         /*
 514          * configure VHV
 515          */
 516         target_read_u32(target, 0xFFE8A080, &fmmaxep);
 517         if (fmmaxep == 0xf000)
 518         {
 519                 fmmaxep = 0xf000 + 4095;
 520                 target_write_u32(target, 0xFFE8A80C, 0x9964);
 521                 DEBUG("set fmptr3=0x9964");
 522         }
 523         else
 524         {
 525                 fmmaxep = 0xa000 + 4095;
 526                 target_write_u32(target, 0xFFE8A80C, 0x9b64);
 527                 DEBUG("set fmptr3=0x9b64");
 528         }
 529         target_write_u32(target, 0xFFE8A080, fmmaxep);
 530         DEBUG("set fmmaxep=0x%04x", fmmaxep);
 531
 532         /*
 533          * FMPTR4=0xa000
 534          */
 535         target_write_u32(target, 0xFFE8A810, 0xa000);
 536         DEBUG("set fmptr4=0xa000");
 537
 538         /*
 539          * FMPESETUP, delay parameter selected based on clock frequency.
 540          *
 541          * According to the TI App Note SPNU257 and flashing code, delay is
 542          * int((sysclk(MHz) + 1) / 2), with a minimum of 5.  The system
 543          * clock is usually derived from the ZPLL module, and selected by
 544          * the plldis global.
 545          */
 546         target_read_u32(target, 0xFFFFFFDC, &glbctrl);
 547         sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * oscMHz / (1 + (glbctrl & 7));
 548         delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
 549         target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
 550         DEBUG("set fmpsetup=0x%04x", (delay << 4) | (delay << 8));
 551
 552         /*
 553          * FMPVEVACCESS, based on delay.
 554          */
 555         k = delay | (delay << 8);
 556         target_write_u32(target, 0xFFE8A05C, k);
 557         DEBUG("set fmpvevaccess=0x%04x", k);
 558
 559         /*
 560          * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
 561          */
 562         k <<= 1;
 563         target_write_u32(target, 0xFFE8A034, k);
 564         DEBUG("set fmpchold=0x%04x", k);
 565         target_write_u32(target, 0xFFE8A040, k);
 566         DEBUG("set fmpvevhold=0x%04x", k);
 567         target_write_u32(target, 0xFFE8A024, k);
 568         DEBUG("set fmpvevsetup=0x%04x", k);
 569
 570         /*
 571          * FMCVACCESS, based on delay.
 572          */
 573         k = delay * 16;
 574         target_write_u32(target, 0xFFE8A060, k);
 575         DEBUG("set fmcvaccess=0x%04x", k);
 576
 577         /*
 578          * FMCSETUP, based on delay.
 579          */
 580         k = 0x3000 | delay * 20;
 581         target_write_u32(target, 0xFFE8A020, k);
 582         DEBUG("set fmcsetup=0x%04x", k);
 583
 584         /*
 585          * FMEHOLD, based on delay.
 586          */
 587         k = (delay * 20) << 2;
 588         target_write_u32(target, 0xFFE8A038, k);
 589         DEBUG("set fmehold=0x%04x", k);
 590
 591         /*
 592          * PWIDTH, CWIDTH, EWIDTH, based on delay.
 593          */
 594         target_write_u32(target, 0xFFE8A050, delay * 8);
 595         DEBUG("set fmpwidth=0x%04x", delay * 8);
 596         target_write_u32(target, 0xFFE8A058, delay * 1000);
 597         DEBUG("set fmcwidth=0x%04x", delay * 1000);
 598         target_write_u32(target, 0xFFE8A054, delay * 5400);
 599         DEBUG("set fmewidth=0x%04x", delay * 5400);
 600
 601         return result;
 602 }
 603
 604 /* ---------------------------------------------------------------------- */
 605
 606 int tms470_flash_status(struct flash_bank_s *bank)
 607 {
 608         target_t *target = bank->target;
 609         int result = ERROR_OK;
 610         u32 fmmstat;
 611
 612         target_read_u32(target, 0xFFE8BC0C, &fmmstat);
 613         DEBUG("set fmmstat=0x%04x", fmmstat);
 614
 615         if (fmmstat & 0x0080)
 616         {
 617                 WARNING("tms470 flash command: erase still active after busy clear.");
 618                 result = ERROR_FLASH_OPERATION_FAILED;
 619         }
 620
 621         if (fmmstat & 0x0040)
 622         {
 623                 WARNING("tms470 flash command: program still active after busy clear.");
 624                 result = ERROR_FLASH_OPERATION_FAILED;
 625         }
 626
 627         if (fmmstat & 0x0020)
 628         {
 629                 WARNING("tms470 flash command: invalid data command.");
 630                 result = ERROR_FLASH_OPERATION_FAILED;
 631         }
 632
 633         if (fmmstat & 0x0010)
 634         {
 635                 WARNING("tms470 flash command: program, erase or validate sector failed.");
 636                 result = ERROR_FLASH_OPERATION_FAILED;
 637         }
 638
 639         if (fmmstat & 0x0008)
 640         {
 641                 WARNING("tms470 flash command: voltage instability detected.");
 642                 result = ERROR_FLASH_OPERATION_FAILED;
 643         }
 644
 645         if (fmmstat & 0x0006)
 646         {
 647                 WARNING("tms470 flash command: command suspend detected.");
 648                 result = ERROR_FLASH_OPERATION_FAILED;
 649         }
 650
 651         if (fmmstat & 0x0001)
 652         {
 653                 WARNING("tms470 flash command: sector was locked.");
 654                 result = ERROR_FLASH_OPERATION_FAILED;
 655         }
 656
 657         return result;
 658 }
 659
 660 /* ---------------------------------------------------------------------- */
 661
 662 int tms470_erase_sector(struct flash_bank_s *bank, int sector)
 663 {
 664         u32 glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
 665         target_t *target = bank->target;
 666         u32 flashAddr = bank->base + bank->sectors[sector].offset;
 667         int result = ERROR_OK;
 668
 669         /*
 670          * Set the bit GLBCTRL4 of the GLBCTRL register (in the System
 671          * module) to enable writing to the flash registers }.
 672          */
 673         target_read_u32(target, 0xFFFFFFDC, &glbctrl);
 674         target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
 675         DEBUG("set glbctrl=0x%08x", glbctrl | 0x10);
 676
 677         /* Force normal read mode. */
 678         target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
 679         target_write_u32(target, 0xFFE89C00, 0);
 680         DEBUG("set fmregopt=0x%08x", 0);
 681
 682         (void)tms470_flash_initialize_internal_state_machine(bank);
 683
 684         /*
 685          * Select one or more bits in FMBSEA or FMBSEB to disable Level 1
 686          * protection for the particular sector to be erased/written.
 687          */
 688         if (sector < 16)
 689         {
 690                 target_read_u32(target, 0xFFE88008, &fmbsea);
 691                 target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
 692                 DEBUG("set fmbsea=0x%04x", fmbsea | (1 << sector));
 693         }
 694         else
 695         {
 696                 target_read_u32(target, 0xFFE8800C, &fmbseb);
 697                 target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
 698                 DEBUG("set fmbseb=0x%04x", fmbseb | (1 << (sector - 16)));
 699         }
 700         bank->sectors[sector].is_protected = 0;
 701
 702         /*
 703          * clear status regiser, sent erase command, kickoff erase
 704          */
 705         target_write_u16(target, flashAddr, 0x0040);
 706         DEBUG("write *(u16 *)0x%08x=0x0040", flashAddr);
 707         target_write_u16(target, flashAddr, 0x0020);
 708         DEBUG("write *(u16 *)0x%08x=0x0020", flashAddr);
 709         target_write_u16(target, flashAddr, 0xffff);
 710         DEBUG("write *(u16 *)0x%08x=0xffff", flashAddr);
 711
 712         /*
 713          * Monitor FMMSTAT, busy until clear, then check and other flags for
 714          * ultimate result of the operation.
 715          */
 716         do
 717         {
 718                 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
 719                 if (fmmstat & 0x0100)
 720                 {
 721                         usleep(1000);
 722                 }
 723         }
 724         while (fmmstat & 0x0100);
 725
 726         result = tms470_flash_status(bank);
 727
 728         if (sector < 16)
 729         {
 730                 target_write_u32(target, 0xFFE88008, fmbsea);
 731                 DEBUG("set fmbsea=0x%04x", fmbsea);
 732                 bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
 733         }
 734         else
 735         {
 736                 target_write_u32(target, 0xFFE8800C, fmbseb);
 737                 DEBUG("set fmbseb=0x%04x", fmbseb);
 738                 bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
 739         }
 740         target_write_u32(target, 0xFFE89C00, orig_fmregopt);
 741         DEBUG("set fmregopt=0x%08x", orig_fmregopt);
 742         target_write_u32(target, 0xFFFFFFDC, glbctrl);
 743         DEBUG("set glbctrl=0x%08x", glbctrl);
 744
 745         if (result == ERROR_OK)
 746         {
 747                 bank->sectors[sector].is_erased = 1;
 748         }
 749
 750         return result;
 751 }
 752
 753 /* ----------------------------------------------------------------------
 754               Implementation of Flash Driver Interfaces
 755    ---------------------------------------------------------------------- */
 756
 757 int tms470_register_commands(struct command_context_s *cmd_ctx)
 758 {
 759         command_t *tms470_cmd = register_command(cmd_ctx, NULL, "tms470", NULL, COMMAND_ANY, "applies to TI tms470 family");
 760
 761         register_command(cmd_ctx, tms470_cmd, "flash_keyset", tms470_handle_flash_keyset_command, COMMAND_ANY, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
 762         register_command(cmd_ctx, tms470_cmd, "osc_megahertz", tms470_handle_osc_megahertz_command, COMMAND_ANY, "tms470 osc_megahertz <MHz>");
 763         register_command(cmd_ctx, tms470_cmd, "plldis", tms470_handle_plldis_command, COMMAND_ANY, "tms470 plldis <0/1>");
 764
 765         return ERROR_OK;
 766 }
 767
 768 /* ---------------------------------------------------------------------- */
 769
 770 int tms470_erase(struct flash_bank_s *bank, int first, int last)
 771 {
 772         tms470_flash_bank_t *tms470_info = bank->driver_priv;
 773         int sector, result = ERROR_OK;
 774
 775         if (bank->target->state != TARGET_HALTED)
 776         {
 777                 return ERROR_TARGET_NOT_HALTED;
 778         }
 779
 780         tms470_read_part_info(bank);
 781
 782         if ((first < 0) || (first >= bank->num_sectors) || (last < 0) || (last >= bank->num_sectors) || (first > last))
 783         {
 784                 ERROR("Sector range %d to %d invalid.", first, last);
 785                 return ERROR_FLASH_SECTOR_INVALID;
 786         }
 787
 788         result = tms470_unlock_flash(bank);
 789         if (result != ERROR_OK)
 790         {
 791                 return result;
 792         }
 793
 794         for (sector = first; sector <= last; sector++)
 795         {
 796                 INFO("Erasing tms470 bank %d sector %d...", tms470_info->ordinal, sector);
 797
 798                 result = tms470_erase_sector(bank, sector);
 799
 800                 if (result != ERROR_OK)
 801                 {
 802                         ERROR("tms470 could not erase flash sector.");
 803                         break;
 804                 }
 805                 else
 806                 {
 807                         INFO("sector erased successfully.");
 808                 }
 809         }
 810
 811         return result;
 812 }
 813
 814 /* ---------------------------------------------------------------------- */
 815
 816 int tms470_protect(struct flash_bank_s *bank, int set, int first, int last)
 817 {
 818         tms470_flash_bank_t *tms470_info = bank->driver_priv;
 819         target_t *target = bank->target;
 820         u32 fmmac2, fmbsea, fmbseb;
 821         int sector;
 822
 823         if (target->state != TARGET_HALTED)
 824         {
 825                 return ERROR_TARGET_NOT_HALTED;
 826         }
 827
 828         tms470_read_part_info(bank);
 829
 830         if ((first < 0) || (first >= bank->num_sectors) || (last < 0) || (last >= bank->num_sectors) || (first > last))
 831         {
 832                 ERROR("Sector range %d to %d invalid.", first, last);
 833                 return ERROR_FLASH_SECTOR_INVALID;
 834         }
 835
 836         /* enable the appropriate bank */
 837         target_read_u32(target, 0xFFE8BC04, &fmmac2);
 838         target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
 839
 840         /* get the original sector proection flags for this bank */
 841         target_read_u32(target, 0xFFE88008, &fmbsea);
 842         target_read_u32(target, 0xFFE8800C, &fmbseb);
 843
 844         for (sector = 0; sector < bank->num_sectors; sector++)
 845         {
 846                 if (sector < 16)
 847                 {
 848                         fmbsea = set ? fmbsea & ~(1 << sector) : fmbsea | (1 << sector);
 849                         bank->sectors[sector].is_protected = set ? 1 : 0;
 850                 }
 851                 else
 852                 {
 853                         fmbseb = set ? fmbseb & ~(1 << (sector - 16)) : fmbseb | (1 << (sector - 16));
 854                         bank->sectors[sector].is_protected = set ? 1 : 0;
 855                 }
 856         }
 857
 858         /* update the protection bits */
 859         target_write_u32(target, 0xFFE88008, fmbsea);
 860         target_write_u32(target, 0xFFE8800C, fmbseb);
 861
 862         return ERROR_OK;
 863 }
 864
 865 /* ---------------------------------------------------------------------- */
 866
 867 int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count)
 868 {
 869         target_t *target = bank->target;
 870         tms470_flash_bank_t *tms470_info = bank->driver_priv;
 871         u32 glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
 872         int i, result = ERROR_OK;
 873
 874         if (target->state != TARGET_HALTED)
 875         {
 876                 return ERROR_TARGET_NOT_HALTED;
 877         }
 878
 879         tms470_read_part_info(bank);
 880
 881         INFO("Writing %d bytes starting at 0x%08x", count, bank->base + offset);
 882
 883         /* set GLBCTRL.4  */
 884         target_read_u32(target, 0xFFFFFFDC, &glbctrl);
 885         target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
 886
 887         (void)tms470_flash_initialize_internal_state_machine(bank);
 888
 889         /* force max wait states */
 890         target_read_u32(target, 0xFFE88004, &fmbac2);
 891         target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
 892
 893         /* save current access mode, force normal read mode */
 894         target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
 895         target_write_u32(target, 0xFFE89C00, 0x00);
 896
 897         /*
 898          * Disable Level 1 protection for all sectors to be erased/written.
 899          */
 900         target_read_u32(target, 0xFFE88008, &fmbsea);
 901         target_write_u32(target, 0xFFE88008, 0xffff);
 902         target_read_u32(target, 0xFFE8800C, &fmbseb);
 903         target_write_u32(target, 0xFFE8800C, 0xffff);
 904
 905         /* read MAXPP */
 906         target_read_u32(target, 0xFFE8A07C, &fmmaxpp);
 907
 908         for (i = 0; i < count; i += 2)
 909         {
 910                 u32 addr = bank->base + offset + i;
 911                 u16 word = (((u16) buffer[i]) << 8) | (u16) buffer[i + 1];
 912
 913                 if (word != 0xffff)
 914                 {
 915                         INFO("writing 0x%04x at 0x%08x", word, addr);
 916
 917                         /* clear status register */
 918                         target_write_u16(target, addr, 0x0040);
 919                         /* program flash command */
 920                         target_write_u16(target, addr, 0x0010);
 921                         /* burn the 16-bit word (big-endian) */
 922                         target_write_u16(target, addr, word);
 923
 924                         /*
 925                          * Monitor FMMSTAT, busy until clear, then check and other flags
 926                          * for ultimate result of the operation.
 927                          */
 928                         do
 929                         {
 930                                 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
 931                                 if (fmmstat & 0x0100)
 932                                 {
 933                                         usleep(1000);
 934                                 }
 935                         }
 936                         while (fmmstat & 0x0100);
 937
 938                         if (fmmstat & 0x3ff)
 939                         {
 940                                 ERROR("fmstat=0x%04x", fmmstat);
 941                                 ERROR("Could not program word 0x%04x at address 0x%08x.", word, addr);
 942                                 result = ERROR_FLASH_OPERATION_FAILED;
 943                                 break;
 944                         }
 945                 }
 946                 else
 947                 {
 948                         INFO("skipping 0xffff at 0x%08x", addr);
 949                 }
 950         }
 951
 952         /* restore */
 953         target_write_u32(target, 0xFFE88008, fmbsea);
 954         target_write_u32(target, 0xFFE8800C, fmbseb);
 955         target_write_u32(target, 0xFFE88004, fmbac2);
 956         target_write_u32(target, 0xFFE89C00, orig_fmregopt);
 957         target_write_u32(target, 0xFFFFFFDC, glbctrl);
 958
 959         return result;
 960 }
 961
 962 /* ---------------------------------------------------------------------- */
 963
 964 int tms470_probe(struct flash_bank_s *bank)
 965 {
 966         if (bank->target->state != TARGET_HALTED)
 967         {
 968                 WARNING("Cannot communicate... target not halted.");
 969                 return ERROR_TARGET_NOT_HALTED;
 970         }
 971
 972         return tms470_read_part_info(bank);
 973 }
 974
 975 int tms470_auto_probe(struct flash_bank_s *bank)
 976 {
 977         tms470_flash_bank_t *tms470_info = bank->driver_priv;
 978
 979         if (tms470_info->device_ident_reg)
 980                 return ERROR_OK;
 981         return tms470_probe(bank);
 982 }
 983
 984 /* ---------------------------------------------------------------------- */
 985
 986 int tms470_erase_check(struct flash_bank_s *bank)
 987 {
 988         target_t *target = bank->target;
 989         tms470_flash_bank_t *tms470_info = bank->driver_priv;
 990         int sector, result = ERROR_OK;
 991         u32 fmmac2, fmbac2, glbctrl, orig_fmregopt;
 992         static u8 buffer[64 * 1024];
 993
 994         if (target->state != TARGET_HALTED)
 995         {
 996                 return ERROR_TARGET_NOT_HALTED;
 997         }
 998
 999         if (!tms470_info->device_ident_reg)
1000         {
1001                 tms470_read_part_info(bank);
1002         }
1003
1004         /* set GLBCTRL.4  */
1005         target_read_u32(target, 0xFFFFFFDC, &glbctrl);
1006         target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
1007
1008         /* save current access mode, force normal read mode */
1009         target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
1010         target_write_u32(target, 0xFFE89C00, 0x00);
1011
1012         /* enable the appropriate bank */
1013         target_read_u32(target, 0xFFE8BC04, &fmmac2);
1014         target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1015
1016         /* TCR=0 */
1017         target_write_u32(target, 0xFFE8BC10, 0x2fc0);
1018
1019         /* clear TEZ in fmbrdy */
1020         target_write_u32(target, 0xFFE88010, 0x0b);
1021
1022         /* save current wait states, force max */
1023         target_read_u32(target, 0xFFE88004, &fmbac2);
1024         target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
1025
1026         /*
1027          * The TI primitives inspect the flash memory by reading one 32-bit
1028          * word at a time.  Here we read an entire sector and inspect it in
1029          * an attempt to reduce the JTAG overhead.
1030          */
1031         for (sector = 0; sector < bank->num_sectors; sector++)
1032         {
1033                 if (bank->sectors[sector].is_erased != 1)
1034                 {
1035                         u32 i, addr = bank->base + bank->sectors[sector].offset;
1036
1037                         INFO("checking flash bank %d sector %d", tms470_info->ordinal, sector);
1038
1039                         target_read_buffer(target, addr, bank->sectors[sector].size, buffer);
1040
1041                         bank->sectors[sector].is_erased = 1;
1042                         for (i = 0; i < bank->sectors[sector].size; i++)
1043                         {
1044                                 if (buffer[i] != 0xff)
1045                                 {
1046                                         WARNING("tms470 bank %d, sector %d, not erased.", tms470_info->ordinal, sector);
1047                                         WARNING("at location 0x%08x: flash data is 0x%02x.", addr + i, buffer[i]);
1048
1049                                         bank->sectors[sector].is_erased = 0;
1050                                         break;
1051                                 }
1052                         }
1053                 }
1054                 if (bank->sectors[sector].is_erased != 1)
1055                 {
1056                         result = ERROR_FLASH_SECTOR_NOT_ERASED;
1057                         break;
1058                 }
1059                 else
1060                 {
1061                         INFO("sector erased");
1062                 }
1063         }
1064
1065         /* reset TEZ, wait states, read mode, GLBCTRL.4 */
1066         target_write_u32(target, 0xFFE88010, 0x0f);
1067         target_write_u32(target, 0xFFE88004, fmbac2);
1068         target_write_u32(target, 0xFFE89C00, orig_fmregopt);
1069         target_write_u32(target, 0xFFFFFFDC, glbctrl);
1070
1071         return result;
1072 }
1073
1074 /* ---------------------------------------------------------------------- */
1075
1076 int tms470_protect_check(struct flash_bank_s *bank)
1077 {
1078         target_t *target = bank->target;
1079         tms470_flash_bank_t *tms470_info = bank->driver_priv;
1080         int sector, result = ERROR_OK;
1081         u32 fmmac2, fmbsea, fmbseb;
1082
1083         if (target->state != TARGET_HALTED)
1084         {
1085                 return ERROR_TARGET_NOT_HALTED;
1086         }
1087
1088         if (!tms470_info->device_ident_reg)
1089         {
1090                 tms470_read_part_info(bank);
1091         }
1092
1093         /* enable the appropriate bank */
1094         target_read_u32(target, 0xFFE8BC04, &fmmac2);
1095         target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1096
1097         target_read_u32(target, 0xFFE88008, &fmbsea);
1098         target_read_u32(target, 0xFFE8800C, &fmbseb);
1099
1100         for (sector = 0; sector < bank->num_sectors; sector++)
1101         {
1102                 int protected;
1103
1104                 if (sector < 16)
1105                 {
1106                         protected = fmbsea & (1 << sector) ? 0 : 1;
1107                         bank->sectors[sector].is_protected = protected;
1108                 }
1109                 else
1110                 {
1111                         protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
1112                         bank->sectors[sector].is_protected = protected;
1113                 }
1114
1115                 DEBUG("bank %d sector %d is %s", tms470_info->ordinal, sector, protected ? "protected" : "not protected");
1116         }
1117
1118         return result;
1119 }
1120
1121 /* ---------------------------------------------------------------------- */
1122
1123 int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size)
1124 {
1125         int used = 0;
1126         tms470_flash_bank_t *tms470_info = bank->driver_priv;
1127
1128         if (!tms470_info->device_ident_reg)
1129         {
1130                 tms470_read_part_info(bank);
1131         }
1132
1133         if (!tms470_info->device_ident_reg)
1134         {
1135                 (void)snprintf(buf, buf_size, "Cannot identify target as a TMS470\n");
1136                 return ERROR_FLASH_OPERATION_FAILED;
1137         }
1138
1139         used += snprintf(buf, buf_size, "\ntms470 information: Chip is %s\n", tms470_info->part_name);
1140         buf += used;
1141         buf_size -= used;
1142
1143         used += snprintf(buf, buf_size, "Flash protection level 2 is %s\n", tms470_check_flash_unlocked(bank->target) == ERROR_OK ? "disabled" : "enabled");
1144         buf += used;
1145         buf_size -= used;
1146
1147         return ERROR_OK;
1148 }
1149
1150 /* ---------------------------------------------------------------------- */
1151
1152 /*
1153  * flash bank tms470 <base> <size> <chip_width> <bus_width> <target>
1154  * [options...]
1155  */
1156
1157 int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
1158 {
1159         bank->driver_priv = malloc(sizeof(tms470_flash_bank_t));
1160
1161         if (!bank->driver_priv)
1162         {
1163                 return ERROR_FLASH_OPERATION_FAILED;
1164         }
1165
1166         (void)memset(bank->driver_priv, 0, sizeof(tms470_flash_bank_t));
1167
1168         return ERROR_OK;
1169 }