1 /***************************************************************************
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2 * Copyright (C) 2005 by Dominic Rath *
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3 * Dominic.Rath@gmx.de *
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5 * This program is free software; you can redistribute it and/or modify *
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6 * it under the terms of the GNU General Public License as published by *
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7 * the Free Software Foundation; either version 2 of the License, or *
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8 * (at your option) any later version. *
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10 * This program is distributed in the hope that it will be useful, *
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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13 * GNU General Public License for more details. *
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15 * You should have received a copy of the GNU General Public License *
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16 * along with this program; if not, write to the *
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17 * Free Software Foundation, Inc., *
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18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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19 ***************************************************************************/
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20 #ifdef HAVE_CONFIG_H
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24 #include "replacements.h"
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30 #include "armv4_5.h"
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31 #include "algorithm.h"
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32 #include "binarybuffer.h"
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38 str7x_mem_layout_t mem_layout[] = {
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39 {0x00000000, 0x02000, 0x01},
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40 {0x00002000, 0x02000, 0x02},
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41 {0x00004000, 0x02000, 0x04},
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42 {0x00006000, 0x02000, 0x08},
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43 {0x00008000, 0x08000, 0x10},
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44 {0x00010000, 0x10000, 0x20},
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45 {0x00020000, 0x10000, 0x40},
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46 {0x00030000, 0x10000, 0x80},
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47 {0x000C0000, 0x02000, 0x10000},
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48 {0x000C2000, 0x02000, 0x20000},
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51 int str7x_register_commands(struct command_context_s *cmd_ctx);
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52 int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
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53 int str7x_erase(struct flash_bank_s *bank, int first, int last);
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54 int str7x_protect(struct flash_bank_s *bank, int set, int first, int last);
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55 int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
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56 int str7x_probe(struct flash_bank_s *bank);
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57 int str7x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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58 int str7x_protect_check(struct flash_bank_s *bank);
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59 int str7x_erase_check(struct flash_bank_s *bank);
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60 int str7x_info(struct flash_bank_s *bank, char *buf, int buf_size);
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62 int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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64 flash_driver_t str7x_flash =
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67 .register_commands = str7x_register_commands,
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68 .flash_bank_command = str7x_flash_bank_command,
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69 .erase = str7x_erase,
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70 .protect = str7x_protect,
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71 .write = str7x_write,
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72 .probe = str7x_probe,
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73 .auto_probe = str7x_probe,
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74 .erase_check = str7x_erase_check,
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75 .protect_check = str7x_protect_check,
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79 int str7x_register_commands(struct command_context_s *cmd_ctx)
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81 command_t *str7x_cmd = register_command(cmd_ctx, NULL, "str7x", NULL, COMMAND_ANY, NULL);
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83 register_command(cmd_ctx, str7x_cmd, "disable_jtag", str7x_handle_disable_jtag_command, COMMAND_EXEC,
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84 "disable jtag access");
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89 int str7x_get_flash_adr(struct flash_bank_s *bank, u32 reg)
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91 return (bank->base | reg);
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94 int str7x_build_block_list(struct flash_bank_s *bank)
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96 str7x_flash_bank_t *str7x_info = bank->driver_priv;
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99 int num_sectors = 0, b0_sectors = 0, b1_sectors = 0;
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101 switch (bank->size)
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116 ERROR("BUG: unknown bank->size encountered");
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120 if( str7x_info->bank1 == 1 )
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125 num_sectors = b0_sectors + b1_sectors;
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127 bank->num_sectors = num_sectors;
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128 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
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129 str7x_info->sector_bits = malloc(sizeof(u32) * num_sectors);
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130 str7x_info->sector_bank = malloc(sizeof(u32) * num_sectors);
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134 for (i = 0; i < b0_sectors; i++)
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136 bank->sectors[num_sectors].offset = mem_layout[i].sector_start;
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137 bank->sectors[num_sectors].size = mem_layout[i].sector_size;
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138 bank->sectors[num_sectors].is_erased = -1;
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139 bank->sectors[num_sectors].is_protected = 1;
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140 str7x_info->sector_bank[num_sectors] = 0;
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141 str7x_info->sector_bits[num_sectors++] = mem_layout[i].sector_bit;
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146 for (i = 8; i < 10; i++)
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148 bank->sectors[num_sectors].offset = mem_layout[i].sector_start;
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149 bank->sectors[num_sectors].size = mem_layout[i].sector_size;
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150 bank->sectors[num_sectors].is_erased = -1;
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151 bank->sectors[num_sectors].is_protected = 1;
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152 str7x_info->sector_bank[num_sectors] = 1;
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153 str7x_info->sector_bits[num_sectors++] = mem_layout[i].sector_bit;
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160 /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
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162 int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
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164 str7x_flash_bank_t *str7x_info;
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168 WARNING("incomplete flash_bank str7x configuration");
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169 return ERROR_FLASH_BANK_INVALID;
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172 str7x_info = malloc(sizeof(str7x_flash_bank_t));
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173 bank->driver_priv = str7x_info;
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175 /* set default bits for str71x flash */
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176 str7x_info->bank1 = 1;
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177 str7x_info->busy_bits = (FLASH_LOCK|FLASH_BSYA1|FLASH_BSYA0);
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178 str7x_info->disable_bit = (1<<1);
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180 if (strcmp(args[6], "STR71x") == 0)
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182 if (bank->base != 0x40000000)
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184 WARNING("overriding flash base address for STR71x device with 0x40000000");
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185 bank->base = 0x40000000;
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188 else if (strcmp(args[6], "STR73x") == 0)
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190 str7x_info->bank1 = 0;
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191 str7x_info->busy_bits = (FLASH_LOCK|FLASH_BSYA0);
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193 if (bank->base != 0x80000000)
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195 WARNING("overriding flash base address for STR73x device with 0x80000000");
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196 bank->base = 0x80000000;
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199 else if (strcmp(args[6], "STR75x") == 0)
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201 str7x_info->disable_bit = (1<<0);
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203 if (bank->base != 0x20000000)
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205 WARNING("overriding flash base address for STR75x device with 0x20000000");
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206 bank->base = 0x20000000;
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211 ERROR("unknown STR7x variant: '%s'", args[6]);
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213 return ERROR_FLASH_BANK_INVALID;
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216 str7x_build_block_list(bank);
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218 str7x_info->write_algorithm = NULL;
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223 u32 str7x_status(struct flash_bank_s *bank)
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225 target_t *target = bank->target;
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228 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
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233 u32 str7x_result(struct flash_bank_s *bank)
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235 target_t *target = bank->target;
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238 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &retval);
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243 int str7x_blank_check(struct flash_bank_s *bank, int first, int last)
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245 target_t *target = bank->target;
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250 if ((first < 0) || (last > bank->num_sectors))
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251 return ERROR_FLASH_SECTOR_INVALID;
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253 if (bank->target->state != TARGET_HALTED)
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255 return ERROR_TARGET_NOT_HALTED;
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258 buffer = malloc(256);
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260 for (i = first; i <= last; i++)
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262 bank->sectors[i].is_erased = 1;
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264 target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
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266 for (nBytes = 0; nBytes < 256; nBytes++)
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268 if (buffer[nBytes] != 0xFF)
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270 bank->sectors[i].is_erased = 0;
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281 int str7x_protect_check(struct flash_bank_s *bank)
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283 str7x_flash_bank_t *str7x_info = bank->driver_priv;
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284 target_t *target = bank->target;
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289 if (bank->target->state != TARGET_HALTED)
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291 return ERROR_TARGET_NOT_HALTED;
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294 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &retval);
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296 for (i = 0; i < bank->num_sectors; i++)
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298 if (retval & str7x_info->sector_bits[i])
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299 bank->sectors[i].is_protected = 0;
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301 bank->sectors[i].is_protected = 1;
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307 int str7x_erase(struct flash_bank_s *bank, int first, int last)
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309 str7x_flash_bank_t *str7x_info = bank->driver_priv;
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310 target_t *target = bank->target;
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315 u32 b0_sectors = 0, b1_sectors = 0;
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317 for (i = first; i <= last; i++)
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319 if (str7x_info->sector_bank[i] == 0)
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320 b0_sectors |= str7x_info->sector_bits[i];
\r
321 else if (str7x_info->sector_bank[i] == 1)
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322 b1_sectors |= str7x_info->sector_bits[i];
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324 ERROR("BUG: str7x_info->sector_bank[i] neither 0 nor 1 (%i)", str7x_info->sector_bank[i]);
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329 DEBUG("b0_sectors: 0x%x", b0_sectors);
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331 /* clear FLASH_ER register */
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332 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
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335 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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338 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
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340 cmd = FLASH_SER|FLASH_WMS;
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341 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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343 while (((retval = str7x_status(bank)) & str7x_info->busy_bits)){
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347 retval = str7x_result(bank);
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351 ERROR("error erasing flash bank, FLASH_ER: 0x%x", retval);
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352 return ERROR_FLASH_OPERATION_FAILED;
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358 DEBUG("b1_sectors: 0x%x", b1_sectors);
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360 /* clear FLASH_ER register */
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361 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
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364 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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367 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
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369 cmd = FLASH_SER|FLASH_WMS;
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370 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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372 while (((retval = str7x_status(bank)) & str7x_info->busy_bits)){
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376 retval = str7x_result(bank);
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380 ERROR("error erasing flash bank, FLASH_ER: 0x%x", retval);
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381 return ERROR_FLASH_OPERATION_FAILED;
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385 for (i = first; i <= last; i++)
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386 bank->sectors[i].is_erased = 1;
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391 int str7x_protect(struct flash_bank_s *bank, int set, int first, int last)
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393 str7x_flash_bank_t *str7x_info = bank->driver_priv;
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394 target_t *target = bank->target;
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398 u32 protect_blocks;
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400 if (bank->target->state != TARGET_HALTED)
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402 return ERROR_TARGET_NOT_HALTED;
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405 protect_blocks = 0xFFFFFFFF;
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409 for (i = first; i <= last; i++)
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410 protect_blocks &= ~(str7x_info->sector_bits[i]);
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413 /* clear FLASH_ER register */
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414 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
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417 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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419 cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
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420 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
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422 cmd = protect_blocks;
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423 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
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425 cmd = FLASH_SPR|FLASH_WMS;
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426 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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428 while (((retval = str7x_status(bank)) & str7x_info->busy_bits)){
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432 retval = str7x_result(bank);
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434 DEBUG("retval: 0x%8.8x", retval);
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436 if (retval & FLASH_ERER)
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437 return ERROR_FLASH_SECTOR_NOT_ERASED;
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438 else if (retval & FLASH_WPF)
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439 return ERROR_FLASH_OPERATION_FAILED;
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444 int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
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446 str7x_flash_bank_t *str7x_info = bank->driver_priv;
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447 target_t *target = bank->target;
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448 u32 buffer_size = 8192;
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449 working_area_t *source;
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450 u32 address = bank->base + offset;
\r
451 reg_param_t reg_params[6];
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452 armv4_5_algorithm_t armv4_5_info;
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453 int retval = ERROR_OK;
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455 u32 str7x_flash_write_code[] = {
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457 0xe3a04201, /* mov r4, #0x10000000 */
\r
458 0xe5824000, /* str r4, [r2, #0x0] */
\r
459 0xe5821010, /* str r1, [r2, #0x10] */
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460 0xe4904004, /* ldr r4, [r0], #4 */
\r
461 0xe5824008, /* str r4, [r2, #0x8] */
\r
462 0xe4904004, /* ldr r4, [r0], #4 */
\r
463 0xe582400c, /* str r4, [r2, #0xc] */
\r
464 0xe3a04209, /* mov r4, #0x90000000 */
\r
465 0xe5824000, /* str r4, [r2, #0x0] */
\r
467 0xe5924000, /* ldr r4, [r2, #0x0] */
\r
468 0xe1140005, /* tst r4, r5 */
\r
469 0x1afffffc, /* bne busy */
\r
470 0xe5924014, /* ldr r4, [r2, #0x14] */
\r
471 0xe31400ff, /* tst r4, #0xff */
\r
472 0x03140c01, /* tsteq r4, #0x100 */
\r
473 0x1a000002, /* bne exit */
\r
474 0xe2811008, /* add r1, r1, #0x8 */
\r
475 0xe2533001, /* subs r3, r3, #1 */
\r
476 0x1affffec, /* bne write */
\r
478 0xeafffffe, /* b exit */
\r
481 /* flash write code */
\r
482 if (target_alloc_working_area(target, 4 * 20, &str7x_info->write_algorithm) != ERROR_OK)
\r
484 WARNING("no working area available, can't do block memory writes");
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485 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
\r
488 target_write_buffer(target, str7x_info->write_algorithm->address, 20 * 4, (u8*)str7x_flash_write_code);
\r
490 /* memory buffer */
\r
491 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
\r
494 if (buffer_size <= 256)
\r
496 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
\r
497 if (str7x_info->write_algorithm)
\r
498 target_free_working_area(target, str7x_info->write_algorithm);
\r
500 WARNING("no large enough working area available, can't do block memory writes");
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501 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
\r
505 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
\r
506 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
\r
507 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
\r
509 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
\r
510 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
\r
511 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
\r
512 init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
\r
513 init_reg_param(®_params[4], "r4", 32, PARAM_IN);
\r
514 init_reg_param(®_params[5], "r5", 32, PARAM_OUT);
\r
518 u32 thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
\r
520 target_write_buffer(target, source->address, thisrun_count * 8, buffer);
\r
522 buf_set_u32(reg_params[0].value, 0, 32, source->address);
\r
523 buf_set_u32(reg_params[1].value, 0, 32, address);
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524 buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
\r
525 buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
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526 buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
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528 if ((retval = target->type->run_algorithm(target, 0, NULL, 6, reg_params, str7x_info->write_algorithm->address, str7x_info->write_algorithm->address + (19 * 4), 10000, &armv4_5_info)) != ERROR_OK)
\r
530 ERROR("error executing str7x flash write algorithm");
\r
534 if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
\r
536 retval = ERROR_FLASH_OPERATION_FAILED;
\r
540 buffer += thisrun_count * 8;
\r
541 address += thisrun_count * 8;
\r
542 count -= thisrun_count;
\r
545 target_free_working_area(target, source);
\r
546 target_free_working_area(target, str7x_info->write_algorithm);
\r
548 destroy_reg_param(®_params[0]);
\r
549 destroy_reg_param(®_params[1]);
\r
550 destroy_reg_param(®_params[2]);
\r
551 destroy_reg_param(®_params[3]);
\r
552 destroy_reg_param(®_params[4]);
\r
553 destroy_reg_param(®_params[5]);
\r
558 int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
\r
560 target_t *target = bank->target;
\r
561 str7x_flash_bank_t *str7x_info = bank->driver_priv;
\r
562 u32 dwords_remaining = (count / 8);
\r
563 u32 bytes_remaining = (count & 0x00000007);
\r
564 u32 address = bank->base + offset;
\r
565 u32 bytes_written = 0;
\r
568 u32 check_address = offset;
\r
573 WARNING("offset 0x%x breaks required 8-byte alignment", offset);
\r
574 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
\r
577 for (i = 0; i < bank->num_sectors; i++)
\r
579 u32 sec_start = bank->sectors[i].offset;
\r
580 u32 sec_end = sec_start + bank->sectors[i].size;
\r
582 /* check if destination falls within the current sector */
\r
583 if ((check_address >= sec_start) && (check_address < sec_end))
\r
585 /* check if destination ends in the current sector */
\r
586 if (offset + count < sec_end)
\r
587 check_address = offset + count;
\r
589 check_address = sec_end;
\r
593 if (check_address != offset + count)
\r
594 return ERROR_FLASH_DST_OUT_OF_BANK;
\r
596 /* clear FLASH_ER register */
\r
597 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
\r
599 /* multiple dwords (8-byte) to be programmed? */
\r
600 if (dwords_remaining > 0)
\r
602 /* try using a block write */
\r
603 if ((retval = str7x_write_block(bank, buffer, offset, dwords_remaining)) != ERROR_OK)
\r
605 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
\r
607 /* if block write failed (no sufficient working area),
\r
608 * we use normal (slow) single dword accesses */
\r
609 WARNING("couldn't use block writes, falling back to single memory accesses");
\r
611 else if (retval == ERROR_FLASH_OPERATION_FAILED)
\r
613 /* if an error occured, we examine the reason, and quit */
\r
614 retval = str7x_result(bank);
\r
616 ERROR("flash writing failed with error code: 0x%x", retval);
\r
617 return ERROR_FLASH_OPERATION_FAILED;
\r
622 buffer += dwords_remaining * 8;
\r
623 address += dwords_remaining * 8;
\r
624 dwords_remaining = 0;
\r
628 while (dwords_remaining > 0)
\r
632 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
\r
635 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
\r
638 target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, buffer + bytes_written);
\r
639 bytes_written += 4;
\r
642 target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, buffer + bytes_written);
\r
643 bytes_written += 4;
\r
645 /* start programming cycle */
\r
646 cmd = FLASH_DWPG | FLASH_WMS;
\r
647 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
\r
649 while (((retval = str7x_status(bank)) & str7x_info->busy_bits))
\r
654 retval = str7x_result(bank);
\r
656 if (retval & FLASH_PGER)
\r
657 return ERROR_FLASH_OPERATION_FAILED;
\r
658 else if (retval & FLASH_WPF)
\r
659 return ERROR_FLASH_OPERATION_FAILED;
\r
661 dwords_remaining--;
\r
665 if (bytes_remaining)
\r
667 u8 last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
\r
670 while(bytes_remaining > 0)
\r
672 last_dword[i++] = *(buffer + bytes_written);
\r
679 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
\r
682 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
\r
685 target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, last_dword);
\r
686 bytes_written += 4;
\r
689 target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, last_dword + 4);
\r
690 bytes_written += 4;
\r
692 /* start programming cycle */
\r
693 cmd = FLASH_DWPG | FLASH_WMS;
\r
694 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
\r
696 while (((retval = str7x_status(bank)) & str7x_info->busy_bits))
\r
701 retval = str7x_result(bank);
\r
703 if (retval & FLASH_PGER)
\r
704 return ERROR_FLASH_OPERATION_FAILED;
\r
705 else if (retval & FLASH_WPF)
\r
706 return ERROR_FLASH_OPERATION_FAILED;
\r
712 int str7x_probe(struct flash_bank_s *bank)
\r
717 int str7x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
722 int str7x_erase_check(struct flash_bank_s *bank)
\r
724 return str7x_blank_check(bank, 0, bank->num_sectors - 1);
\r
727 int str7x_info(struct flash_bank_s *bank, char *buf, int buf_size)
\r
729 snprintf(buf, buf_size, "str7x flash driver info" );
\r
733 int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
735 flash_bank_t *bank;
\r
736 target_t *target = NULL;
\r
737 str7x_flash_bank_t *str7x_info = NULL;
\r
741 u16 ProtectionLevel = 0;
\r
742 u16 ProtectionRegs;
\r
746 command_print(cmd_ctx, "str7x disable_jtag <bank>");
\r
750 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
\r
753 command_print(cmd_ctx, "str7x disable_jtag <bank> ok");
\r
757 str7x_info = bank->driver_priv;
\r
759 target = bank->target;
\r
761 if (target->state != TARGET_HALTED)
\r
763 return ERROR_TARGET_NOT_HALTED;
\r
766 /* first we get protection status */
\r
767 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &retval);
\r
769 if (!(retval & str7x_info->disable_bit))
\r
771 ProtectionLevel = 1;
\r
774 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &retval);
\r
775 ProtectionRegs = ~(retval >> 16);
\r
777 while (((ProtectionRegs) != 0) && (ProtectionLevel < 16))
\r
779 ProtectionRegs >>= 1;
\r
783 if (ProtectionLevel == 0)
\r
785 flash_cmd = FLASH_SPR;
\r
786 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
\r
787 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
\r
788 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), 0xFFFFFFFD);
\r
789 flash_cmd = FLASH_SPR | FLASH_WMS;
\r
790 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
\r
794 flash_cmd = FLASH_SPR;
\r
795 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
\r
796 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
\r
797 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), ~(1<<(15+ProtectionLevel)));
\r
798 flash_cmd = FLASH_SPR | FLASH_WMS;
\r
799 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
\r