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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "stm32x.h"
  27 #include "flash.h"
  28 #include "target.h"
  29 #include "log.h"
  30 #include "armv7m.h"
  31 #include "algorithm.h"
  32 #include "binarybuffer.h"
  33
  34 #include <stdlib.h>
  35 #include <string.h>
  36
  37 int stm32x_register_commands(struct command_context_s *cmd_ctx);
  38 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  39 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
  40 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
  41 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  42 int stm32x_probe(struct flash_bank_s *bank);
  43 int stm32x_auto_probe(struct flash_bank_s *bank);
  44 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  45 int stm32x_protect_check(struct flash_bank_s *bank);
  46 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
  47
  48 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  49 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  50 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  51 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53
  54 flash_driver_t stm32x_flash =
  55 {
  56         .name = "stm32x",
  57         .register_commands = stm32x_register_commands,
  58         .flash_bank_command = stm32x_flash_bank_command,
  59         .erase = stm32x_erase,
  60         .protect = stm32x_protect,
  61         .write = stm32x_write,
  62         .probe = stm32x_probe,
  63         .auto_probe = stm32x_auto_probe,
  64         .erase_check = default_flash_mem_blank_check,
  65         .protect_check = stm32x_protect_check,
  66         .info = stm32x_info
  67 };
  68
  69 int stm32x_register_commands(struct command_context_s *cmd_ctx)
  70 {
  71         command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
  72
  73         register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
  74                                          "lock device");
  75         register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
  76                                          "unlock protected device");
  77         register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
  78                                          "mass erase device");
  79         register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
  80                                          "read device option bytes");
  81         register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
  82                                          "write device option bytes");
  83         return ERROR_OK;
  84 }
  85
  86 /* flash bank stm32x <base> <size> 0 0 <target#>
  87  */
  88 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
  89 {
  90         stm32x_flash_bank_t *stm32x_info;
  91
  92         if (argc < 6)
  93         {
  94                 LOG_WARNING("incomplete flash_bank stm32x configuration");
  95                 return ERROR_FLASH_BANK_INVALID;
  96         }
  97
  98         stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
  99         bank->driver_priv = stm32x_info;
 100
 101         stm32x_info->write_algorithm = NULL;
 102         stm32x_info->probed = 0;
 103
 104         return ERROR_OK;
 105 }
 106
 107 u32 stm32x_get_flash_status(flash_bank_t *bank)
 108 {
 109         target_t *target = bank->target;
 110         u32 status;
 111
 112         target_read_u32(target, STM32_FLASH_SR, &status);
 113
 114         return status;
 115 }
 116
 117 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
 118 {
 119         u32 status;
 120
 121         /* wait for busy to clear */
 122         while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
 123         {
 124                 LOG_DEBUG("status: 0x%x", status);
 125                 usleep(1000);
 126         }
 127
 128         return status;
 129 }
 130
 131 int stm32x_read_options(struct flash_bank_s *bank)
 132 {
 133         u32 optiondata;
 134         stm32x_flash_bank_t *stm32x_info = NULL;
 135         target_t *target = bank->target;
 136
 137         stm32x_info = bank->driver_priv;
 138
 139         /* read current option bytes */
 140         target_read_u32(target, STM32_FLASH_OBR, &optiondata);
 141
 142         stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
 143         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 144
 145         if (optiondata & (1 << OPT_READOUT))
 146                 LOG_INFO("Device Security Bit Set");
 147
 148         /* each bit refers to a 4bank protection */
 149         target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
 150
 151         stm32x_info->option_bytes.protection[0] = (u16)optiondata;
 152         stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
 153         stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
 154         stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
 155
 156         return ERROR_OK;
 157 }
 158
 159 int stm32x_erase_options(struct flash_bank_s *bank)
 160 {
 161         stm32x_flash_bank_t *stm32x_info = NULL;
 162         target_t *target = bank->target;
 163         u32 status;
 164
 165         stm32x_info = bank->driver_priv;
 166
 167         /* read current options */
 168         stm32x_read_options(bank);
 169
 170         /* unlock flash registers */
 171         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 172         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 173
 174         /* unlock option flash registers */
 175         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 176         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 177
 178         /* erase option bytes */
 179         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
 180         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
 181
 182         status = stm32x_wait_status_busy(bank, 10);
 183
 184         if( status & FLASH_WRPRTERR )
 185                 return ERROR_FLASH_OPERATION_FAILED;
 186         if( status & FLASH_PGERR )
 187                 return ERROR_FLASH_OPERATION_FAILED;
 188
 189         /* clear readout protection and complementary option bytes
 190          * this will also force a device unlock if set */
 191         stm32x_info->option_bytes.RDP = 0x5AA5;
 192
 193         return ERROR_OK;
 194 }
 195
 196 int stm32x_write_options(struct flash_bank_s *bank)
 197 {
 198         stm32x_flash_bank_t *stm32x_info = NULL;
 199         target_t *target = bank->target;
 200         u32 status;
 201
 202         stm32x_info = bank->driver_priv;
 203
 204         /* unlock flash registers */
 205         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 206         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 207
 208         /* unlock option flash registers */
 209         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 210         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 211
 212         /* program option bytes */
 213         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
 214
 215         /* write user option byte */
 216         target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
 217
 218         status = stm32x_wait_status_busy(bank, 10);
 219
 220         if( status & FLASH_WRPRTERR )
 221                 return ERROR_FLASH_OPERATION_FAILED;
 222         if( status & FLASH_PGERR )
 223                 return ERROR_FLASH_OPERATION_FAILED;
 224
 225         /* write protection byte 1 */
 226         target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
 227
 228         status = stm32x_wait_status_busy(bank, 10);
 229
 230         if( status & FLASH_WRPRTERR )
 231                 return ERROR_FLASH_OPERATION_FAILED;
 232         if( status & FLASH_PGERR )
 233                 return ERROR_FLASH_OPERATION_FAILED;
 234
 235         /* write protection byte 2 */
 236         target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
 237
 238         status = stm32x_wait_status_busy(bank, 10);
 239
 240         if( status & FLASH_WRPRTERR )
 241                 return ERROR_FLASH_OPERATION_FAILED;
 242         if( status & FLASH_PGERR )
 243                 return ERROR_FLASH_OPERATION_FAILED;
 244
 245         /* write protection byte 3 */
 246         target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
 247
 248         status = stm32x_wait_status_busy(bank, 10);
 249
 250         if( status & FLASH_WRPRTERR )
 251                 return ERROR_FLASH_OPERATION_FAILED;
 252         if( status & FLASH_PGERR )
 253                 return ERROR_FLASH_OPERATION_FAILED;
 254
 255         /* write protection byte 4 */
 256         target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
 257
 258         status = stm32x_wait_status_busy(bank, 10);
 259
 260         if( status & FLASH_WRPRTERR )
 261                 return ERROR_FLASH_OPERATION_FAILED;
 262         if( status & FLASH_PGERR )
 263                 return ERROR_FLASH_OPERATION_FAILED;
 264
 265         /* write readout protection bit */
 266         target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
 267
 268         status = stm32x_wait_status_busy(bank, 10);
 269
 270         if( status & FLASH_WRPRTERR )
 271                 return ERROR_FLASH_OPERATION_FAILED;
 272         if( status & FLASH_PGERR )
 273                 return ERROR_FLASH_OPERATION_FAILED;
 274
 275         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 276
 277         return ERROR_OK;
 278 }
 279
 280 int stm32x_protect_check(struct flash_bank_s *bank)
 281 {
 282         target_t *target = bank->target;
 283         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 284
 285         u32 protection;
 286         int i, s;
 287         int num_bits;
 288
 289         if (target->state != TARGET_HALTED)
 290         {
 291                 return ERROR_TARGET_NOT_HALTED;
 292         }
 293
 294         /* medium density - each bit refers to a 4bank protection
 295          * high density - each bit refers to a 2bank protection */
 296         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 297
 298         /* medium density - each protection bit is for 4 * 1K pages
 299          * high density - each protection bit is for 2 * 2K pages */
 300         num_bits = (bank->num_sectors / stm32x_info->ppage_size);
 301
 302         for (i = 0; i < num_bits; i++)
 303         {
 304                 int set = 1;
 305
 306                 if( protection & (1 << i))
 307                         set = 0;
 308
 309                 for (s = 0; s < stm32x_info->ppage_size; s++)
 310                         bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 311         }
 312
 313         return ERROR_OK;
 314 }
 315
 316 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
 317 {
 318         target_t *target = bank->target;
 319
 320         int i;
 321         u32 status;
 322
 323         if (bank->target->state != TARGET_HALTED)
 324         {
 325                 return ERROR_TARGET_NOT_HALTED;
 326         }
 327
 328         /* unlock flash registers */
 329         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 330         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 331
 332         for (i = first; i <= last; i++)
 333         {
 334                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
 335                 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
 336                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
 337
 338                 status = stm32x_wait_status_busy(bank, 10);
 339
 340                 if( status & FLASH_WRPRTERR )
 341                         return ERROR_FLASH_OPERATION_FAILED;
 342                 if( status & FLASH_PGERR )
 343                         return ERROR_FLASH_OPERATION_FAILED;
 344                 bank->sectors[i].is_erased = 1;
 345         }
 346
 347         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 348
 349         return ERROR_OK;
 350 }
 351
 352 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
 353 {
 354         stm32x_flash_bank_t *stm32x_info = NULL;
 355         target_t *target = bank->target;
 356         u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 357         int i, reg, bit;
 358         int status;
 359         u32 protection;
 360
 361         stm32x_info = bank->driver_priv;
 362
 363         if (target->state != TARGET_HALTED)
 364         {
 365                 return ERROR_TARGET_NOT_HALTED;
 366         }
 367
 368         if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
 369         {
 370                 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", stm32x_info->ppage_size);
 371                 return ERROR_FLASH_SECTOR_INVALID;
 372         }
 373
 374         /* medium density - each bit refers to a 4bank protection
 375          * high density - each bit refers to a 2bank protection */
 376         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 377
 378         prot_reg[0] = (u16)protection;
 379         prot_reg[1] = (u16)(protection >> 8);
 380         prot_reg[2] = (u16)(protection >> 16);
 381         prot_reg[3] = (u16)(protection >> 24);
 382
 383         for (i = first; i <= last; i++)
 384         {
 385                 reg = (i / stm32x_info->ppage_size) / 8;
 386                 bit = (i / stm32x_info->ppage_size) - (reg * 8);
 387
 388                 if( set )
 389                         prot_reg[reg] &= ~(1 << bit);
 390                 else
 391                         prot_reg[reg] |= (1 << bit);
 392         }
 393
 394         if ((status = stm32x_erase_options(bank)) != ERROR_OK)
 395                 return status;
 396
 397         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 398         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 399         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 400         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 401
 402         return stm32x_write_options(bank);
 403 }
 404
 405 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 406 {
 407         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 408         target_t *target = bank->target;
 409         u32 buffer_size = 8192;
 410         working_area_t *source;
 411         u32 address = bank->base + offset;
 412         reg_param_t reg_params[4];
 413         armv7m_algorithm_t armv7m_info;
 414         int retval = ERROR_OK;
 415
 416         u8 stm32x_flash_write_code[] = {
 417                                                                         /* write: */
 418                 0xDF, 0xF8, 0x24, 0x40,         /* ldr  r4, STM32_FLASH_CR */
 419                 0x09, 0x4D,                                     /* ldr  r5, STM32_FLASH_SR */
 420                 0x4F, 0xF0, 0x01, 0x03,         /* mov  r3, #1 */
 421                 0x23, 0x60,                                     /* str  r3, [r4, #0] */
 422                 0x30, 0xF8, 0x02, 0x3B,         /* ldrh r3, [r0], #2 */
 423                 0x21, 0xF8, 0x02, 0x3B,         /* strh r3, [r1], #2 */
 424                                                                         /* busy: */
 425                 0x2B, 0x68,                                     /* ldr  r3, [r5, #0] */
 426                 0x13, 0xF0, 0x01, 0x0F,         /* tst  r3, #0x01 */
 427                 0xFB, 0xD0,                                     /* beq  busy */
 428                 0x13, 0xF0, 0x14, 0x0F,         /* tst  r3, #0x14 */
 429                 0x01, 0xD1,                                     /* bne  exit */
 430                 0x01, 0x3A,                                     /* subs r2, r2, #1 */
 431                 0xED, 0xD1,                                     /* bne  write */
 432                                                                         /* exit: */
 433                 0xFE, 0xE7,                                     /* b exit */
 434                 0x10, 0x20, 0x02, 0x40,         /* STM32_FLASH_CR:      .word 0x40022010 */
 435                 0x0C, 0x20, 0x02, 0x40          /* STM32_FLASH_SR:      .word 0x4002200C */
 436         };
 437
 438         /* flash write code */
 439         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
 440         {
 441                 LOG_WARNING("no working area available, can't do block memory writes");
 442                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 443         };
 444
 445         if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code))!=ERROR_OK)
 446                 return retval;
 447
 448         /* memory buffer */
 449         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
 450         {
 451                 buffer_size /= 2;
 452                 if (buffer_size <= 256)
 453                 {
 454                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
 455                         if (stm32x_info->write_algorithm)
 456                                 target_free_working_area(target, stm32x_info->write_algorithm);
 457
 458                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 459                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 460                 }
 461         };
 462
 463         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 464         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 465
 466         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 467         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 468         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 469         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
 470
 471         while (count > 0)
 472         {
 473                 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
 474
 475                 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)
 476                         break;
 477
 478                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 479                 buf_set_u32(reg_params[1].value, 0, 32, address);
 480                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
 481
 482                 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
 483                                 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
 484                 {
 485                         LOG_ERROR("error executing stm32x flash write algorithm");
 486                         break;
 487                 }
 488
 489                 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
 490                 {
 491                         retval = ERROR_FLASH_OPERATION_FAILED;
 492                         break;
 493                 }
 494
 495                 buffer += thisrun_count * 2;
 496                 address += thisrun_count * 2;
 497                 count -= thisrun_count;
 498         }
 499
 500         target_free_working_area(target, source);
 501         target_free_working_area(target, stm32x_info->write_algorithm);
 502
 503         destroy_reg_param(&reg_params[0]);
 504         destroy_reg_param(&reg_params[1]);
 505         destroy_reg_param(&reg_params[2]);
 506         destroy_reg_param(&reg_params[3]);
 507
 508         return retval;
 509 }
 510
 511 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 512 {
 513         target_t *target = bank->target;
 514         u32 words_remaining = (count / 2);
 515         u32 bytes_remaining = (count & 0x00000001);
 516         u32 address = bank->base + offset;
 517         u32 bytes_written = 0;
 518         u8 status;
 519         u32 retval;
 520
 521         if (bank->target->state != TARGET_HALTED)
 522         {
 523                 return ERROR_TARGET_NOT_HALTED;
 524         }
 525
 526         if (offset & 0x1)
 527         {
 528                 LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset);
 529                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 530         }
 531
 532         /* unlock flash registers */
 533         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 534         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 535
 536         /* multiple half words (2-byte) to be programmed? */
 537         if (words_remaining > 0)
 538         {
 539                 /* try using a block write */
 540                 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
 541                 {
 542                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 543                         {
 544                                 /* if block write failed (no sufficient working area),
 545                                  * we use normal (slow) single dword accesses */
 546                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 547                         }
 548                         else if (retval == ERROR_FLASH_OPERATION_FAILED)
 549                         {
 550                                 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
 551                                 return ERROR_FLASH_OPERATION_FAILED;
 552                         }
 553                 }
 554                 else
 555                 {
 556                         buffer += words_remaining * 2;
 557                         address += words_remaining * 2;
 558                         words_remaining = 0;
 559                 }
 560         }
 561
 562         while (words_remaining > 0)
 563         {
 564                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 565                 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
 566
 567                 status = stm32x_wait_status_busy(bank, 5);
 568
 569                 if( status & FLASH_WRPRTERR )
 570                         return ERROR_FLASH_OPERATION_FAILED;
 571                 if( status & FLASH_PGERR )
 572                         return ERROR_FLASH_OPERATION_FAILED;
 573
 574                 bytes_written += 2;
 575                 words_remaining--;
 576                 address += 2;
 577         }
 578
 579         if (bytes_remaining)
 580         {
 581                 u8 last_halfword[2] = {0xff, 0xff};
 582                 int i = 0;
 583
 584                 while(bytes_remaining > 0)
 585                 {
 586                         last_halfword[i++] = *(buffer + bytes_written);
 587                         bytes_remaining--;
 588                         bytes_written++;
 589                 }
 590
 591                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 592                 target_write_u16(target, address, *(u16*)last_halfword);
 593
 594                 status = stm32x_wait_status_busy(bank, 5);
 595
 596                 if( status & FLASH_WRPRTERR )
 597                         return ERROR_FLASH_OPERATION_FAILED;
 598                 if( status & FLASH_PGERR )
 599                         return ERROR_FLASH_OPERATION_FAILED;
 600         }
 601
 602         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 603
 604         return ERROR_OK;
 605 }
 606
 607 int stm32x_probe(struct flash_bank_s *bank)
 608 {
 609         target_t *target = bank->target;
 610         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 611         int i;
 612         u16 num_pages;
 613         u32 device_id;
 614         int page_size;
 615
 616         if (bank->target->state != TARGET_HALTED)
 617         {
 618                 return ERROR_TARGET_NOT_HALTED;
 619         }
 620
 621         stm32x_info->probed = 0;
 622
 623         /* read stm32 device id register */
 624         target_read_u32(target, 0xE0042000, &device_id);
 625         LOG_INFO( "device id = 0x%08x", device_id );
 626
 627         switch (device_id & 0x7ff)
 628         {
 629                 case 0x410:
 630                         /* medium density - we have 1k pages
 631                          * 4 pages for a protection area */
 632                         page_size = 1024;
 633                         stm32x_info->ppage_size = 4;
 634                         break;
 635
 636                 case 0x414:
 637                         /* high density - we have 2k pages
 638                          * 2 pages for a protection area */
 639                         page_size = 2048;
 640                         stm32x_info->ppage_size = 2;
 641                         break;
 642
 643                 default:
 644                         LOG_WARNING( "Cannot identify target as a STM32 family." );
 645                         return ERROR_FLASH_OPERATION_FAILED;
 646         }
 647
 648         /* get flash size from target */
 649         if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
 650         {
 651                 /* failed reading flash size, default to 128k */
 652                 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 128k flash" );
 653                 num_pages = 128;
 654         }
 655
 656         /* check for early silicon rev A */
 657         if ((device_id >> 16) == 0 )
 658         {
 659                 /* number of sectors incorrect on revA */
 660                 LOG_WARNING( "STM32 Rev A Silicon detected, probe inaccurate - assuming 128k flash" );
 661                 num_pages = 128;
 662         }
 663
 664         LOG_INFO( "flash size = %dkbytes", num_pages );
 665
 666         /* calculate numbers of pages */
 667         if (page_size - 1024)
 668                 num_pages /= (page_size - 1024);
 669
 670         bank->base = 0x08000000;
 671         bank->size = (num_pages * page_size);
 672         bank->num_sectors = num_pages;
 673         bank->sectors = malloc(sizeof(flash_sector_t) * num_pages);
 674
 675         for (i = 0; i < num_pages; i++)
 676         {
 677                 bank->sectors[i].offset = i * page_size;
 678                 bank->sectors[i].size = page_size;
 679                 bank->sectors[i].is_erased = -1;
 680                 bank->sectors[i].is_protected = 1;
 681         }
 682
 683         stm32x_info->probed = 1;
 684
 685         return ERROR_OK;
 686 }
 687
 688 int stm32x_auto_probe(struct flash_bank_s *bank)
 689 {
 690         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 691         if (stm32x_info->probed)
 692                 return ERROR_OK;
 693         return stm32x_probe(bank);
 694 }
 695
 696 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 697 {
 698         return ERROR_OK;
 699 }
 700
 701 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
 702 {
 703         snprintf(buf, buf_size, "stm32x flash driver info" );
 704         return ERROR_OK;
 705 }
 706
 707 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 708 {
 709         flash_bank_t *bank;
 710         target_t *target = NULL;
 711         stm32x_flash_bank_t *stm32x_info = NULL;
 712
 713         if (argc < 1)
 714         {
 715                 command_print(cmd_ctx, "stm32x lock <bank>");
 716                 return ERROR_OK;
 717         }
 718
 719         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 720         if (!bank)
 721         {
 722                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 723                 return ERROR_OK;
 724         }
 725
 726         stm32x_info = bank->driver_priv;
 727
 728         target = bank->target;
 729
 730         if (target->state != TARGET_HALTED)
 731         {
 732                 return ERROR_TARGET_NOT_HALTED;
 733         }
 734
 735         if (stm32x_erase_options(bank) != ERROR_OK)
 736         {
 737                 command_print(cmd_ctx, "stm32x failed to erase options");
 738                 return ERROR_OK;
 739         }
 740
 741         /* set readout protection */
 742         stm32x_info->option_bytes.RDP = 0;
 743
 744         if (stm32x_write_options(bank) != ERROR_OK)
 745         {
 746                 command_print(cmd_ctx, "stm32x failed to lock device");
 747                 return ERROR_OK;
 748         }
 749
 750         command_print(cmd_ctx, "stm32x locked");
 751
 752         return ERROR_OK;
 753 }
 754
 755 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 756 {
 757         flash_bank_t *bank;
 758         target_t *target = NULL;
 759         stm32x_flash_bank_t *stm32x_info = NULL;
 760
 761         if (argc < 1)
 762         {
 763                 command_print(cmd_ctx, "stm32x unlock <bank>");
 764                 return ERROR_OK;
 765         }
 766
 767         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 768         if (!bank)
 769         {
 770                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 771                 return ERROR_OK;
 772         }
 773
 774         stm32x_info = bank->driver_priv;
 775
 776         target = bank->target;
 777
 778         if (target->state != TARGET_HALTED)
 779         {
 780                 return ERROR_TARGET_NOT_HALTED;
 781         }
 782
 783         if (stm32x_erase_options(bank) != ERROR_OK)
 784         {
 785                 command_print(cmd_ctx, "stm32x failed to unlock device");
 786                 return ERROR_OK;
 787         }
 788
 789         if (stm32x_write_options(bank) != ERROR_OK)
 790         {
 791                 command_print(cmd_ctx, "stm32x failed to lock device");
 792                 return ERROR_OK;
 793         }
 794
 795         command_print(cmd_ctx, "stm32x unlocked");
 796
 797         return ERROR_OK;
 798 }
 799
 800 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 801 {
 802         flash_bank_t *bank;
 803         u32 optionbyte;
 804         target_t *target = NULL;
 805         stm32x_flash_bank_t *stm32x_info = NULL;
 806
 807         if (argc < 1)
 808         {
 809                 command_print(cmd_ctx, "stm32x options_read <bank>");
 810                 return ERROR_OK;
 811         }
 812
 813         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 814         if (!bank)
 815         {
 816                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 817                 return ERROR_OK;
 818         }
 819
 820         stm32x_info = bank->driver_priv;
 821
 822         target = bank->target;
 823
 824         if (target->state != TARGET_HALTED)
 825         {
 826                 return ERROR_TARGET_NOT_HALTED;
 827         }
 828
 829         target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
 830         command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
 831
 832         if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
 833                 command_print(cmd_ctx, "Option Byte Complement Error");
 834
 835         if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
 836                 command_print(cmd_ctx, "Readout Protection On");
 837         else
 838                 command_print(cmd_ctx, "Readout Protection Off");
 839
 840         if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
 841                 command_print(cmd_ctx, "Software Watchdog");
 842         else
 843                 command_print(cmd_ctx, "Hardware Watchdog");
 844
 845         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
 846                 command_print(cmd_ctx, "Stop: No reset generated");
 847         else
 848                 command_print(cmd_ctx, "Stop: Reset generated");
 849
 850         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
 851                 command_print(cmd_ctx, "Standby: No reset generated");
 852         else
 853                 command_print(cmd_ctx, "Standby: Reset generated");
 854
 855         return ERROR_OK;
 856 }
 857
 858 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 859 {
 860         flash_bank_t *bank;
 861         target_t *target = NULL;
 862         stm32x_flash_bank_t *stm32x_info = NULL;
 863         u16 optionbyte = 0xF8;
 864
 865         if (argc < 4)
 866         {
 867                 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
 868                 return ERROR_OK;
 869         }
 870
 871         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 872         if (!bank)
 873         {
 874                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 875                 return ERROR_OK;
 876         }
 877
 878         stm32x_info = bank->driver_priv;
 879
 880         target = bank->target;
 881
 882         if (target->state != TARGET_HALTED)
 883         {
 884                 return ERROR_TARGET_NOT_HALTED;
 885         }
 886
 887         if (strcmp(args[1], "SWWDG") == 0)
 888         {
 889                 optionbyte |= (1<<0);
 890         }
 891         else
 892         {
 893                 optionbyte &= ~(1<<0);
 894         }
 895
 896         if (strcmp(args[2], "NORSTSTNDBY") == 0)
 897         {
 898                 optionbyte |= (1<<1);
 899         }
 900         else
 901         {
 902                 optionbyte &= ~(1<<1);
 903         }
 904
 905         if (strcmp(args[3], "NORSTSTOP") == 0)
 906         {
 907                 optionbyte |= (1<<2);
 908         }
 909         else
 910         {
 911                 optionbyte &= ~(1<<2);
 912         }
 913
 914         if (stm32x_erase_options(bank) != ERROR_OK)
 915         {
 916                 command_print(cmd_ctx, "stm32x failed to erase options");
 917                 return ERROR_OK;
 918         }
 919
 920         stm32x_info->option_bytes.user_options = optionbyte;
 921
 922         if (stm32x_write_options(bank) != ERROR_OK)
 923         {
 924                 command_print(cmd_ctx, "stm32x failed to write options");
 925                 return ERROR_OK;
 926         }
 927
 928         command_print(cmd_ctx, "stm32x write options complete");
 929
 930         return ERROR_OK;
 931 }
 932
 933 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 934 {
 935         target_t *target = NULL;
 936         stm32x_flash_bank_t *stm32x_info = NULL;
 937         flash_bank_t *bank;
 938         u32 status;
 939         int i;
 940
 941         if (argc < 1)
 942         {
 943                 command_print(cmd_ctx, "stm32x mass_erase <bank>");
 944                 return ERROR_OK;
 945         }
 946
 947         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 948         if (!bank)
 949         {
 950                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 951                 return ERROR_OK;
 952         }
 953
 954         stm32x_info = bank->driver_priv;
 955
 956         target = bank->target;
 957
 958         if (target->state != TARGET_HALTED)
 959         {
 960                 return ERROR_TARGET_NOT_HALTED;
 961         }
 962
 963         /* unlock option flash registers */
 964         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 965         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 966
 967         /* mass erase flash memory */
 968         target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
 969         target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
 970
 971         status = stm32x_wait_status_busy(bank, 10);
 972
 973         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 974
 975         if( status & FLASH_WRPRTERR )
 976         {
 977                 command_print(cmd_ctx, "stm32x device protected");
 978                 return ERROR_OK;
 979         }
 980
 981         if( status & FLASH_PGERR )
 982         {
 983                 command_print(cmd_ctx, "stm32x device programming failed");
 984                 return ERROR_OK;
 985         }
 986
 987         /* set all sectors as erased */
 988         for (i = 0; i < bank->num_sectors; i++)
 989         {
 990                 bank->sectors[i].is_erased = 1;
 991         }
 992
 993         command_print(cmd_ctx, "stm32x mass erase complete");
 994
 995         return ERROR_OK;
 996 }