git.gag.com Git - fw/openocd/blob - src/flash/stm32x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "stm32x.h"
  27 #include "flash.h"
  28 #include "target.h"
  29 #include "log.h"
  30 #include "armv7m.h"
  31 #include "algorithm.h"
  32 #include "binarybuffer.h"
  33
  34 #include <stdlib.h>
  35 #include <string.h>
  36
  37 int stm32x_register_commands(struct command_context_s *cmd_ctx);
  38 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  39 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
  40 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
  41 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  42 int stm32x_probe(struct flash_bank_s *bank);
  43 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  44 int stm32x_protect_check(struct flash_bank_s *bank);
  45 int stm32x_erase_check(struct flash_bank_s *bank);
  46 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
  47
  48 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  49 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  50 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  51 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53
  54 flash_driver_t stm32x_flash =
  55 {
  56         .name = "stm32x",
  57         .register_commands = stm32x_register_commands,
  58         .flash_bank_command = stm32x_flash_bank_command,
  59         .erase = stm32x_erase,
  60         .protect = stm32x_protect,
  61         .write = stm32x_write,
  62         .probe = stm32x_probe,
  63         .erase_check = stm32x_erase_check,
  64         .protect_check = stm32x_protect_check,
  65         .info = stm32x_info
  66 };
  67
  68 int stm32x_register_commands(struct command_context_s *cmd_ctx)
  69 {
  70         command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
  71
  72         register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
  73                                          "lock device");
  74         register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
  75                                          "unlock protected device");
  76         register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
  77                                          "mass erase device");
  78         register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
  79                                          "read device option bytes");
  80         register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
  81                                          "write device option bytes");
  82         return ERROR_OK;
  83 }
  84
  85 int stm32x_build_block_list(struct flash_bank_s *bank)
  86 {
  87         int i;
  88         int num_sectors = 0;
  89
  90         switch (bank->size)
  91         {
  92                 case 32 * 1024:
  93                         num_sectors = 32;
  94                         break;
  95                 case 64 * 1024:
  96                         num_sectors = 64;
  97                         break;
  98                 case 128 * 1024:
  99                         num_sectors = 128;
 100                         break;
 101                 default:
 102                         ERROR("BUG: unknown bank->size encountered");
 103                         exit(-1);
 104         }
 105
 106         bank->num_sectors = num_sectors;
 107         bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
 108
 109         for (i = 0; i < num_sectors; i++)
 110         {
 111                 bank->sectors[i].offset = i * 1024;
 112                 bank->sectors[i].size = 1024;
 113                 bank->sectors[i].is_erased = -1;
 114                 bank->sectors[i].is_protected = 1;
 115         }
 116
 117         return ERROR_OK;
 118 }
 119
 120 /* flash bank stm32x <base> <size> 0 0 <target#>
 121  */
 122 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 123 {
 124         stm32x_flash_bank_t *stm32x_info;
 125
 126         if (argc < 6)
 127         {
 128                 WARNING("incomplete flash_bank stm32x configuration");
 129                 return ERROR_FLASH_BANK_INVALID;
 130         }
 131
 132         stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
 133         bank->driver_priv = stm32x_info;
 134
 135         if (bank->base != 0x08000000)
 136         {
 137                 WARNING("overriding flash base address for STM32x device with 0x08000000");
 138                 bank->base = 0x08000000;
 139         }
 140
 141         stm32x_build_block_list(bank);
 142
 143         stm32x_info->write_algorithm = NULL;
 144
 145         return ERROR_OK;
 146 }
 147
 148 u32 stm32x_get_flash_status(flash_bank_t *bank)
 149 {
 150         target_t *target = bank->target;
 151         u32 status;
 152
 153         target_read_u32(target, STM32_FLASH_SR, &status);
 154
 155         return status;
 156 }
 157
 158 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
 159 {
 160         u32 status;
 161
 162         /* wait for busy to clear */
 163         while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
 164         {
 165                 DEBUG("status: 0x%x", status);
 166                 usleep(1000);
 167         }
 168
 169         return status;
 170 }
 171
 172 int stm32x_read_options(struct flash_bank_s *bank)
 173 {
 174         u32 optiondata;
 175         stm32x_flash_bank_t *stm32x_info = NULL;
 176         target_t *target = bank->target;
 177
 178         stm32x_info = bank->driver_priv;
 179
 180         /* read current option bytes */
 181         target_read_u32(target, STM32_FLASH_OBR, &optiondata);
 182
 183         stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
 184         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 185
 186         if (optiondata & (1 << OPT_READOUT))
 187                 INFO("Device Security Bit Set");
 188
 189         /* each bit refers to a 4bank protection */
 190         target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
 191
 192         stm32x_info->option_bytes.protection[0] = (u16)optiondata;
 193         stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
 194         stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
 195         stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
 196
 197         return ERROR_OK;
 198 }
 199
 200 int stm32x_erase_options(struct flash_bank_s *bank)
 201 {
 202         stm32x_flash_bank_t *stm32x_info = NULL;
 203         target_t *target = bank->target;
 204         u32 status;
 205
 206         stm32x_info = bank->driver_priv;
 207
 208         /* read current options */
 209         stm32x_read_options(bank);
 210
 211         /* unlock flash registers */
 212         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 213         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 214
 215         /* unlock option flash registers */
 216         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 217         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 218
 219         /* erase option bytes */
 220         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
 221         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
 222
 223         status = stm32x_wait_status_busy(bank, 10);
 224
 225         if( status & FLASH_WRPRTERR )
 226                 return ERROR_FLASH_OPERATION_FAILED;
 227         if( status & FLASH_PGERR )
 228                 return ERROR_FLASH_OPERATION_FAILED;
 229
 230         /* clear readout protection and complementary option bytes
 231          * this will also force a device unlock if set */
 232         stm32x_info->option_bytes.RDP = 0x5AA5;
 233
 234         return ERROR_OK;
 235 }
 236
 237 int stm32x_write_options(struct flash_bank_s *bank)
 238 {
 239         stm32x_flash_bank_t *stm32x_info = NULL;
 240         target_t *target = bank->target;
 241         u32 status;
 242
 243         stm32x_info = bank->driver_priv;
 244
 245         /* unlock flash registers */
 246         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 247         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 248
 249         /* unlock option flash registers */
 250         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 251         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 252
 253         /* program option bytes */
 254         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
 255
 256         /* write user option byte */
 257         target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
 258
 259         status = stm32x_wait_status_busy(bank, 10);
 260
 261         if( status & FLASH_WRPRTERR )
 262                 return ERROR_FLASH_OPERATION_FAILED;
 263         if( status & FLASH_PGERR )
 264                 return ERROR_FLASH_OPERATION_FAILED;
 265
 266         /* write protection byte 1 */
 267         target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
 268
 269         status = stm32x_wait_status_busy(bank, 10);
 270
 271         if( status & FLASH_WRPRTERR )
 272                 return ERROR_FLASH_OPERATION_FAILED;
 273         if( status & FLASH_PGERR )
 274                 return ERROR_FLASH_OPERATION_FAILED;
 275
 276         /* write protection byte 2 */
 277         target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
 278
 279         status = stm32x_wait_status_busy(bank, 10);
 280
 281         if( status & FLASH_WRPRTERR )
 282                 return ERROR_FLASH_OPERATION_FAILED;
 283         if( status & FLASH_PGERR )
 284                 return ERROR_FLASH_OPERATION_FAILED;
 285
 286         /* write protection byte 3 */
 287         target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
 288
 289         status = stm32x_wait_status_busy(bank, 10);
 290
 291         if( status & FLASH_WRPRTERR )
 292                 return ERROR_FLASH_OPERATION_FAILED;
 293         if( status & FLASH_PGERR )
 294                 return ERROR_FLASH_OPERATION_FAILED;
 295
 296         /* write protection byte 4 */
 297         target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
 298
 299         status = stm32x_wait_status_busy(bank, 10);
 300
 301         if( status & FLASH_WRPRTERR )
 302                 return ERROR_FLASH_OPERATION_FAILED;
 303         if( status & FLASH_PGERR )
 304                 return ERROR_FLASH_OPERATION_FAILED;
 305
 306         /* write readout protection bit */
 307         target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
 308
 309         status = stm32x_wait_status_busy(bank, 10);
 310
 311         if( status & FLASH_WRPRTERR )
 312                 return ERROR_FLASH_OPERATION_FAILED;
 313         if( status & FLASH_PGERR )
 314                 return ERROR_FLASH_OPERATION_FAILED;
 315
 316         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 317
 318         return ERROR_OK;
 319 }
 320
 321 int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)
 322 {
 323         target_t *target = bank->target;
 324         u8 *buffer;
 325         int i;
 326         int nBytes;
 327
 328         if ((first < 0) || (last > bank->num_sectors))
 329                 return ERROR_FLASH_SECTOR_INVALID;
 330
 331         if (target->state != TARGET_HALTED)
 332         {
 333                 return ERROR_TARGET_NOT_HALTED;
 334         }
 335
 336         buffer = malloc(256);
 337
 338         for (i = first; i <= last; i++)
 339         {
 340                 bank->sectors[i].is_erased = 1;
 341
 342                 target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
 343
 344                 for (nBytes = 0; nBytes < 256; nBytes++)
 345                 {
 346                         if (buffer[nBytes] != 0xFF)
 347                         {
 348                                 bank->sectors[i].is_erased = 0;
 349                                 break;
 350                         }
 351                 }
 352         }
 353
 354         free(buffer);
 355
 356         return ERROR_OK;
 357 }
 358
 359 int stm32x_protect_check(struct flash_bank_s *bank)
 360 {
 361         target_t *target = bank->target;
 362
 363         u32 protection;
 364         int i, s;
 365         int num_bits;
 366
 367         if (target->state != TARGET_HALTED)
 368         {
 369                 return ERROR_TARGET_NOT_HALTED;
 370         }
 371
 372         /* each bit refers to a 4bank protection */
 373         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 374
 375         /* each protection bit is for 4 1K pages */
 376         num_bits = (bank->num_sectors / 4);
 377
 378         for (i = 0; i < num_bits; i++)
 379         {
 380                 int set = 1;
 381
 382                 if( protection & (1 << i))
 383                         set = 0;
 384
 385                 for (s = 0; s < 4; s++)
 386                         bank->sectors[(i * 4) + s].is_protected = set;
 387         }
 388
 389         return ERROR_OK;
 390 }
 391
 392 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
 393 {
 394         target_t *target = bank->target;
 395
 396         int i;
 397         u32 status;
 398
 399         if (target->state != TARGET_HALTED)
 400         {
 401                 return ERROR_TARGET_NOT_HALTED;
 402         }
 403
 404         /* unlock flash registers */
 405         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 406         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 407
 408         for (i = first; i <= last; i++)
 409         {
 410                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
 411                 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
 412                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
 413
 414                 status = stm32x_wait_status_busy(bank, 10);
 415
 416                 if( status & FLASH_WRPRTERR )
 417                         return ERROR_FLASH_OPERATION_FAILED;
 418                 if( status & FLASH_PGERR )
 419                         return ERROR_FLASH_OPERATION_FAILED;
 420                 bank->sectors[i].is_erased = 1;
 421         }
 422
 423         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 424
 425         return ERROR_OK;
 426 }
 427
 428 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
 429 {
 430         stm32x_flash_bank_t *stm32x_info = NULL;
 431         target_t *target = bank->target;
 432         u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 433         int i, reg, bit;
 434         int status;
 435         u32 protection;
 436
 437         stm32x_info = bank->driver_priv;
 438
 439         if (target->state != TARGET_HALTED)
 440         {
 441                 return ERROR_TARGET_NOT_HALTED;
 442         }
 443
 444         if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))
 445         {
 446                 WARNING("sector start/end incorrect - stm32 has 4K sector protection");
 447                 return ERROR_FLASH_SECTOR_INVALID;
 448         }
 449
 450         /* each bit refers to a 4bank protection */
 451         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 452
 453         prot_reg[0] = (u16)protection;
 454         prot_reg[1] = (u16)(protection >> 8);
 455         prot_reg[2] = (u16)(protection >> 16);
 456         prot_reg[3] = (u16)(protection >> 24);
 457
 458         for (i = first; i <= last; i++)
 459         {
 460                 reg = (i / 4) / 8;
 461                 bit = (i / 4) - (reg * 8);
 462
 463                 if( set )
 464                         prot_reg[reg] &= ~(1 << bit);
 465                 else
 466                         prot_reg[reg] |= (1 << bit);
 467         }
 468
 469         if ((status = stm32x_erase_options(bank)) != ERROR_OK)
 470                 return status;
 471
 472         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 473         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 474         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 475         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 476
 477         return stm32x_write_options(bank);
 478 }
 479
 480 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 481 {
 482         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 483         target_t *target = bank->target;
 484         u32 buffer_size = 8192;
 485         working_area_t *source;
 486         u32 address = bank->base + offset;
 487         reg_param_t reg_params[4];
 488         armv7m_algorithm_t armv7m_info;
 489         int retval = ERROR_OK;
 490
 491         u8 stm32x_flash_write_code[] = {
 492                                                                         /* write: */
 493                 0xDF, 0xF8, 0x24, 0x40,         /* ldr  r4, STM32_FLASH_CR */
 494                 0x09, 0x4D,                                     /* ldr  r5, STM32_FLASH_SR */
 495                 0x4F, 0xF0, 0x01, 0x03,         /* mov  r3, #1 */
 496                 0x23, 0x60,                                     /* str  r3, [r4, #0] */
 497                 0x30, 0xF8, 0x02, 0x3B,         /* ldrh r3, [r0], #2 */
 498                 0x21, 0xF8, 0x02, 0x3B,         /* strh r3, [r1], #2 */
 499                                                                         /* busy: */
 500                 0x2B, 0x68,                                     /* ldr  r3, [r5, #0] */
 501                 0x13, 0xF0, 0x01, 0x0F,         /* tst  r3, #0x01 */
 502                 0xFB, 0xD0,                                     /* beq  busy */
 503                 0x13, 0xF0, 0x14, 0x0F,         /* tst  r3, #0x14 */
 504                 0x01, 0xD1,                                     /* bne  exit */
 505                 0x01, 0x3A,                                     /* subs r2, r2, #1 */
 506                 0xED, 0xD1,                                     /* bne  write */
 507                                                                         /* exit: */
 508                 0xFE, 0xE7,                                     /* b exit */
 509                 0x10, 0x20, 0x02, 0x40,         /* STM32_FLASH_CR:      .word 0x40022010 */
 510                 0x0C, 0x20, 0x02, 0x40          /* STM32_FLASH_SR:      .word 0x4002200C */
 511         };
 512
 513         /* flash write code */
 514         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
 515         {
 516                 WARNING("no working area available, can't do block memory writes");
 517                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 518         };
 519
 520         target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
 521
 522         /* memory buffer */
 523         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
 524         {
 525                 buffer_size /= 2;
 526                 if (buffer_size <= 256)
 527                 {
 528                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
 529                         if (stm32x_info->write_algorithm)
 530                                 target_free_working_area(target, stm32x_info->write_algorithm);
 531
 532                         WARNING("no large enough working area available, can't do block memory writes");
 533                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 534                 }
 535         };
 536
 537         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 538         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 539         armv7m_info.core_state = ARMV7M_STATE_THUMB;
 540
 541         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 542         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 543         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 544         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
 545
 546         while (count > 0)
 547         {
 548                 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
 549
 550                 target_write_buffer(target, source->address, thisrun_count * 2, buffer);
 551
 552                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 553                 buf_set_u32(reg_params[1].value, 0, 32, address);
 554                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
 555
 556                 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
 557                                 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
 558                 {
 559                         ERROR("error executing str7x flash write algorithm");
 560                         break;
 561                 }
 562
 563                 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
 564                 {
 565                         retval = ERROR_FLASH_OPERATION_FAILED;
 566                         break;
 567                 }
 568
 569                 buffer += thisrun_count * 2;
 570                 address += thisrun_count * 2;
 571                 count -= thisrun_count;
 572         }
 573
 574         target_free_working_area(target, source);
 575         target_free_working_area(target, stm32x_info->write_algorithm);
 576
 577         destroy_reg_param(&reg_params[0]);
 578         destroy_reg_param(&reg_params[1]);
 579         destroy_reg_param(&reg_params[2]);
 580         destroy_reg_param(&reg_params[3]);
 581
 582         return retval;
 583 }
 584
 585 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 586 {
 587         target_t *target = bank->target;
 588         u32 words_remaining = (count / 2);
 589         u32 bytes_remaining = (count & 0x00000001);
 590         u32 address = bank->base + offset;
 591         u32 bytes_written = 0;
 592         u8 status;
 593         u32 retval;
 594
 595         if (target->state != TARGET_HALTED)
 596         {
 597                 return ERROR_TARGET_NOT_HALTED;
 598         }
 599
 600         if (offset & 0x1)
 601         {
 602                 WARNING("offset 0x%x breaks required 2-byte alignment", offset);
 603                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 604         }
 605
 606         /* unlock flash registers */
 607         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 608         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 609
 610         /* multiple half words (2-byte) to be programmed? */
 611         if (words_remaining > 0)
 612         {
 613                 /* try using a block write */
 614                 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
 615                 {
 616                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 617                         {
 618                                 /* if block write failed (no sufficient working area),
 619                                  * we use normal (slow) single dword accesses */
 620                                 WARNING("couldn't use block writes, falling back to single memory accesses");
 621                         }
 622                         else if (retval == ERROR_FLASH_OPERATION_FAILED)
 623                         {
 624                                 ERROR("flash writing failed with error code: 0x%x", retval);
 625                                 return ERROR_FLASH_OPERATION_FAILED;
 626                         }
 627                 }
 628                 else
 629                 {
 630                         buffer += words_remaining * 2;
 631                         address += words_remaining * 2;
 632                         words_remaining = 0;
 633                 }
 634         }
 635
 636         while (words_remaining > 0)
 637         {
 638                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 639                 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
 640
 641                 status = stm32x_wait_status_busy(bank, 5);
 642
 643                 if( status & FLASH_WRPRTERR )
 644                         return ERROR_FLASH_OPERATION_FAILED;
 645                 if( status & FLASH_PGERR )
 646                         return ERROR_FLASH_OPERATION_FAILED;
 647
 648                 bytes_written += 2;
 649                 words_remaining--;
 650                 address += 2;
 651         }
 652
 653         if (bytes_remaining)
 654         {
 655                 u8 last_halfword[2] = {0xff, 0xff};
 656                 int i = 0;
 657
 658                 while(bytes_remaining > 0)
 659                 {
 660                         last_halfword[i++] = *(buffer + bytes_written);
 661                         bytes_remaining--;
 662                         bytes_written++;
 663                 }
 664
 665                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 666                 target_write_u16(target, address, *(u16*)last_halfword);
 667
 668                 status = stm32x_wait_status_busy(bank, 5);
 669
 670                 if( status & FLASH_WRPRTERR )
 671                         return ERROR_FLASH_OPERATION_FAILED;
 672                 if( status & FLASH_PGERR )
 673                         return ERROR_FLASH_OPERATION_FAILED;
 674         }
 675
 676         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 677
 678         return ERROR_OK;
 679 }
 680
 681 int stm32x_probe(struct flash_bank_s *bank)
 682 {
 683         return ERROR_OK;
 684 }
 685
 686 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 687 {
 688         return ERROR_OK;
 689 }
 690
 691 int stm32x_erase_check(struct flash_bank_s *bank)
 692 {
 693         return stm32x_blank_check(bank, 0, bank->num_sectors - 1);
 694 }
 695
 696 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
 697 {
 698         snprintf(buf, buf_size, "stm32x flash driver info" );
 699         return ERROR_OK;
 700 }
 701
 702 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 703 {
 704         flash_bank_t *bank;
 705         target_t *target = NULL;
 706         stm32x_flash_bank_t *stm32x_info = NULL;
 707
 708         if (argc < 1)
 709         {
 710                 command_print(cmd_ctx, "stm32x lock <bank>");
 711                 return ERROR_OK;
 712         }
 713
 714         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 715         if (!bank)
 716         {
 717                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 718                 return ERROR_OK;
 719         }
 720
 721         stm32x_info = bank->driver_priv;
 722
 723         target = bank->target;
 724
 725         if (target->state != TARGET_HALTED)
 726         {
 727                 return ERROR_TARGET_NOT_HALTED;
 728         }
 729
 730         if (stm32x_erase_options(bank) != ERROR_OK)
 731         {
 732                 command_print(cmd_ctx, "stm32x failed to erase options");
 733                 return ERROR_OK;
 734         }
 735
 736         /* set readout protection */
 737         stm32x_info->option_bytes.RDP = 0;
 738
 739         if (stm32x_write_options(bank) != ERROR_OK)
 740         {
 741                 command_print(cmd_ctx, "stm32x failed to lock device");
 742                 return ERROR_OK;
 743         }
 744
 745         command_print(cmd_ctx, "stm32x locked");
 746
 747         return ERROR_OK;
 748 }
 749
 750 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 751 {
 752         flash_bank_t *bank;
 753         target_t *target = NULL;
 754         stm32x_flash_bank_t *stm32x_info = NULL;
 755
 756         if (argc < 1)
 757         {
 758                 command_print(cmd_ctx, "stm32x unlock <bank>");
 759                 return ERROR_OK;
 760         }
 761
 762         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 763         if (!bank)
 764         {
 765                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 766                 return ERROR_OK;
 767         }
 768
 769         stm32x_info = bank->driver_priv;
 770
 771         target = bank->target;
 772
 773         if (target->state != TARGET_HALTED)
 774         {
 775                 return ERROR_TARGET_NOT_HALTED;
 776         }
 777
 778         if (stm32x_erase_options(bank) != ERROR_OK)
 779         {
 780                 command_print(cmd_ctx, "stm32x failed to unlock device");
 781                 return ERROR_OK;
 782         }
 783
 784         if (stm32x_write_options(bank) != ERROR_OK)
 785         {
 786                 command_print(cmd_ctx, "stm32x failed to lock device");
 787                 return ERROR_OK;
 788         }
 789
 790         command_print(cmd_ctx, "stm32x unlocked");
 791
 792         return ERROR_OK;
 793 }
 794
 795 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 796 {
 797         flash_bank_t *bank;
 798         u32 optionbyte;
 799         target_t *target = NULL;
 800         stm32x_flash_bank_t *stm32x_info = NULL;
 801
 802         if (argc < 1)
 803         {
 804                 command_print(cmd_ctx, "stm32x options_read <bank>");
 805                 return ERROR_OK;
 806         }
 807
 808         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 809         if (!bank)
 810         {
 811                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 812                 return ERROR_OK;
 813         }
 814
 815         stm32x_info = bank->driver_priv;
 816
 817         target = bank->target;
 818
 819         if (target->state != TARGET_HALTED)
 820         {
 821                 return ERROR_TARGET_NOT_HALTED;
 822         }
 823
 824         target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
 825         command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
 826
 827         if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
 828                 command_print(cmd_ctx, "Option Byte Complement Error");
 829
 830         if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
 831                 command_print(cmd_ctx, "Readout Protection On");
 832         else
 833                 command_print(cmd_ctx, "Readout Protection Off");
 834
 835         if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
 836                 command_print(cmd_ctx, "Software Watchdog");
 837         else
 838                 command_print(cmd_ctx, "Hardware Watchdog");
 839
 840         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
 841                 command_print(cmd_ctx, "Stop: No reset generated");
 842         else
 843                 command_print(cmd_ctx, "Stop: Reset generated");
 844
 845         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
 846                 command_print(cmd_ctx, "Standby: No reset generated");
 847         else
 848                 command_print(cmd_ctx, "Standby: Reset generated");
 849
 850         return ERROR_OK;
 851 }
 852
 853 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 854 {
 855         flash_bank_t *bank;
 856         target_t *target = NULL;
 857         stm32x_flash_bank_t *stm32x_info = NULL;
 858         u16 optionbyte = 0xF8;
 859
 860         if (argc < 4)
 861         {
 862                 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
 863                 return ERROR_OK;
 864         }
 865
 866         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 867         if (!bank)
 868         {
 869                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 870                 return ERROR_OK;
 871         }
 872
 873         stm32x_info = bank->driver_priv;
 874
 875         target = bank->target;
 876
 877         if (target->state != TARGET_HALTED)
 878         {
 879                 return ERROR_TARGET_NOT_HALTED;
 880         }
 881
 882         if (strcmp(args[1], "SWWDG") == 0)
 883         {
 884                 optionbyte |= (1<<0);
 885         }
 886         else
 887         {
 888                 optionbyte &= ~(1<<0);
 889         }
 890
 891         if (strcmp(args[2], "NORSTSTNDBY") == 0)
 892         {
 893                 optionbyte |= (1<<1);
 894         }
 895         else
 896         {
 897                 optionbyte &= ~(1<<1);
 898         }
 899
 900         if (strcmp(args[3], "NORSTSTOP") == 0)
 901         {
 902                 optionbyte |= (1<<2);
 903         }
 904         else
 905         {
 906                 optionbyte &= ~(1<<2);
 907         }
 908
 909         if (stm32x_erase_options(bank) != ERROR_OK)
 910         {
 911                 command_print(cmd_ctx, "stm32x failed to erase options");
 912                 return ERROR_OK;
 913         }
 914
 915         stm32x_info->option_bytes.user_options = optionbyte;
 916
 917         if (stm32x_write_options(bank) != ERROR_OK)
 918         {
 919                 command_print(cmd_ctx, "stm32x failed to write options");
 920                 return ERROR_OK;
 921         }
 922
 923         command_print(cmd_ctx, "stm32x write options complete");
 924
 925         return ERROR_OK;
 926 }
 927
 928 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 929 {
 930         target_t *target = NULL;
 931         stm32x_flash_bank_t *stm32x_info = NULL;
 932         flash_bank_t *bank;
 933         u32 status;
 934
 935         if (argc < 1)
 936         {
 937                 command_print(cmd_ctx, "stm32x mass_erase <bank>");
 938                 return ERROR_OK;
 939         }
 940
 941         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 942         if (!bank)
 943         {
 944                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 945                 return ERROR_OK;
 946         }
 947
 948         stm32x_info = bank->driver_priv;
 949
 950         target = bank->target;
 951
 952         if (target->state != TARGET_HALTED)
 953         {
 954                 return ERROR_TARGET_NOT_HALTED;
 955         }
 956
 957         /* unlock option flash registers */
 958         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 959         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 960
 961         /* mass erase flash memory */
 962         target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
 963         target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
 964
 965         status = stm32x_wait_status_busy(bank, 10);
 966
 967         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 968
 969         if( status & FLASH_WRPRTERR )
 970         {
 971                 command_print(cmd_ctx, "stm32x device protected");
 972                 return ERROR_OK;
 973         }
 974
 975         if( status & FLASH_PGERR )
 976         {
 977                 command_print(cmd_ctx, "stm32x device programming failed");
 978                 return ERROR_OK;
 979         }
 980
 981         command_print(cmd_ctx, "stm32x mass erase complete");
 982
 983         return ERROR_OK;
 984 }