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   1 /***************************************************************************\r
   2  *   Copyright (C) 2005 by Dominic Rath                                    *\r
   3  *   Dominic.Rath@gmx.de                                                   *\r
   4  *                                                                         *\r
   5  *   This program is free software; you can redistribute it and/or modify  *\r
   6  *   it under the terms of the GNU General Public License as published by  *\r
   7  *   the Free Software Foundation; either version 2 of the License, or     *\r
   8  *   (at your option) any later version.                                   *\r
   9  *                                                                         *\r
  10  *   This program is distributed in the hope that it will be useful,       *\r
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *\r
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *\r
  13  *   GNU General Public License for more details.                          *\r
  14  *                                                                         *\r
  15  *   You should have received a copy of the GNU General Public License     *\r
  16  *   along with this program; if not, write to the                         *\r
  17  *   Free Software Foundation, Inc.,                                       *\r
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *\r
  19  ***************************************************************************/\r
  20 #ifdef HAVE_CONFIG_H\r
  21 #include "config.h"\r
  22 #endif\r
  23 \r
  24 #include "replacements.h"\r
  25 \r
  26 #include "stm32x.h"\r
  27 #include "flash.h"\r
  28 #include "target.h"\r
  29 #include "log.h"\r
  30 #include "armv7m.h"\r
  31 #include "algorithm.h"\r
  32 #include "binarybuffer.h"\r
  33 \r
  34 #include <stdlib.h>\r
  35 #include <string.h>\r
  36 \r
  37 int stm32x_register_commands(struct command_context_s *cmd_ctx);\r
  38 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);\r
  39 int stm32x_erase(struct flash_bank_s *bank, int first, int last);\r
  40 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);\r
  41 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);\r
  42 int stm32x_probe(struct flash_bank_s *bank);\r
  43 int stm32x_auto_probe(struct flash_bank_s *bank);\r
  44 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  45 int stm32x_protect_check(struct flash_bank_s *bank);\r
  46 int stm32x_erase_check(struct flash_bank_s *bank);\r
  47 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);\r
  48 \r
  49 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  50 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  51 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  52 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  53 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  54 \r
  55 flash_driver_t stm32x_flash =\r
  56 {\r
  57         .name = "stm32x",\r
  58         .register_commands = stm32x_register_commands,\r
  59         .flash_bank_command = stm32x_flash_bank_command,\r
  60         .erase = stm32x_erase,\r
  61         .protect = stm32x_protect,\r
  62         .write = stm32x_write,\r
  63         .probe = stm32x_probe,\r
  64         .auto_probe = stm32x_auto_probe,\r
  65         .erase_check = stm32x_erase_check,\r
  66         .protect_check = stm32x_protect_check,\r
  67         .info = stm32x_info\r
  68 };\r
  69 \r
  70 int stm32x_register_commands(struct command_context_s *cmd_ctx)\r
  71 {\r
  72         command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");\r
  73         \r
  74         register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,\r
  75                                          "lock device");\r
  76         register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,\r
  77                                          "unlock protected device");\r
  78         register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,\r
  79                                          "mass erase device");\r
  80         register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,\r
  81                                          "read device option bytes");\r
  82         register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,\r
  83                                          "write device option bytes");\r
  84         return ERROR_OK;\r
  85 }\r
  86 \r
  87 /* flash bank stm32x <base> <size> 0 0 <target#>\r
  88  */\r
  89 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)\r
  90 {\r
  91         stm32x_flash_bank_t *stm32x_info;\r
  92         \r
  93         if (argc < 6)\r
  94         {\r
  95                 WARNING("incomplete flash_bank stm32x configuration");\r
  96                 return ERROR_FLASH_BANK_INVALID;\r
  97         }\r
  98         \r
  99         stm32x_info = malloc(sizeof(stm32x_flash_bank_t));\r
 100         bank->driver_priv = stm32x_info;\r
 101         \r
 102         stm32x_info->write_algorithm = NULL;\r
 103         stm32x_info->probed = 0;\r
 104         \r
 105         return ERROR_OK;\r
 106 }\r
 107 \r
 108 u32 stm32x_get_flash_status(flash_bank_t *bank)\r
 109 {\r
 110         target_t *target = bank->target;\r
 111         u32 status;\r
 112         \r
 113         target_read_u32(target, STM32_FLASH_SR, &status);\r
 114         \r
 115         return status;\r
 116 }\r
 117 \r
 118 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)\r
 119 {\r
 120         u32 status;\r
 121         \r
 122         /* wait for busy to clear */\r
 123         while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))\r
 124         {\r
 125                 DEBUG("status: 0x%x", status);\r
 126                 usleep(1000);\r
 127         }\r
 128         \r
 129         return status;\r
 130 }\r
 131 \r
 132 int stm32x_read_options(struct flash_bank_s *bank)\r
 133 {\r
 134         u32 optiondata;\r
 135         stm32x_flash_bank_t *stm32x_info = NULL;\r
 136         target_t *target = bank->target;\r
 137         \r
 138         stm32x_info = bank->driver_priv;\r
 139         \r
 140         /* read current option bytes */\r
 141         target_read_u32(target, STM32_FLASH_OBR, &optiondata);\r
 142         \r
 143         stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);\r
 144         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;\r
 145         \r
 146         if (optiondata & (1 << OPT_READOUT))\r
 147                 INFO("Device Security Bit Set");\r
 148         \r
 149         /* each bit refers to a 4bank protection */\r
 150         target_read_u32(target, STM32_FLASH_WRPR, &optiondata);\r
 151         \r
 152         stm32x_info->option_bytes.protection[0] = (u16)optiondata;\r
 153         stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);\r
 154         stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);\r
 155         stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);\r
 156                 \r
 157         return ERROR_OK;\r
 158 }\r
 159 \r
 160 int stm32x_erase_options(struct flash_bank_s *bank)\r
 161 {\r
 162         stm32x_flash_bank_t *stm32x_info = NULL;\r
 163         target_t *target = bank->target;\r
 164         u32 status;\r
 165         \r
 166         stm32x_info = bank->driver_priv;\r
 167         \r
 168         /* read current options */\r
 169         stm32x_read_options(bank);\r
 170         \r
 171         /* unlock flash registers */\r
 172         target_write_u32(target, STM32_FLASH_KEYR, KEY1);\r
 173         target_write_u32(target, STM32_FLASH_KEYR, KEY2);\r
 174         \r
 175         /* unlock option flash registers */\r
 176         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);\r
 177         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);\r
 178         \r
 179         /* erase option bytes */\r
 180         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);\r
 181         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);\r
 182         \r
 183         status = stm32x_wait_status_busy(bank, 10);\r
 184         \r
 185         if( status & FLASH_WRPRTERR )\r
 186                 return ERROR_FLASH_OPERATION_FAILED;\r
 187         if( status & FLASH_PGERR )\r
 188                 return ERROR_FLASH_OPERATION_FAILED;\r
 189         \r
 190         /* clear readout protection and complementary option bytes\r
 191          * this will also force a device unlock if set */\r
 192         stm32x_info->option_bytes.RDP = 0x5AA5;\r
 193         \r
 194         return ERROR_OK;\r
 195 }\r
 196 \r
 197 int stm32x_write_options(struct flash_bank_s *bank)\r
 198 {\r
 199         stm32x_flash_bank_t *stm32x_info = NULL;\r
 200         target_t *target = bank->target;\r
 201         u32 status;\r
 202         \r
 203         stm32x_info = bank->driver_priv;\r
 204         \r
 205         /* unlock flash registers */\r
 206         target_write_u32(target, STM32_FLASH_KEYR, KEY1);\r
 207         target_write_u32(target, STM32_FLASH_KEYR, KEY2);\r
 208         \r
 209         /* unlock option flash registers */\r
 210         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);\r
 211         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);\r
 212         \r
 213         /* program option bytes */\r
 214         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);\r
 215                 \r
 216         /* write user option byte */\r
 217         target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);\r
 218         \r
 219         status = stm32x_wait_status_busy(bank, 10);\r
 220         \r
 221         if( status & FLASH_WRPRTERR )\r
 222                 return ERROR_FLASH_OPERATION_FAILED;\r
 223         if( status & FLASH_PGERR )\r
 224                 return ERROR_FLASH_OPERATION_FAILED;\r
 225         \r
 226         /* write protection byte 1 */\r
 227         target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);\r
 228         \r
 229         status = stm32x_wait_status_busy(bank, 10);\r
 230         \r
 231         if( status & FLASH_WRPRTERR )\r
 232                 return ERROR_FLASH_OPERATION_FAILED;\r
 233         if( status & FLASH_PGERR )\r
 234                 return ERROR_FLASH_OPERATION_FAILED;\r
 235         \r
 236         /* write protection byte 2 */\r
 237         target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);\r
 238         \r
 239         status = stm32x_wait_status_busy(bank, 10);\r
 240         \r
 241         if( status & FLASH_WRPRTERR )\r
 242                 return ERROR_FLASH_OPERATION_FAILED;\r
 243         if( status & FLASH_PGERR )\r
 244                 return ERROR_FLASH_OPERATION_FAILED;\r
 245         \r
 246         /* write protection byte 3 */\r
 247         target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);\r
 248         \r
 249         status = stm32x_wait_status_busy(bank, 10);\r
 250         \r
 251         if( status & FLASH_WRPRTERR )\r
 252                 return ERROR_FLASH_OPERATION_FAILED;\r
 253         if( status & FLASH_PGERR )\r
 254                 return ERROR_FLASH_OPERATION_FAILED;\r
 255         \r
 256         /* write protection byte 4 */\r
 257         target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);\r
 258         \r
 259         status = stm32x_wait_status_busy(bank, 10);\r
 260         \r
 261         if( status & FLASH_WRPRTERR )\r
 262                 return ERROR_FLASH_OPERATION_FAILED;\r
 263         if( status & FLASH_PGERR )\r
 264                 return ERROR_FLASH_OPERATION_FAILED;\r
 265         \r
 266         /* write readout protection bit */\r
 267         target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);\r
 268         \r
 269         status = stm32x_wait_status_busy(bank, 10);\r
 270         \r
 271         if( status & FLASH_WRPRTERR )\r
 272                 return ERROR_FLASH_OPERATION_FAILED;\r
 273         if( status & FLASH_PGERR )\r
 274                 return ERROR_FLASH_OPERATION_FAILED;\r
 275         \r
 276         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);\r
 277         \r
 278         return ERROR_OK;\r
 279 }\r
 280 \r
 281 int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)\r
 282 {\r
 283         target_t *target = bank->target;\r
 284         u8 *buffer;\r
 285         int i;\r
 286         int nBytes;\r
 287         \r
 288         if ((first < 0) || (last > bank->num_sectors))\r
 289                 return ERROR_FLASH_SECTOR_INVALID;\r
 290 \r
 291         if (target->state != TARGET_HALTED)\r
 292         {\r
 293                 return ERROR_TARGET_NOT_HALTED;\r
 294         }\r
 295         \r
 296         buffer = malloc(256);\r
 297         \r
 298         for (i = first; i <= last; i++)\r
 299         {\r
 300                 bank->sectors[i].is_erased = 1;\r
 301 \r
 302                 target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);\r
 303                 \r
 304                 for (nBytes = 0; nBytes < 256; nBytes++)\r
 305                 {\r
 306                         if (buffer[nBytes] != 0xFF)\r
 307                         {\r
 308                                 bank->sectors[i].is_erased = 0;\r
 309                                 break;\r
 310                         }\r
 311                 }       \r
 312         }\r
 313         \r
 314         free(buffer);\r
 315 \r
 316         return ERROR_OK;\r
 317 }\r
 318 \r
 319 int stm32x_protect_check(struct flash_bank_s *bank)\r
 320 {\r
 321         target_t *target = bank->target;\r
 322         \r
 323         u32 protection;\r
 324         int i, s;\r
 325         int num_bits;\r
 326 \r
 327         if (target->state != TARGET_HALTED)\r
 328         {\r
 329                 return ERROR_TARGET_NOT_HALTED;\r
 330         }\r
 331 \r
 332         /* each bit refers to a 4bank protection */\r
 333         target_read_u32(target, STM32_FLASH_WRPR, &protection);\r
 334         \r
 335         /* each protection bit is for 4 1K pages */\r
 336         num_bits = (bank->num_sectors / 4);\r
 337         \r
 338         for (i = 0; i < num_bits; i++)\r
 339         {\r
 340                 int set = 1;\r
 341                 \r
 342                 if( protection & (1 << i))\r
 343                         set = 0;\r
 344                 \r
 345                 for (s = 0; s < 4; s++)\r
 346                         bank->sectors[(i * 4) + s].is_protected = set;\r
 347         }\r
 348 \r
 349         return ERROR_OK;\r
 350 }\r
 351 \r
 352 int stm32x_erase(struct flash_bank_s *bank, int first, int last)\r
 353 {\r
 354         target_t *target = bank->target;\r
 355         \r
 356         int i;\r
 357         u32 status;\r
 358         \r
 359         /* unlock flash registers */\r
 360         target_write_u32(target, STM32_FLASH_KEYR, KEY1);\r
 361         target_write_u32(target, STM32_FLASH_KEYR, KEY2);\r
 362         \r
 363         for (i = first; i <= last; i++)\r
 364         {       \r
 365                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);\r
 366                 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);\r
 367                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);\r
 368                 \r
 369                 status = stm32x_wait_status_busy(bank, 10);\r
 370                 \r
 371                 if( status & FLASH_WRPRTERR )\r
 372                         return ERROR_FLASH_OPERATION_FAILED;\r
 373                 if( status & FLASH_PGERR )\r
 374                         return ERROR_FLASH_OPERATION_FAILED;\r
 375                 bank->sectors[i].is_erased = 1;\r
 376         }\r
 377 \r
 378         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);\r
 379         \r
 380         return ERROR_OK;\r
 381 }\r
 382 \r
 383 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)\r
 384 {\r
 385         stm32x_flash_bank_t *stm32x_info = NULL;\r
 386         target_t *target = bank->target;\r
 387         u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};\r
 388         int i, reg, bit;\r
 389         int status;\r
 390         u32 protection;\r
 391         \r
 392         stm32x_info = bank->driver_priv;\r
 393         \r
 394         if (target->state != TARGET_HALTED)\r
 395         {\r
 396                 return ERROR_TARGET_NOT_HALTED;\r
 397         }\r
 398         \r
 399         if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))\r
 400         {\r
 401                 WARNING("sector start/end incorrect - stm32 has 4K sector protection");\r
 402                 return ERROR_FLASH_SECTOR_INVALID;\r
 403         }\r
 404         \r
 405         /* each bit refers to a 4bank protection */\r
 406         target_read_u32(target, STM32_FLASH_WRPR, &protection);\r
 407         \r
 408         prot_reg[0] = (u16)protection;\r
 409         prot_reg[1] = (u16)(protection >> 8);\r
 410         prot_reg[2] = (u16)(protection >> 16);\r
 411         prot_reg[3] = (u16)(protection >> 24);\r
 412         \r
 413         for (i = first; i <= last; i++)\r
 414         {\r
 415                 reg = (i / 4) / 8;\r
 416                 bit = (i / 4) - (reg * 8);\r
 417                 \r
 418                 if( set )\r
 419                         prot_reg[reg] &= ~(1 << bit);\r
 420                 else\r
 421                         prot_reg[reg] |= (1 << bit);\r
 422         }\r
 423         \r
 424         if ((status = stm32x_erase_options(bank)) != ERROR_OK)\r
 425                 return status;\r
 426         \r
 427         stm32x_info->option_bytes.protection[0] = prot_reg[0];\r
 428         stm32x_info->option_bytes.protection[1] = prot_reg[1];\r
 429         stm32x_info->option_bytes.protection[2] = prot_reg[2];\r
 430         stm32x_info->option_bytes.protection[3] = prot_reg[3];\r
 431         \r
 432         return stm32x_write_options(bank);\r
 433 }\r
 434 \r
 435 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)\r
 436 {\r
 437         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;\r
 438         target_t *target = bank->target;\r
 439         u32 buffer_size = 8192;\r
 440         working_area_t *source;\r
 441         u32 address = bank->base + offset;\r
 442         reg_param_t reg_params[4];\r
 443         armv7m_algorithm_t armv7m_info;\r
 444         int retval = ERROR_OK;\r
 445         \r
 446         u8 stm32x_flash_write_code[] = {\r
 447                                                                         /* write: */\r
 448                 0xDF, 0xF8, 0x24, 0x40,         /* ldr  r4, STM32_FLASH_CR */\r
 449                 0x09, 0x4D,                                     /* ldr  r5, STM32_FLASH_SR */\r
 450                 0x4F, 0xF0, 0x01, 0x03,         /* mov  r3, #1 */\r
 451                 0x23, 0x60,                                     /* str  r3, [r4, #0] */\r
 452                 0x30, 0xF8, 0x02, 0x3B,         /* ldrh r3, [r0], #2 */\r
 453                 0x21, 0xF8, 0x02, 0x3B,         /* strh r3, [r1], #2 */\r
 454                                                                         /* busy: */\r
 455                 0x2B, 0x68,                                     /* ldr  r3, [r5, #0] */\r
 456                 0x13, 0xF0, 0x01, 0x0F,         /* tst  r3, #0x01 */\r
 457                 0xFB, 0xD0,                                     /* beq  busy */\r
 458                 0x13, 0xF0, 0x14, 0x0F,         /* tst  r3, #0x14 */\r
 459                 0x01, 0xD1,                                     /* bne  exit */\r
 460                 0x01, 0x3A,                                     /* subs r2, r2, #1 */\r
 461                 0xED, 0xD1,                                     /* bne  write */\r
 462                                                                         /* exit: */\r
 463                 0xFE, 0xE7,                                     /* b exit */                            \r
 464                 0x10, 0x20, 0x02, 0x40,         /* STM32_FLASH_CR:      .word 0x40022010 */\r
 465                 0x0C, 0x20, 0x02, 0x40          /* STM32_FLASH_SR:      .word 0x4002200C */\r
 466         };\r
 467         \r
 468         /* flash write code */\r
 469         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)\r
 470         {\r
 471                 WARNING("no working area available, can't do block memory writes");\r
 472                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;\r
 473         };\r
 474         \r
 475         target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);\r
 476 \r
 477         /* memory buffer */\r
 478         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)\r
 479         {\r
 480                 buffer_size /= 2;\r
 481                 if (buffer_size <= 256)\r
 482                 {\r
 483                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */\r
 484                         if (stm32x_info->write_algorithm)\r
 485                                 target_free_working_area(target, stm32x_info->write_algorithm);\r
 486                         \r
 487                         WARNING("no large enough working area available, can't do block memory writes");\r
 488                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;\r
 489                 }\r
 490         };\r
 491         \r
 492         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;\r
 493         armv7m_info.core_mode = ARMV7M_MODE_ANY;\r
 494         armv7m_info.core_state = ARMV7M_STATE_THUMB;\r
 495         \r
 496         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);\r
 497         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);\r
 498         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);\r
 499         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);\r
 500         \r
 501         while (count > 0)\r
 502         {\r
 503                 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;\r
 504                 \r
 505                 target_write_buffer(target, source->address, thisrun_count * 2, buffer);\r
 506                 \r
 507                 buf_set_u32(reg_params[0].value, 0, 32, source->address);\r
 508                 buf_set_u32(reg_params[1].value, 0, 32, address);\r
 509                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);\r
 510                 \r
 511                 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \\r
 512                                 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)\r
 513                 {\r
 514                         ERROR("error executing str7x flash write algorithm");\r
 515                         break;\r
 516                 }\r
 517                 \r
 518                 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)\r
 519                 {\r
 520                         retval = ERROR_FLASH_OPERATION_FAILED;\r
 521                         break;\r
 522                 }\r
 523                 \r
 524                 buffer += thisrun_count * 2;\r
 525                 address += thisrun_count * 2;\r
 526                 count -= thisrun_count;\r
 527         }\r
 528         \r
 529         target_free_working_area(target, source);\r
 530         target_free_working_area(target, stm32x_info->write_algorithm);\r
 531         \r
 532         destroy_reg_param(&reg_params[0]);\r
 533         destroy_reg_param(&reg_params[1]);\r
 534         destroy_reg_param(&reg_params[2]);\r
 535         destroy_reg_param(&reg_params[3]);\r
 536         \r
 537         return retval;\r
 538 }\r
 539 \r
 540 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)\r
 541 {\r
 542         target_t *target = bank->target;\r
 543         u32 words_remaining = (count / 2);\r
 544         u32 bytes_remaining = (count & 0x00000001);\r
 545         u32 address = bank->base + offset;\r
 546         u32 bytes_written = 0;\r
 547         u8 status;\r
 548         u32 retval;\r
 549         \r
 550         if (offset & 0x1)\r
 551         {\r
 552                 WARNING("offset 0x%x breaks required 2-byte alignment", offset);\r
 553                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;\r
 554         }\r
 555         \r
 556         /* unlock flash registers */\r
 557         target_write_u32(target, STM32_FLASH_KEYR, KEY1);\r
 558         target_write_u32(target, STM32_FLASH_KEYR, KEY2);\r
 559         \r
 560         /* multiple half words (2-byte) to be programmed? */\r
 561         if (words_remaining > 0) \r
 562         {\r
 563                 /* try using a block write */\r
 564                 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)\r
 565                 {\r
 566                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)\r
 567                         {\r
 568                                 /* if block write failed (no sufficient working area),\r
 569                                  * we use normal (slow) single dword accesses */ \r
 570                                 WARNING("couldn't use block writes, falling back to single memory accesses");\r
 571                         }\r
 572                         else if (retval == ERROR_FLASH_OPERATION_FAILED)\r
 573                         {\r
 574                                 ERROR("flash writing failed with error code: 0x%x", retval);\r
 575                                 return ERROR_FLASH_OPERATION_FAILED;\r
 576                         }\r
 577                 }\r
 578                 else\r
 579                 {\r
 580                         buffer += words_remaining * 2;\r
 581                         address += words_remaining * 2;\r
 582                         words_remaining = 0;\r
 583                 }\r
 584         }\r
 585 \r
 586         while (words_remaining > 0)\r
 587         {\r
 588                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);\r
 589                 target_write_u16(target, address, *(u16*)(buffer + bytes_written));\r
 590                 \r
 591                 status = stm32x_wait_status_busy(bank, 5);\r
 592                 \r
 593                 if( status & FLASH_WRPRTERR )\r
 594                         return ERROR_FLASH_OPERATION_FAILED;\r
 595                 if( status & FLASH_PGERR )\r
 596                         return ERROR_FLASH_OPERATION_FAILED;\r
 597 \r
 598                 bytes_written += 2;\r
 599                 words_remaining--;\r
 600                 address += 2;\r
 601         }\r
 602         \r
 603         if (bytes_remaining)\r
 604         {\r
 605                 u8 last_halfword[2] = {0xff, 0xff};\r
 606                 int i = 0;\r
 607                                 \r
 608                 while(bytes_remaining > 0)\r
 609                 {\r
 610                         last_halfword[i++] = *(buffer + bytes_written); \r
 611                         bytes_remaining--;\r
 612                         bytes_written++;\r
 613                 }\r
 614                 \r
 615                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);\r
 616                 target_write_u16(target, address, *(u16*)last_halfword);\r
 617                 \r
 618                 status = stm32x_wait_status_busy(bank, 5);\r
 619                 \r
 620                 if( status & FLASH_WRPRTERR )\r
 621                         return ERROR_FLASH_OPERATION_FAILED;\r
 622                 if( status & FLASH_PGERR )\r
 623                         return ERROR_FLASH_OPERATION_FAILED;\r
 624         }\r
 625         \r
 626         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);\r
 627         \r
 628         return ERROR_OK;\r
 629 }\r
 630 \r
 631 int stm32x_probe(struct flash_bank_s *bank)\r
 632 {\r
 633         target_t *target = bank->target;\r
 634         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;\r
 635         int i;\r
 636         u16 num_sectors;\r
 637         u32 device_id;\r
 638         \r
 639         stm32x_info->probed = 0;\r
 640         \r
 641         /* read stm32 device id register */\r
 642         target_read_u32(target, 0xE0042000, &device_id);\r
 643         INFO( "device id = 0x%08x", device_id );\r
 644         \r
 645         if (!(device_id & 0x410))\r
 646     {\r
 647                 WARNING( "Cannot identify target as a STM32 family." );\r
 648                 return ERROR_FLASH_OPERATION_FAILED;\r
 649     }\r
 650     \r
 651         /* get flash size from target */\r
 652         target_read_u16(target, 0x1FFFF7E0, &num_sectors);\r
 653         \r
 654         /* check for early silicon rev A */\r
 655         if ((device_id >> 16) == 0 )\r
 656         {\r
 657                 /* number of sectors incorrect on revA */\r
 658                 WARNING( "STM32 Rev A Silicon detected, probe inaccurate - assuming 128k flash" );\r
 659                 num_sectors = 128;\r
 660         }\r
 661         \r
 662         INFO( "flash size = %dkbytes", num_sectors );\r
 663         \r
 664         bank->base = 0x08000000;\r
 665         bank->size = num_sectors * 1024;\r
 666         bank->num_sectors = num_sectors;\r
 667         bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);\r
 668         \r
 669         for (i = 0; i < num_sectors; i++)\r
 670         {\r
 671                 bank->sectors[i].offset = i * 1024;\r
 672                 bank->sectors[i].size = 1024;\r
 673                 bank->sectors[i].is_erased = -1;\r
 674                 bank->sectors[i].is_protected = 1;\r
 675         }\r
 676         \r
 677         stm32x_info->probed = 1;\r
 678         \r
 679         return ERROR_OK;\r
 680 }\r
 681 \r
 682 int stm32x_auto_probe(struct flash_bank_s *bank)\r
 683 {\r
 684         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;\r
 685         if (stm32x_info->probed)\r
 686                 return ERROR_OK;\r
 687         return stm32x_probe(bank);\r
 688 }\r
 689 \r
 690 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
 691 {\r
 692         return ERROR_OK;\r
 693 }\r
 694 \r
 695 int stm32x_erase_check(struct flash_bank_s *bank)\r
 696 {\r
 697         return stm32x_blank_check(bank, 0, bank->num_sectors - 1);\r
 698 }\r
 699 \r
 700 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)\r
 701 {\r
 702         snprintf(buf, buf_size, "stm32x flash driver info" );\r
 703         return ERROR_OK;\r
 704 }\r
 705 \r
 706 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
 707 {\r
 708         flash_bank_t *bank;\r
 709         target_t *target = NULL;\r
 710         stm32x_flash_bank_t *stm32x_info = NULL;\r
 711         \r
 712         if (argc < 1)\r
 713         {\r
 714                 command_print(cmd_ctx, "stm32x lock <bank>");\r
 715                 return ERROR_OK;        \r
 716         }\r
 717         \r
 718         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
 719         if (!bank)\r
 720         {\r
 721                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
 722                 return ERROR_OK;\r
 723         }\r
 724         \r
 725         stm32x_info = bank->driver_priv;\r
 726         \r
 727         target = bank->target;\r
 728         \r
 729         if (target->state != TARGET_HALTED)\r
 730         {\r
 731                 return ERROR_TARGET_NOT_HALTED;\r
 732         }\r
 733         \r
 734         if (stm32x_erase_options(bank) != ERROR_OK)\r
 735         {\r
 736                 command_print(cmd_ctx, "stm32x failed to erase options");\r
 737                 return ERROR_OK;\r
 738         }\r
 739                 \r
 740         /* set readout protection */    \r
 741         stm32x_info->option_bytes.RDP = 0;\r
 742         \r
 743         if (stm32x_write_options(bank) != ERROR_OK)\r
 744         {\r
 745                 command_print(cmd_ctx, "stm32x failed to lock device");\r
 746                 return ERROR_OK;\r
 747         }\r
 748         \r
 749         command_print(cmd_ctx, "stm32x locked");\r
 750         \r
 751         return ERROR_OK;\r
 752 }\r
 753 \r
 754 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
 755 {\r
 756         flash_bank_t *bank;\r
 757         target_t *target = NULL;\r
 758         stm32x_flash_bank_t *stm32x_info = NULL;\r
 759         \r
 760         if (argc < 1)\r
 761         {\r
 762                 command_print(cmd_ctx, "stm32x unlock <bank>");\r
 763                 return ERROR_OK;        \r
 764         }\r
 765         \r
 766         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
 767         if (!bank)\r
 768         {\r
 769                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
 770                 return ERROR_OK;\r
 771         }\r
 772         \r
 773         stm32x_info = bank->driver_priv;\r
 774         \r
 775         target = bank->target;\r
 776         \r
 777         if (target->state != TARGET_HALTED)\r
 778         {\r
 779                 return ERROR_TARGET_NOT_HALTED;\r
 780         }\r
 781                 \r
 782         if (stm32x_erase_options(bank) != ERROR_OK)\r
 783         {\r
 784                 command_print(cmd_ctx, "stm32x failed to unlock device");\r
 785                 return ERROR_OK;\r
 786         }\r
 787         \r
 788         if (stm32x_write_options(bank) != ERROR_OK)\r
 789         {\r
 790                 command_print(cmd_ctx, "stm32x failed to lock device");\r
 791                 return ERROR_OK;\r
 792         }\r
 793         \r
 794         command_print(cmd_ctx, "stm32x unlocked");\r
 795         \r
 796         return ERROR_OK;\r
 797 }\r
 798 \r
 799 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
 800 {\r
 801         flash_bank_t *bank;\r
 802         u32 optionbyte;\r
 803         target_t *target = NULL;\r
 804         stm32x_flash_bank_t *stm32x_info = NULL;\r
 805         \r
 806         if (argc < 1)\r
 807         {\r
 808                 command_print(cmd_ctx, "stm32x options_read <bank>");\r
 809                 return ERROR_OK;        \r
 810         }\r
 811         \r
 812         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
 813         if (!bank)\r
 814         {\r
 815                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
 816                 return ERROR_OK;\r
 817         }\r
 818         \r
 819         stm32x_info = bank->driver_priv;\r
 820         \r
 821         target = bank->target;\r
 822         \r
 823         if (target->state != TARGET_HALTED)\r
 824         {\r
 825                 return ERROR_TARGET_NOT_HALTED;\r
 826         }\r
 827         \r
 828         target_read_u32(target, STM32_FLASH_OBR, &optionbyte);\r
 829         command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);\r
 830         \r
 831         if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))\r
 832                 command_print(cmd_ctx, "Option Byte Complement Error");\r
 833         \r
 834         if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))\r
 835                 command_print(cmd_ctx, "Readout Protection On");\r
 836         else\r
 837                 command_print(cmd_ctx, "Readout Protection Off");\r
 838         \r
 839         if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))\r
 840                 command_print(cmd_ctx, "Software Watchdog");\r
 841         else\r
 842                 command_print(cmd_ctx, "Hardware Watchdog");\r
 843         \r
 844         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))\r
 845                 command_print(cmd_ctx, "Stop: No reset generated");\r
 846         else\r
 847                 command_print(cmd_ctx, "Stop: Reset generated");\r
 848         \r
 849         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))\r
 850                 command_print(cmd_ctx, "Standby: No reset generated");\r
 851         else\r
 852                 command_print(cmd_ctx, "Standby: Reset generated");\r
 853         \r
 854         return ERROR_OK;\r
 855 }\r
 856 \r
 857 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
 858 {\r
 859         flash_bank_t *bank;\r
 860         target_t *target = NULL;\r
 861         stm32x_flash_bank_t *stm32x_info = NULL;\r
 862         u16 optionbyte = 0xF8;\r
 863         \r
 864         if (argc < 4)\r
 865         {\r
 866                 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");\r
 867                 return ERROR_OK;        \r
 868         }\r
 869         \r
 870         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
 871         if (!bank)\r
 872         {\r
 873                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
 874                 return ERROR_OK;\r
 875         }\r
 876         \r
 877         stm32x_info = bank->driver_priv;\r
 878         \r
 879         target = bank->target;\r
 880         \r
 881         if (target->state != TARGET_HALTED)\r
 882         {\r
 883                 return ERROR_TARGET_NOT_HALTED;\r
 884         }\r
 885         \r
 886         if (strcmp(args[1], "SWWDG") == 0)\r
 887         {\r
 888                 optionbyte |= (1<<0);\r
 889         }\r
 890         else\r
 891         {\r
 892                 optionbyte &= ~(1<<0);\r
 893         }\r
 894         \r
 895         if (strcmp(args[2], "NORSTSTNDBY") == 0)\r
 896         {\r
 897                 optionbyte |= (1<<1);\r
 898         }\r
 899         else\r
 900         {\r
 901                 optionbyte &= ~(1<<1);\r
 902         }\r
 903         \r
 904         if (strcmp(args[3], "NORSTSTOP") == 0)\r
 905         {\r
 906                 optionbyte |= (1<<2);\r
 907         }\r
 908         else\r
 909         {\r
 910                 optionbyte &= ~(1<<2);\r
 911         }\r
 912         \r
 913         if (stm32x_erase_options(bank) != ERROR_OK)\r
 914         {\r
 915                 command_print(cmd_ctx, "stm32x failed to erase options");\r
 916                 return ERROR_OK;\r
 917         }\r
 918         \r
 919         stm32x_info->option_bytes.user_options = optionbyte;\r
 920         \r
 921         if (stm32x_write_options(bank) != ERROR_OK)\r
 922         {\r
 923                 command_print(cmd_ctx, "stm32x failed to write options");\r
 924                 return ERROR_OK;\r
 925         }\r
 926         \r
 927         command_print(cmd_ctx, "stm32x write options complete");\r
 928         \r
 929         return ERROR_OK;\r
 930 }\r
 931 \r
 932 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
 933 {\r
 934         target_t *target = NULL;\r
 935         stm32x_flash_bank_t *stm32x_info = NULL;\r
 936         flash_bank_t *bank;\r
 937         u32 status;\r
 938         \r
 939         if (argc < 1)\r
 940         {\r
 941                 command_print(cmd_ctx, "stm32x mass_erase <bank>");\r
 942                 return ERROR_OK;        \r
 943         }\r
 944         \r
 945         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
 946         if (!bank)\r
 947         {\r
 948                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
 949                 return ERROR_OK;\r
 950         }\r
 951         \r
 952         stm32x_info = bank->driver_priv;\r
 953         \r
 954         target = bank->target;\r
 955         \r
 956         if (target->state != TARGET_HALTED)\r
 957         {\r
 958                 return ERROR_TARGET_NOT_HALTED;\r
 959         }\r
 960         \r
 961         /* unlock option flash registers */\r
 962         target_write_u32(target, STM32_FLASH_KEYR, KEY1);\r
 963         target_write_u32(target, STM32_FLASH_KEYR, KEY2);\r
 964         \r
 965         /* mass erase flash memory */\r
 966         target_write_u32(target, STM32_FLASH_CR, FLASH_MER);\r
 967         target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);\r
 968         \r
 969         status = stm32x_wait_status_busy(bank, 10);\r
 970         \r
 971         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);\r
 972         \r
 973         if( status & FLASH_WRPRTERR )\r
 974         {\r
 975                 command_print(cmd_ctx, "stm32x device protected");\r
 976                 return ERROR_OK;\r
 977         }\r
 978         \r
 979         if( status & FLASH_PGERR )\r
 980         {\r
 981                 command_print(cmd_ctx, "stm32x device programming failed");\r
 982                 return ERROR_OK;\r
 983         }\r
 984         \r
 985         command_print(cmd_ctx, "stm32x mass erase complete");\r
 986         \r
 987         return ERROR_OK;\r
 988 }\r