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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20
  21 /***************************************************************************
  22 * STELLARIS is tested on LM3S811
  23 ***************************************************************************/
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "replacements.h"
  29
  30 #include "stellaris.h"
  31 #include "cortex_m3.h"
  32
  33 #include "flash.h"
  34 #include "target.h"
  35 #include "log.h"
  36 #include "binarybuffer.h"
  37 #include "types.h"
  38
  39 #include <stdlib.h>
  40 #include <string.h>
  41 #include <unistd.h>
  42
  43 #define DID0_VER(did0) ((did0>>28)&0x07)
  44 int stellaris_register_commands(struct command_context_s *cmd_ctx);
  45 int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  46 int stellaris_erase(struct flash_bank_s *bank, int first, int last);
  47 int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last);
  48 int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  49 int stellaris_auto_probe(struct flash_bank_s *bank);
  50 int stellaris_probe(struct flash_bank_s *bank);
  51 int stellaris_erase_check(struct flash_bank_s *bank);
  52 int stellaris_protect_check(struct flash_bank_s *bank);
  53 int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size);
  54
  55 int stellaris_read_part_info(struct flash_bank_s *bank);
  56 u32 stellaris_get_flash_status(flash_bank_t *bank);
  57 void stellaris_set_flash_mode(flash_bank_t *bank,int mode);
  58 u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
  59
  60 int stellaris_read_part_info(struct flash_bank_s *bank);
  61
  62 flash_driver_t stellaris_flash =
  63 {
  64         .name = "stellaris",
  65         .register_commands = stellaris_register_commands,
  66         .flash_bank_command = stellaris_flash_bank_command,
  67         .erase = stellaris_erase,
  68         .protect = stellaris_protect,
  69         .write = stellaris_write,
  70         .probe = stellaris_probe,
  71         .auto_probe = stellaris_auto_probe,
  72         .erase_check = stellaris_erase_check,
  73         .protect_check = stellaris_protect_check,
  74         .info = stellaris_info
  75 };
  76
  77 struct {
  78         u32 partno;
  79         char *partname;
  80 }       StellarisParts[] =
  81 {
  82         {0x01,"LM3S101"},
  83         {0x02,"LM3S102"},
  84         {0x19,"LM3S300"},
  85         {0x11,"LM3S301"},
  86         {0x12,"LM3S310"},
  87         {0x1A,"LM3S308"},
  88         {0x13,"LM3S315"},
  89         {0x14,"LM3S316"},
  90         {0x17,"LM3S317"},
  91         {0x18,"LM3S318"},
  92         {0x15,"LM3S328"},
  93         {0x2A,"LM3S600"},
  94         {0x21,"LM3S601"},
  95         {0x2B,"LM3S608"},
  96         {0x22,"LM3S610"},
  97         {0x23,"LM3S611"},
  98         {0x24,"LM3S612"},
  99         {0x25,"LM3S613"},
 100         {0x26,"LM3S615"},
 101         {0x28,"LM3S617"},
 102         {0x29,"LM3S618"},
 103         {0x27,"LM3S628"},
 104         {0x38,"LM3S800"},
 105         {0x31,"LM3S801"},
 106         {0x39,"LM3S808"},
 107         {0x32,"LM3S811"},
 108         {0x33,"LM3S812"},
 109         {0x34,"LM3S815"},
 110         {0x36,"LM3S817"},
 111         {0x37,"LM3S818"},
 112         {0x35,"LM3S828"},
 113         {0x51,"LM3S2110"},
 114         {0x52,"LM3S2739"},
 115         {0x53,"LM3S2651"},
 116         {0x54,"LM3S2939"},
 117         {0x55,"LM3S2965"},
 118         {0x56,"LM3S2432"},
 119         {0x57,"LM3S2620"},
 120         {0x58,"LM3S2950"},
 121         {0x59,"LM3S2412"},
 122         {0x5A,"LM3S2533"},
 123         {0x61,"LM3S8630"},
 124         {0x62,"LM3S8970"},
 125         {0x63,"LM3S8730"},
 126         {0x64,"LM3S8530"},
 127         {0x65,"LM3S8930"},
 128         {0x71,"LM3S6610"},
 129         {0x72,"LM3S6950"},
 130         {0x73,"LM3S6965"},
 131         {0x74,"LM3S6110"},
 132         {0x75,"LM3S6432"},
 133         {0x76,"LM3S6537"},
 134         {0x77,"LM3S6753"},
 135         {0x78,"LM3S6952"},
 136         {0x82,"LM3S6422"},
 137         {0x83,"LM3S6633"},
 138         {0x84,"LM3S2139"},
 139         {0x85,"LM3S2637"},
 140         {0x86,"LM3S8738"},
 141         {0x88,"LM3S8938"},
 142         {0x89,"LM3S6938"},
 143         {0x8B,"LM3S6637"},
 144         {0x8C,"LM3S8933"},
 145         {0x8D,"LM3S8733"},
 146         {0x8E,"LM3S8538"},
 147         {0x8F,"LM3S2948"},
 148         {0xA1,"LM3S6100"},
 149         {0xA2,"LM3S2410"},
 150         {0xA3,"LM3S6730"},
 151         {0xA4,"LM3S2730"},
 152         {0xA5,"LM3S6420"},
 153         {0xA6,"LM3S8962"},
 154         {0xB3,"LM3S1635"},
 155         {0xB4,"LM3S1850"},
 156         {0xB5,"LM3S1960"},
 157         {0xB7,"LM3S1937"},
 158         {0xB8,"LM3S1968"},
 159         {0xB9,"LM3S1751"},
 160         {0xBA,"LM3S1439"},
 161         {0xBB,"LM3S1512"},
 162         {0xBC,"LM3S1435"},
 163         {0xBD,"LM3S1637"},
 164         {0xBE,"LM3S1958"},
 165         {0xBF,"LM3S1110"},
 166         {0xC0,"LM3S1620"},
 167         {0xC1,"LM3S1150"},
 168         {0xC2,"LM3S1165"},
 169         {0xC3,"LM3S1133"},
 170         {0xC4,"LM3S1162"},
 171         {0xC5,"LM3S1138"},
 172         {0xC6,"LM3S1332"},
 173         {0xC7,"LM3S1538"},
 174         {0xD0,"LM3S6815"},
 175         {0xD1,"LM3S6816"},
 176         {0xD2,"LM3S6915"},
 177         {0xD3,"LM3S6916"},
 178         {0xD4,"LM3S2016"},
 179         {0xD5,"LM3S1615"},
 180         {0xD6,"LM3S1616"},
 181         {0xD7,"LM3S8971"},
 182         {0xD8,"LM3S1108"},
 183         {0xD9,"LM3S1101"},
 184         {0xDA,"LM3S1608"},
 185         {0xDB,"LM3S1601"},
 186         {0xDC,"LM3S1918"},
 187         {0xDD,"LM3S1911"},
 188         {0xDE,"LM3S2108"},
 189         {0xDF,"LM3S2101"},
 190         {0xE0,"LM3S2608"},
 191         {0xE1,"LM3S2601"},
 192         {0xE2,"LM3S2918"},
 193         {0xE3,"LM3S2911"},
 194         {0xE4,"LM3S6118"},
 195         {0xE5,"LM3S6111"},
 196         {0xE6,"LM3S6618"},
 197         {0xE7,"LM3S6611"},
 198         {0xE8,"LM3S6918"},
 199         {0xE9,"LM3S6911"},
 200         {0,"Unknown part"}
 201 };
 202
 203 char * StellarisClassname[2] =
 204 {
 205         "Sandstorm",
 206         "Fury"
 207 };
 208
 209 /***************************************************************************
 210 *       openocd command interface                                              *
 211 ***************************************************************************/
 212
 213 /* flash_bank stellaris <base> <size> 0 0 <target#>
 214  */
 215 int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 216 {
 217         stellaris_flash_bank_t *stellaris_info;
 218
 219         if (argc < 6)
 220         {
 221                 LOG_WARNING("incomplete flash_bank stellaris configuration");
 222                 return ERROR_FLASH_BANK_INVALID;
 223         }
 224
 225         stellaris_info = calloc(sizeof(stellaris_flash_bank_t),1);
 226         bank->base = 0x0;
 227         bank->driver_priv = stellaris_info;
 228
 229         stellaris_info->target_name = "Unknown target";
 230
 231         /* part wasn't probed for info yet */
 232         stellaris_info->did1 = 0;
 233
 234         /* TODO Use an optional main oscillator clock rate in kHz from arg[6] */
 235         return ERROR_OK;
 236 }
 237
 238 int stellaris_register_commands(struct command_context_s *cmd_ctx)
 239 {
 240 /*
 241         command_t *stellaris_cmd = register_command(cmd_ctx, NULL, "stellaris", NULL, COMMAND_ANY, NULL);
 242         register_command(cmd_ctx, stellaris_cmd, "gpnvm", stellaris_handle_gpnvm_command, COMMAND_EXEC,
 243                         "stellaris gpnvm <num> <bit> set|clear, set or clear stellaris gpnvm bit");
 244 */
 245         return ERROR_OK;
 246 }
 247
 248 int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
 249 {
 250         int printed, device_class;
 251         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
 252
 253         stellaris_read_part_info(bank);
 254
 255         if (stellaris_info->did1 == 0)
 256         {
 257                 printed = snprintf(buf, buf_size, "Cannot identify target as a Stellaris\n");
 258                 buf += printed;
 259                 buf_size -= printed;
 260                 return ERROR_FLASH_OPERATION_FAILED;
 261         }
 262
 263         if (DID0_VER(stellaris_info->did0)>0)
 264         {
 265                 device_class = (stellaris_info->did0>>16)&0xFF;
 266         }
 267         else
 268         {
 269                 device_class = 0;
 270         }
 271         printed = snprintf(buf, buf_size, "\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n",
 272           device_class, StellarisClassname[device_class], stellaris_info->target_name,
 273           'A' + ((stellaris_info->did0>>8)&0xFF), (stellaris_info->did0)&0xFF);
 274         buf += printed;
 275         buf_size -= printed;
 276
 277         printed = snprintf(buf, buf_size, "did1: 0x%8.8x, arch: 0x%4.4x, eproc: %s, ramsize:%ik,  flashsize: %ik\n",
 278          stellaris_info->did1, stellaris_info->did1, "ARMV7M", (1+((stellaris_info->dc0>>16)&0xFFFF))/4, (1+(stellaris_info->dc0&0xFFFF))*2);
 279         buf += printed;
 280         buf_size -= printed;
 281
 282         printed = snprintf(buf, buf_size, "master clock(estimated): %ikHz,  rcc is 0x%x \n", stellaris_info->mck_freq / 1000, stellaris_info->rcc);
 283         buf += printed;
 284         buf_size -= printed;
 285
 286         if (stellaris_info->num_lockbits>0) {
 287                 printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", stellaris_info->pagesize, stellaris_info->num_lockbits, stellaris_info->lockbits,stellaris_info->num_pages/stellaris_info->num_lockbits);
 288                 buf += printed;
 289                 buf_size -= printed;
 290         }
 291         return ERROR_OK;
 292 }
 293
 294 /***************************************************************************
 295 *       chip identification and status                                         *
 296 ***************************************************************************/
 297
 298 u32 stellaris_get_flash_status(flash_bank_t *bank)
 299 {
 300         target_t *target = bank->target;
 301         u32 fmc;
 302
 303         target_read_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, &fmc);
 304
 305         return fmc;
 306 }
 307
 308 /** Read clock configuration and set stellaris_info->usec_clocks*/
 309
 310 void stellaris_read_clock_info(flash_bank_t *bank)
 311 {
 312         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
 313         target_t *target = bank->target;
 314         u32 rcc, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
 315         unsigned long mainfreq;
 316
 317         target_read_u32(target, SCB_BASE|RCC, &rcc);
 318         LOG_DEBUG("Stellaris RCC %x",rcc);
 319         target_read_u32(target, SCB_BASE|PLLCFG, &pllcfg);
 320         LOG_DEBUG("Stellaris PLLCFG %x",pllcfg);
 321         stellaris_info->rcc = rcc;
 322
 323         sysdiv = (rcc>>23)&0xF;
 324         usesysdiv = (rcc>>22)&0x1;
 325         bypass = (rcc>>11)&0x1;
 326         oscsrc = (rcc>>4)&0x3;
 327         /* xtal = (rcc>>6)&0xF; */
 328         switch (oscsrc)
 329         {
 330                 case 0:
 331                         mainfreq = 6000000;  /* Default xtal */
 332                         break;
 333                 case 1:
 334                         mainfreq = 22500000; /* Internal osc. 15 MHz +- 50% */
 335                         break;
 336                 case 2:
 337                         mainfreq = 5625000;  /* Internal osc. / 4 */
 338                         break;
 339                 case 3:
 340                         LOG_WARNING("Invalid oscsrc (3) in rcc register");
 341                         mainfreq = 6000000;
 342                         break;
 343
 344                 default: /* NOTREACHED */
 345                         mainfreq = 0;
 346                         break;
 347         }
 348
 349         if (!bypass)
 350                 mainfreq = 200000000; /* PLL out frec */
 351
 352         if (usesysdiv)
 353                 stellaris_info->mck_freq = mainfreq/(1+sysdiv);
 354         else
 355                 stellaris_info->mck_freq = mainfreq;
 356
 357         /* Forget old flash timing */
 358         stellaris_set_flash_mode(bank,0);
 359 }
 360
 361 /* Setup the timimg registers */
 362 void stellaris_set_flash_mode(flash_bank_t *bank,int mode)
 363 {
 364         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
 365         target_t *target = bank->target;
 366
 367         u32 usecrl = (stellaris_info->mck_freq/1000000ul-1);
 368         LOG_DEBUG("usecrl = %i",usecrl);
 369         target_write_u32(target, SCB_BASE|USECRL , usecrl);
 370
 371 }
 372
 373 u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
 374 {
 375         u32 status;
 376
 377         /* Stellaris waits for cmdbit to clear */
 378         while (((status = stellaris_get_flash_status(bank)) & waitbits) && (timeout-- > 0))
 379         {
 380                 LOG_DEBUG("status: 0x%x", status);
 381                 usleep(1000);
 382         }
 383
 384         /* Flash errors are reflected in the FLASH_CRIS register */
 385
 386         return status;
 387 }
 388
 389 /* Send one command to the flash controller */
 390 int stellaris_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen)
 391 {
 392         u32 fmc;
 393         target_t *target = bank->target;
 394
 395         fmc = FMC_WRKEY | cmd;
 396         target_write_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, fmc);
 397         LOG_DEBUG("Flash command: 0x%x", fmc);
 398
 399         if (stellaris_wait_status_busy(bank, cmd, 100))
 400         {
 401                 return ERROR_FLASH_OPERATION_FAILED;
 402         }
 403
 404         return ERROR_OK;
 405 }
 406
 407 /* Read device id register, main clock frequency register and fill in driver info structure */
 408 int stellaris_read_part_info(struct flash_bank_s *bank)
 409 {
 410         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
 411         target_t *target = bank->target;
 412         u32 did0,did1, ver, fam, status;
 413         int i;
 414
 415         /* Read and parse chip identification register */
 416         target_read_u32(target, SCB_BASE|DID0, &did0);
 417         target_read_u32(target, SCB_BASE|DID1, &did1);
 418         target_read_u32(target, SCB_BASE|DC0, &stellaris_info->dc0);
 419         target_read_u32(target, SCB_BASE|DC1, &stellaris_info->dc1);
 420         LOG_DEBUG("did0 0x%x, did1 0x%x, dc0 0x%x, dc1 0x%x",did0, did1, stellaris_info->dc0,stellaris_info->dc1);
 421
 422         ver = did0 >> 28;
 423         if((ver != 0) && (ver != 1))
 424         {
 425                 LOG_WARNING("Unknown did0 version, cannot identify target");
 426                 return ERROR_FLASH_OPERATION_FAILED;
 427         }
 428
 429         if (did1 == 0)
 430         {
 431                 LOG_WARNING("Cannot identify target as a Stellaris");
 432                 return ERROR_FLASH_OPERATION_FAILED;
 433         }
 434
 435         ver = did1 >> 28;
 436         fam = (did1 >> 24) & 0xF;
 437         if(((ver != 0) && (ver != 1)) || (fam != 0))
 438         {
 439                 LOG_WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris");
 440         }
 441
 442         for (i=0;StellarisParts[i].partno;i++)
 443         {
 444                 if (StellarisParts[i].partno==((did1>>16)&0xFF))
 445                         break;
 446         }
 447
 448         stellaris_info->target_name = StellarisParts[i].partname;
 449
 450         stellaris_info->did0 = did0;
 451         stellaris_info->did1 = did1;
 452
 453         stellaris_info->num_lockbits = 1+(stellaris_info->dc0&0xFFFF);
 454         stellaris_info->num_pages = 2*(1+(stellaris_info->dc0&0xFFFF));
 455         stellaris_info->pagesize = 1024;
 456         bank->size = 1024*stellaris_info->num_pages;
 457         stellaris_info->pages_in_lockregion = 2;
 458         target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits);
 459
 460         /* provide this for the benefit of the higher flash driver layers */
 461         bank->num_sectors = stellaris_info->num_pages;
 462         bank->sectors = malloc(sizeof(flash_sector_t) * bank->num_sectors);
 463         for (i = 0; i < bank->num_sectors; i++)
 464         {
 465                 bank->sectors[i].offset = i*stellaris_info->pagesize;
 466                 bank->sectors[i].size = stellaris_info->pagesize;
 467                 bank->sectors[i].is_erased = -1;
 468                 bank->sectors[i].is_protected = -1;
 469         }
 470
 471         /* Read main and master clock freqency register */
 472         stellaris_read_clock_info(bank);
 473
 474         status = stellaris_get_flash_status(bank);
 475
 476         return ERROR_OK;
 477 }
 478
 479 /***************************************************************************
 480 *       flash operations                                                       *
 481 ***************************************************************************/
 482
 483 int stellaris_erase_check(struct flash_bank_s *bank)
 484 {
 485         /*
 486
 487         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
 488         target_t *target = bank->target;
 489         int i;
 490
 491         */
 492
 493         return ERROR_OK;
 494 }
 495
 496 int stellaris_protect_check(struct flash_bank_s *bank)
 497 {
 498         u32 status;
 499
 500         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
 501
 502         if (bank->target->state != TARGET_HALTED)
 503         {
 504                 return ERROR_TARGET_NOT_HALTED;
 505         }
 506
 507         if (stellaris_info->did1 == 0)
 508         {
 509                 stellaris_read_part_info(bank);
 510         }
 511
 512         if (stellaris_info->did1 == 0)
 513         {
 514                 LOG_WARNING("Cannot identify target as an AT91SAM");
 515                 return ERROR_FLASH_OPERATION_FAILED;
 516         }
 517
 518         status = stellaris_get_flash_status(bank);
 519         stellaris_info->lockbits = status >> 16;
 520
 521         return ERROR_OK;
 522 }
 523
 524 int stellaris_erase(struct flash_bank_s *bank, int first, int last)
 525 {
 526         int banknr;
 527         u32 flash_fmc, flash_cris;
 528         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
 529         target_t *target = bank->target;
 530
 531         if (bank->target->state != TARGET_HALTED)
 532         {
 533                 return ERROR_TARGET_NOT_HALTED;
 534         }
 535
 536         if (stellaris_info->did1 == 0)
 537         {
 538                 stellaris_read_part_info(bank);
 539         }
 540
 541         if (stellaris_info->did1 == 0)
 542         {
 543                 LOG_WARNING("Cannot identify target as Stellaris");
 544                 return ERROR_FLASH_OPERATION_FAILED;
 545         }
 546
 547         if ((first < 0) || (last < first) || (last >= stellaris_info->num_pages))
 548         {
 549                 return ERROR_FLASH_SECTOR_INVALID;
 550         }
 551
 552         /* Configure the flash controller timing */
 553         stellaris_read_clock_info(bank);
 554         stellaris_set_flash_mode(bank,0);
 555
 556         /* Clear and disable flash programming interrupts */
 557         target_write_u32(target, FLASH_CIM, 0);
 558         target_write_u32(target, FLASH_MISC, PMISC|AMISC);
 559
 560         if ((first == 0) && (last == (stellaris_info->num_pages-1)))
 561         {
 562                 target_write_u32(target, FLASH_FMA, 0);
 563                 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
 564                 /* Wait until erase complete */
 565                 do
 566                 {
 567                         target_read_u32(target, FLASH_FMC, &flash_fmc);
 568                 }
 569                 while(flash_fmc & FMC_MERASE);
 570
 571                 /* if device has > 128k, then second erase cycle is needed */
 572                 if(stellaris_info->num_pages * stellaris_info->pagesize > 0x20000)
 573                 {
 574                         target_write_u32(target, FLASH_FMA, 0x20000);
 575                         target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
 576                         /* Wait until erase complete */
 577                         do
 578                         {
 579                                 target_read_u32(target, FLASH_FMC, &flash_fmc);
 580                         }
 581                         while(flash_fmc & FMC_MERASE);
 582                 }
 583
 584                 return ERROR_OK;
 585         }
 586
 587         for (banknr=first;banknr<=last;banknr++)
 588         {
 589                 /* Address is first word in page */
 590                 target_write_u32(target, FLASH_FMA, banknr*stellaris_info->pagesize);
 591                 /* Write erase command */
 592                 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_ERASE);
 593                 /* Wait until erase complete */
 594                 do
 595                 {
 596                         target_read_u32(target, FLASH_FMC, &flash_fmc);
 597                 }
 598                 while(flash_fmc & FMC_ERASE);
 599
 600                 /* Check acess violations */
 601                 target_read_u32(target, FLASH_CRIS, &flash_cris);
 602                 if(flash_cris & (AMASK))
 603                 {
 604                         LOG_WARNING("Error erasing flash page %i,  flash_cris 0x%x", banknr, flash_cris);
 605                         target_write_u32(target, FLASH_CRIS, 0);
 606                         return ERROR_FLASH_OPERATION_FAILED;
 607                 }
 608
 609                 bank->sectors[banknr].is_erased = 1;
 610         }
 611
 612         return ERROR_OK;
 613 }
 614
 615 int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last)
 616 {
 617         u32 fmppe, flash_fmc, flash_cris;
 618         int lockregion;
 619
 620         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
 621         target_t *target = bank->target;
 622
 623         if (bank->target->state != TARGET_HALTED)
 624         {
 625                 return ERROR_TARGET_NOT_HALTED;
 626         }
 627
 628         if ((first < 0) || (last < first) || (last >= stellaris_info->num_lockbits))
 629         {
 630                 return ERROR_FLASH_SECTOR_INVALID;
 631         }
 632
 633         if (stellaris_info->did1 == 0)
 634         {
 635                 stellaris_read_part_info(bank);
 636         }
 637
 638         if (stellaris_info->did1 == 0)
 639         {
 640                 LOG_WARNING("Cannot identify target as an Stellaris MCU");
 641                 return ERROR_FLASH_OPERATION_FAILED;
 642         }
 643
 644         /* Configure the flash controller timing */
 645         stellaris_read_clock_info(bank);
 646         stellaris_set_flash_mode(bank,0);
 647
 648         fmppe = stellaris_info->lockbits;
 649         for (lockregion=first;lockregion<=last;lockregion++)
 650         {
 651                 if (set)
 652                          fmppe &= ~(1<<lockregion);
 653                 else
 654                          fmppe |= (1<<lockregion);
 655         }
 656
 657         /* Clear and disable flash programming interrupts */
 658         target_write_u32(target, FLASH_CIM, 0);
 659         target_write_u32(target, FLASH_MISC, PMISC|AMISC);
 660
 661         LOG_DEBUG("fmppe 0x%x",fmppe);
 662         target_write_u32(target, SCB_BASE|FMPPE, fmppe);
 663         /* Commit FMPPE */
 664         target_write_u32(target, FLASH_FMA, 1);
 665         /* Write commit command */
 666         /* TODO safety check, sice this cannot be undone */
 667         LOG_WARNING("Flash protection cannot be removed once commited, commit is NOT executed !");
 668         /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
 669         /* Wait until erase complete */
 670         do
 671         {
 672                 target_read_u32(target, FLASH_FMC, &flash_fmc);
 673         }
 674         while(flash_fmc & FMC_COMT);
 675
 676         /* Check acess violations */
 677         target_read_u32(target, FLASH_CRIS, &flash_cris);
 678         if(flash_cris & (AMASK))
 679         {
 680                 LOG_WARNING("Error setting flash page protection,  flash_cris 0x%x", flash_cris);
 681                 target_write_u32(target, FLASH_CRIS, 0);
 682                 return ERROR_FLASH_OPERATION_FAILED;
 683         }
 684
 685         target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits);
 686
 687         return ERROR_OK;
 688 }
 689
 690 u8 stellaris_write_code[] =
 691 {
 692 /*
 693         Call with :
 694         r0 = buffer address
 695         r1 = destination address
 696         r2 = bytecount (in) - endaddr (work)
 697
 698         Used registers:
 699         r3 = pFLASH_CTRL_BASE
 700         r4 = FLASHWRITECMD
 701         r5 = #1
 702         r6 = bytes written
 703         r7 = temp reg
 704 */
 705         0x07,0x4B,                      /* ldr r3,pFLASH_CTRL_BASE */
 706         0x08,0x4C,                      /* ldr r4,FLASHWRITECMD */
 707         0x01,0x25,                      /* movs r5, 1 */
 708         0x00,0x26,                      /* movs r6, #0 */
 709 /* mainloop: */
 710         0x19,0x60,                      /* str  r1, [r3, #0] */
 711         0x87,0x59,                      /* ldr  r7, [r0, r6] */
 712         0x5F,0x60,                      /* str  r7, [r3, #4] */
 713         0x9C,0x60,                      /* str  r4, [r3, #8] */
 714 /* waitloop: */
 715         0x9F,0x68,                      /* ldr  r7, [r3, #8] */
 716         0x2F,0x42,                      /* tst  r7, r5 */
 717         0xFC,0xD1,                      /* bne  waitloop */
 718         0x04,0x31,                      /* adds r1, r1, #4 */
 719         0x04,0x36,                      /* adds r6, r6, #4 */
 720         0x96,0x42,                      /* cmp  r6, r2 */
 721         0xF4,0xD1,                      /* bne  mainloop */
 722                                                 /* exit: */
 723         0xFE,0xE7,                      /* b exit */
 724 /* pFLASH_CTRL_BASE: */
 725         0x00,0xD0,0x0F,0x40,    /* .word        0x400FD000 */
 726 /* FLASHWRITECMD: */
 727         0x01,0x00,0x42,0xA4     /* .word        0xA4420001 */
 728 };
 729
 730 int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 wcount)
 731 {
 732         target_t *target = bank->target;
 733         u32 buffer_size = 8192;
 734         working_area_t *source;
 735         working_area_t *write_algorithm;
 736         u32 address = bank->base + offset;
 737         reg_param_t reg_params[8];
 738         armv7m_algorithm_t armv7m_info;
 739         int retval;
 740
 741         LOG_DEBUG("(bank=%p buffer=%p offset=%08X wcount=%08X)",
 742                         bank, buffer, offset, wcount);
 743
 744         /* flash write code */
 745         if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)
 746                 {
 747                         LOG_WARNING("no working area available, can't do block memory writes");
 748                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 749                 };
 750
 751         target_write_buffer(target, write_algorithm->address, sizeof(stellaris_write_code), stellaris_write_code);
 752
 753         /* memory buffer */
 754         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
 755         {
 756                 LOG_DEBUG("called target_alloc_working_area(target=%p buffer_size=%08X source=%p)",
 757                                 target, buffer_size, source);
 758                 buffer_size /= 2;
 759                 if (buffer_size <= 256)
 760                 {
 761                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
 762                         if (write_algorithm)
 763                                 target_free_working_area(target, write_algorithm);
 764
 765                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 766                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 767                 }
 768         };
 769
 770         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 771         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 772
 773         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 774         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 775         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 776         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
 777         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
 778         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
 779         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
 780         init_reg_param(&reg_params[7], "r7", 32, PARAM_OUT);
 781
 782         while (wcount > 0)
 783         {
 784                 u32 thisrun_count = (wcount > (buffer_size / 4)) ? (buffer_size / 4) : wcount;
 785
 786                 target_write_buffer(target, source->address, thisrun_count * 4, buffer);
 787
 788                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 789                 buf_set_u32(reg_params[1].value, 0, 32, address);
 790                 buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
 791                 LOG_WARNING("Algorithm flash write  %i words to 0x%x, %i remaining",thisrun_count,address, wcount);
 792                 LOG_DEBUG("Algorithm flash write  %i words to 0x%x, %i remaining",thisrun_count,address, wcount);
 793                 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)
 794                 {
 795                         LOG_ERROR("error executing stellaris flash write algorithm");
 796                         target_free_working_area(target, source);
 797                         destroy_reg_param(&reg_params[0]);
 798                         destroy_reg_param(&reg_params[1]);
 799                         destroy_reg_param(&reg_params[2]);
 800                         return ERROR_FLASH_OPERATION_FAILED;
 801                 }
 802
 803                 buffer += thisrun_count * 4;
 804                 address += thisrun_count * 4;
 805                 wcount -= thisrun_count;
 806         }
 807
 808
 809         target_free_working_area(target, write_algorithm);
 810         target_free_working_area(target, source);
 811
 812         destroy_reg_param(&reg_params[0]);
 813         destroy_reg_param(&reg_params[1]);
 814         destroy_reg_param(&reg_params[2]);
 815         destroy_reg_param(&reg_params[3]);
 816         destroy_reg_param(&reg_params[4]);
 817         destroy_reg_param(&reg_params[5]);
 818         destroy_reg_param(&reg_params[6]);
 819         destroy_reg_param(&reg_params[7]);
 820
 821         return ERROR_OK;
 822 }
 823
 824 int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 825 {
 826         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
 827         target_t *target = bank->target;
 828         u32 address = offset;
 829         u32 flash_cris,flash_fmc;
 830         u32 retval;
 831
 832         if (bank->target->state != TARGET_HALTED)
 833         {
 834                 return ERROR_TARGET_NOT_HALTED;
 835         }
 836
 837         LOG_DEBUG("(bank=%p buffer=%p offset=%08X count=%08X)",
 838                         bank, buffer, offset, count);
 839
 840         if (stellaris_info->did1 == 0)
 841         {
 842                 stellaris_read_part_info(bank);
 843         }
 844
 845         if (stellaris_info->did1 == 0)
 846         {
 847                 LOG_WARNING("Cannot identify target as a Stellaris processor");
 848                 return ERROR_FLASH_OPERATION_FAILED;
 849         }
 850
 851         if((offset & 3) || (count & 3))
 852         {
 853                 LOG_WARNING("offset size must be word aligned");
 854                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 855         }
 856
 857         if (offset + count > bank->size)
 858                 return ERROR_FLASH_DST_OUT_OF_BANK;
 859
 860         /* Configure the flash controller timing */
 861         stellaris_read_clock_info(bank);
 862         stellaris_set_flash_mode(bank,0);
 863
 864
 865         /* Clear and disable flash programming interrupts */
 866         target_write_u32(target, FLASH_CIM, 0);
 867         target_write_u32(target, FLASH_MISC, PMISC|AMISC);
 868
 869         /* multiple words to be programmed? */
 870         if (count > 0)
 871         {
 872                 /* try using a block write */
 873                 if ((retval = stellaris_write_block(bank, buffer, offset, count/4)) != ERROR_OK)
 874                 {
 875                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 876                         {
 877                                 /* if block write failed (no sufficient working area),
 878                                  * we use normal (slow) single dword accesses */
 879                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 880                         }
 881                         else if (retval == ERROR_FLASH_OPERATION_FAILED)
 882                         {
 883                                 /* if an error occured, we examine the reason, and quit */
 884                                 target_read_u32(target, FLASH_CRIS, &flash_cris);
 885
 886                                 LOG_ERROR("flash writing failed with CRIS: 0x%x", flash_cris);
 887                                 return ERROR_FLASH_OPERATION_FAILED;
 888                         }
 889                 }
 890                 else
 891                 {
 892                         buffer += count * 4;
 893                         address += count * 4;
 894                         count = 0;
 895                 }
 896         }
 897
 898         while(count>0)
 899         {
 900                 if (!(address&0xff)) LOG_DEBUG("0x%x",address);
 901                 /* Program one word */
 902                 target_write_u32(target, FLASH_FMA, address);
 903                 target_write_buffer(target, FLASH_FMD, 4, buffer);
 904                 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
 905                 /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
 906                 /* Wait until write complete */
 907                 do
 908                 {
 909                         target_read_u32(target, FLASH_FMC, &flash_fmc);
 910                 }
 911                 while(flash_fmc & FMC_WRITE);
 912                 buffer += 4;
 913                 address += 4;
 914                 count -= 4;
 915         }
 916         /* Check acess violations */
 917         target_read_u32(target, FLASH_CRIS, &flash_cris);
 918         if(flash_cris & (AMASK))
 919         {
 920                 LOG_DEBUG("flash_cris 0x%x", flash_cris);
 921                 return ERROR_FLASH_OPERATION_FAILED;
 922         }
 923         return ERROR_OK;
 924 }
 925
 926 int stellaris_probe(struct flash_bank_s *bank)
 927 {
 928         /* we can't probe on an stellaris
 929          * if this is an stellaris, it has the configured flash
 930          */
 931
 932         if (bank->target->state != TARGET_HALTED)
 933         {
 934                 return ERROR_TARGET_NOT_HALTED;
 935         }
 936
 937         /* stellaris_read_part_info() already takes care about error checking and reporting */
 938         return stellaris_read_part_info(bank);
 939 }
 940
 941 int stellaris_auto_probe(struct flash_bank_s *bank)
 942 {
 943         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
 944         if (stellaris_info->did1)
 945                 return ERROR_OK;
 946         return stellaris_probe(bank);
 947 }