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   1 /***************************************************************************\r
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *\r
   3  *   lundin@mlu.mine.nu                                                        *\r
   4  *                                                                                                             *\r
   5  *   This program is free software; you can redistribute it and/or modify  *\r
   6  *   it under the terms of the GNU General Public License as published by  *\r
   7  *   the Free Software Foundation; either version 2 of the License, or     *\r
   8  *   (at your option) any later version.                                   *\r
   9  *                                                                         *\r
  10  *   This program is distributed in the hope that it will be useful,       *\r
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *\r
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *\r
  13  *   GNU General Public License for more details.                          *\r
  14  *                                                                         *\r
  15  *   You should have received a copy of the GNU General Public License     *\r
  16  *   along with this program; if not, write to the                         *\r
  17  *   Free Software Foundation, Inc.,                                       *\r
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *\r
  19  ***************************************************************************/\r
  20 \r
  21 /***************************************************************************\r
  22 * STELLARIS is tested on LM3S811\r
  23 * \r
  24 *\r
  25 *\r
  26  ***************************************************************************/\r
  27 #ifdef HAVE_CONFIG_H\r
  28 #include "config.h"\r
  29 #endif\r
  30 \r
  31 #include "replacements.h"\r
  32 \r
  33 #include "stellaris.h"\r
  34 #include "cortex_m3.h"\r
  35 \r
  36 #include "flash.h"\r
  37 #include "target.h"\r
  38 #include "log.h"\r
  39 #include "binarybuffer.h"\r
  40 #include "types.h"\r
  41 \r
  42 #include <stdlib.h>\r
  43 #include <string.h>\r
  44 #include <unistd.h>\r
  45 \r
  46 #define DID0_VER(did0) ((did0>>28)&0x07)\r
  47 int stellaris_register_commands(struct command_context_s *cmd_ctx);\r
  48 int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);\r
  49 int stellaris_erase(struct flash_bank_s *bank, int first, int last);\r
  50 int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last);\r
  51 int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);\r
  52 int stellaris_auto_probe(struct flash_bank_s *bank);\r
  53 int stellaris_probe(struct flash_bank_s *bank);\r
  54 int stellaris_erase_check(struct flash_bank_s *bank);\r
  55 int stellaris_protect_check(struct flash_bank_s *bank);\r
  56 int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size);\r
  57 \r
  58 int stellaris_read_part_info(struct flash_bank_s *bank);\r
  59 u32 stellaris_get_flash_status(flash_bank_t *bank);\r
  60 void stellaris_set_flash_mode(flash_bank_t *bank,int mode);\r
  61 u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);\r
  62 \r
  63 int stellaris_read_part_info(struct flash_bank_s *bank);\r
  64 \r
  65 flash_driver_t stellaris_flash =\r
  66 {\r
  67         .name = "stellaris",\r
  68         .register_commands = stellaris_register_commands,\r
  69         .flash_bank_command = stellaris_flash_bank_command,\r
  70         .erase = stellaris_erase,\r
  71         .protect = stellaris_protect,\r
  72         .write = stellaris_write,\r
  73         .probe = stellaris_probe,\r
  74         .auto_probe = stellaris_auto_probe,\r
  75         .erase_check = stellaris_erase_check,\r
  76         .protect_check = stellaris_protect_check,\r
  77         .info = stellaris_info\r
  78 };\r
  79 \r
  80 \r
  81 struct {\r
  82         u32 partno;\r
  83     char *partname;\r
  84 }       StellarisParts[] =\r
  85 {\r
  86         {0x01,"LM3S101"},\r
  87         {0x02,"LM3S102"},\r
  88         {0x19,"LM3S300"},\r
  89         {0x11,"LM3S301"},\r
  90         {0x12,"LM3S310"},\r
  91         {0x1A,"LM3S308"},\r
  92         {0x13,"LM3S315"},\r
  93         {0x14,"LM3S316"},\r
  94         {0x17,"LM3S317"},\r
  95         {0x18,"LM3S318"},\r
  96         {0x15,"LM3S328"},\r
  97         {0x2A,"LM3S600"},\r
  98         {0x21,"LM3S601"},\r
  99         {0x2B,"LM3S608"},\r
 100         {0x22,"LM3S610"},\r
 101         {0x23,"LM3S611"},\r
 102         {0x24,"LM3S612"},\r
 103         {0x25,"LM3S613"},\r
 104         {0x26,"LM3S615"},\r
 105         {0x28,"LM3S617"},\r
 106         {0x29,"LM3S618"},\r
 107         {0x27,"LM3S628"},\r
 108         {0x38,"LM3S800"},\r
 109         {0x31,"LM3S801"},\r
 110         {0x39,"LM3S808"},\r
 111         {0x32,"LM3S811"},\r
 112         {0x33,"LM3S812"},\r
 113         {0x34,"LM3S815"},\r
 114         {0x36,"LM3S817"},\r
 115         {0x37,"LM3S818"},\r
 116         {0x35,"LM3S828"},\r
 117         {0x51,"LM3S2110"},\r
 118         {0x52,"LM3S2739"},\r
 119         {0x53,"LM3S2651"},\r
 120         {0x54,"LM3S2939"},\r
 121         {0x55,"LM3S2965"},\r
 122         {0x56,"LM3S2432"},\r
 123         {0x57,"LM3S2620"},\r
 124         {0x58,"LM3S2950"},\r
 125         {0x59,"LM3S2412"},\r
 126         {0x5A,"LM3S2533"},\r
 127         {0x61,"LM3S8630"},\r
 128         {0x62,"LM3S8970"},\r
 129         {0x63,"LM3S8730"},\r
 130         {0x64,"LM3S8530"},\r
 131         {0x65,"LM3S8930"},\r
 132         {0x71,"LM3S6610"},\r
 133         {0x72,"LM3S6950"},\r
 134         {0x73,"LM3S6965"},\r
 135         {0x74,"LM3S6110"},\r
 136         {0x75,"LM3S6432"},\r
 137         {0x76,"LM3S6537"},\r
 138         {0x77,"LM3S6753"},\r
 139         {0x78,"LM3S6952"},\r
 140         {0x82,"LM3S6422"},\r
 141         {0x83,"LM3S6633"},\r
 142         {0x84,"LM3S2139"},\r
 143         {0x85,"LM3S2637"},\r
 144         {0x86,"LM3S8738"},\r
 145         {0x88,"LM3S8938"},\r
 146         {0x89,"LM3S6938"},\r
 147         {0x8B,"LM3S6637"},\r
 148         {0x8C,"LM3S8933"},\r
 149         {0x8D,"LM3S8733"},\r
 150         {0x8E,"LM3S8538"},\r
 151         {0x8F,"LM3S2948"},\r
 152         {0xA1,"LM3S6100"},\r
 153         {0xA2,"LM3S2410"},\r
 154         {0xA3,"LM3S6730"},\r
 155         {0xA4,"LM3S2730"},\r
 156         {0xA5,"LM3S6420"},\r
 157         {0xA6,"LM3S8962"},\r
 158         {0xB3,"LM3S1635"},\r
 159         {0xB4,"LM3S1850"},\r
 160         {0xB5,"LM3S1960"},\r
 161         {0xB7,"LM3S1937"},\r
 162         {0xB8,"LM3S1968"},\r
 163         {0xB9,"LM3S1751"},\r
 164         {0xBA,"LM3S1439"},\r
 165         {0xBB,"LM3S1512"},\r
 166         {0xBC,"LM3S1435"},\r
 167         {0xBD,"LM3S1637"},\r
 168         {0xBE,"LM3S1958"},\r
 169         {0xBF,"LM3S1110"},\r
 170         {0xC0,"LM3S1620"},\r
 171         {0xC1,"LM3S1150"},\r
 172         {0xC2,"LM3S1165"},\r
 173         {0xC3,"LM3S1133"},\r
 174         {0xC4,"LM3S1162"},\r
 175         {0xC5,"LM3S1138"},\r
 176         {0xC6,"LM3S1332"},\r
 177         {0xC7,"LM3S1538"},\r
 178         {0xD0,"LM3S6815"},\r
 179         {0xD1,"LM3S6816"},\r
 180         {0xD2,"LM3S6915"},\r
 181         {0xD3,"LM3S6916"},\r
 182         {0xD4,"LM3S2016"},\r
 183         {0xD5,"LM3S1615"},\r
 184         {0xD6,"LM3S1616"},\r
 185         {0xD7,"LM3S8971"},\r
 186         {0xD8,"LM3S1108"},\r
 187         {0xD9,"LM3S1101"},\r
 188         {0xDA,"LM3S1608"},\r
 189         {0xDB,"LM3S1601"},\r
 190         {0xDC,"LM3S1918"},\r
 191         {0xDD,"LM3S1911"},\r
 192         {0xDE,"LM3S2108"},\r
 193         {0xDF,"LM3S2101"},\r
 194         {0xE0,"LM3S2608"},\r
 195         {0xE1,"LM3S2601"},\r
 196         {0xE2,"LM3S2918"},\r
 197         {0xE3,"LM3S2911"},\r
 198         {0xE4,"LM3S6118"},\r
 199         {0xE5,"LM3S6111"},\r
 200         {0xE6,"LM3S6618"},\r
 201         {0xE7,"LM3S6611"},\r
 202         {0xE8,"LM3S6918"},\r
 203         {0xE9,"LM3S6911"},\r
 204         {0,"Unknown part"}\r
 205 };\r
 206 \r
 207 char * StellarisClassname[2] =\r
 208 {\r
 209         "Sandstorm",\r
 210         "Fury"\r
 211 };\r
 212 \r
 213 /***************************************************************************\r
 214 *       openocd command interface                                              *\r
 215 ***************************************************************************/\r
 216 \r
 217 /* flash_bank stellaris <base> <size> 0 0 <target#>\r
 218  */\r
 219 int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)\r
 220 {\r
 221         stellaris_flash_bank_t *stellaris_info;\r
 222         \r
 223         if (argc < 6)\r
 224         {\r
 225                 WARNING("incomplete flash_bank stellaris configuration");\r
 226                 return ERROR_FLASH_BANK_INVALID;\r
 227         }\r
 228         \r
 229         stellaris_info = calloc(sizeof(stellaris_flash_bank_t),1);\r
 230         bank->base = 0x0;\r
 231         bank->driver_priv = stellaris_info;\r
 232         \r
 233         stellaris_info->target_name = "Unknown target";\r
 234         \r
 235         /* part wasn't probed for info yet */\r
 236         stellaris_info->did1 = 0;\r
 237         \r
 238         /* TODO Use an optional main oscillator clock rate in kHz from arg[6] */ \r
 239         return ERROR_OK;\r
 240 }\r
 241 \r
 242 int stellaris_register_commands(struct command_context_s *cmd_ctx)\r
 243 {\r
 244 /*\r
 245         command_t *stellaris_cmd = register_command(cmd_ctx, NULL, "stellaris", NULL, COMMAND_ANY, NULL);\r
 246         register_command(cmd_ctx, stellaris_cmd, "gpnvm", stellaris_handle_gpnvm_command, COMMAND_EXEC,\r
 247                         "stellaris gpnvm <num> <bit> set|clear, set or clear stellaris gpnvm bit");\r
 248 */\r
 249         return ERROR_OK;\r
 250 }\r
 251 \r
 252 int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)\r
 253 {\r
 254         int printed, device_class;\r
 255         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 256         \r
 257         stellaris_read_part_info(bank);\r
 258 \r
 259         if (stellaris_info->did1 == 0)\r
 260         {\r
 261                 printed = snprintf(buf, buf_size, "Cannot identify target as a Stellaris\n");\r
 262                 buf += printed;\r
 263                 buf_size -= printed;\r
 264                 return ERROR_FLASH_OPERATION_FAILED;\r
 265         }\r
 266         \r
 267         if (DID0_VER(stellaris_info->did0)>0)\r
 268         {\r
 269                 device_class = (stellaris_info->did0>>16)&0xFF;\r
 270         }\r
 271         else\r
 272         {\r
 273                 device_class = 0;\r
 274         }       \r
 275     printed = snprintf(buf, buf_size, "\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n",\r
 276          device_class, StellarisClassname[device_class], stellaris_info->target_name,\r
 277          'A' + (stellaris_info->did0>>8)&0xFF, (stellaris_info->did0)&0xFF);\r
 278         buf += printed;\r
 279         buf_size -= printed;\r
 280 \r
 281         printed = snprintf(buf, buf_size, "did1: 0x%8.8x, arch: 0x%4.4x, eproc: %s, ramsize:%ik,  flashsize: %ik\n", \r
 282          stellaris_info->did1, stellaris_info->did1, "ARMV7M", (1+(stellaris_info->dc0>>16)&0xFFFF)/4, (1+stellaris_info->dc0&0xFFFF)*2);\r
 283         buf += printed;\r
 284         buf_size -= printed;\r
 285 \r
 286         printed = snprintf(buf, buf_size, "master clock(estimated): %ikHz,  rcc is 0x%x \n", stellaris_info->mck_freq / 1000, stellaris_info->rcc);\r
 287         buf += printed;\r
 288         buf_size -= printed;\r
 289 \r
 290         if (stellaris_info->num_lockbits>0) {           \r
 291                 printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", stellaris_info->pagesize, stellaris_info->num_lockbits, stellaris_info->lockbits,stellaris_info->num_pages/stellaris_info->num_lockbits);\r
 292                 buf += printed;\r
 293                 buf_size -= printed;\r
 294         }\r
 295         return ERROR_OK;\r
 296 }\r
 297 \r
 298 /***************************************************************************\r
 299 *       chip identification and status                                         *\r
 300 ***************************************************************************/\r
 301 \r
 302 u32 stellaris_get_flash_status(flash_bank_t *bank)\r
 303 {\r
 304         target_t *target = bank->target;\r
 305         u32 fmc;\r
 306         \r
 307         target_read_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, &fmc);\r
 308         \r
 309         return fmc;\r
 310 }\r
 311 \r
 312 /** Read clock configuration and set stellaris_info->usec_clocks*/\r
 313  \r
 314 void stellaris_read_clock_info(flash_bank_t *bank)\r
 315 {\r
 316         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 317         target_t *target = bank->target;\r
 318         u32 rcc, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;\r
 319         unsigned long mainfreq;\r
 320 \r
 321         target_read_u32(target, SCB_BASE|RCC, &rcc);\r
 322         DEBUG("Stellaris RCC %x",rcc);\r
 323         target_read_u32(target, SCB_BASE|PLLCFG, &pllcfg);\r
 324         DEBUG("Stellaris PLLCFG %x",pllcfg);\r
 325         stellaris_info->rcc = rcc;\r
 326         \r
 327         sysdiv = (rcc>>23)&0xF;\r
 328         usesysdiv = (rcc>>22)&0x1;\r
 329         bypass = (rcc>>11)&0x1;\r
 330         oscsrc = (rcc>>4)&0x3;\r
 331         /* xtal = (rcc>>6)&0xF; */\r
 332         switch (oscsrc)\r
 333         {\r
 334                 case 0:\r
 335                         mainfreq = 6000000;  /* Default xtal */\r
 336                         break;\r
 337                 case 1:\r
 338                         mainfreq = 22500000; /* Internal osc. 15 MHz +- 50% */\r
 339                         break;\r
 340                 case 2:\r
 341                         mainfreq = 5625000;  /* Internal osc. / 4 */\r
 342                         break;\r
 343                 case 3:\r
 344                         WARNING("Invalid oscsrc (3) in rcc register");\r
 345                         mainfreq = 6000000;\r
 346                         break;\r
 347         }\r
 348         \r
 349         if (!bypass)\r
 350                 mainfreq = 200000000; /* PLL out frec */\r
 351                 \r
 352         if (usesysdiv)\r
 353                 stellaris_info->mck_freq = mainfreq/(1+sysdiv);\r
 354         else\r
 355                 stellaris_info->mck_freq = mainfreq;\r
 356         \r
 357         /* Forget old flash timing */\r
 358        stellaris_set_flash_mode(bank,0);\r
 359 }\r
 360 \r
 361 /* Setup the timimg registers */\r
 362 void stellaris_set_flash_mode(flash_bank_t *bank,int mode)\r
 363 {\r
 364         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 365         target_t *target = bank->target;\r
 366 \r
 367         u32 usecrl = (stellaris_info->mck_freq/1000000ul-1);\r
 368         DEBUG("usecrl = %i",usecrl);    \r
 369         target_write_u32(target, SCB_BASE|USECRL , usecrl);\r
 370         \r
 371 }\r
 372 \r
 373 u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)\r
 374 {\r
 375         u32 status;\r
 376         \r
 377         /* Stellaris waits for cmdbit to clear */\r
 378         while (((status = stellaris_get_flash_status(bank)) & waitbits) && (timeout-- > 0))\r
 379         {\r
 380                 DEBUG("status: 0x%x", status);\r
 381                 usleep(1000);\r
 382         }\r
 383         \r
 384         /* Flash errors are reflected in the FLASH_CRIS register */\r
 385 \r
 386         return status;\r
 387 }\r
 388 \r
 389 \r
 390 /* Send one command to the flash controller */\r
 391 int stellaris_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen) \r
 392 {\r
 393         u32 fmc;\r
 394 //      stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 395         target_t *target = bank->target;\r
 396 \r
 397         fmc = FMC_WRKEY | cmd; \r
 398         target_write_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, fmc);\r
 399         DEBUG("Flash command: 0x%x", fmc);\r
 400 \r
 401         if (stellaris_wait_status_busy(bank, cmd, 100)) \r
 402         {\r
 403                 return ERROR_FLASH_OPERATION_FAILED;\r
 404         }               \r
 405 \r
 406         return ERROR_OK;\r
 407 }\r
 408 \r
 409 /* Read device id register, main clock frequency register and fill in driver info structure */\r
 410 int stellaris_read_part_info(struct flash_bank_s *bank)\r
 411 {\r
 412         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 413         target_t *target = bank->target;\r
 414     u32 did0,did1, ver, fam, status;\r
 415         int i;\r
 416         \r
 417         /* Read and parse chip identification register */\r
 418         target_read_u32(target, SCB_BASE|DID0, &did0);\r
 419         target_read_u32(target, SCB_BASE|DID1, &did1);\r
 420         target_read_u32(target, SCB_BASE|DC0, &stellaris_info->dc0);\r
 421         target_read_u32(target, SCB_BASE|DC1, &stellaris_info->dc1);\r
 422         DEBUG("did0 0x%x, did1 0x%x, dc0 0x%x, dc1 0x%x",did0, did1, stellaris_info->dc0,stellaris_info->dc1);\r
 423 \r
 424     ver = did0 >> 28;\r
 425     if((ver != 0) && (ver != 1))\r
 426         {\r
 427         WARNING("Unknown did0 version, cannot identify target");\r
 428                 return ERROR_FLASH_OPERATION_FAILED;    \r
 429         }\r
 430 \r
 431     ver = did1 >> 28;\r
 432     fam = (did1 >> 24) & 0xF;\r
 433     if(((ver != 0) && (ver != 1)) || (fam != 0))\r
 434         {\r
 435         WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris");\r
 436         }\r
 437 \r
 438         if (did1 == 0)\r
 439         {\r
 440                 WARNING("Cannot identify target as a Stellaris");\r
 441                 return ERROR_FLASH_OPERATION_FAILED;\r
 442         }\r
 443         \r
 444         for (i=0;StellarisParts[i].partno;i++)\r
 445         {\r
 446                 if (StellarisParts[i].partno==((did1>>16)&0xFF))\r
 447                         break;\r
 448         }\r
 449         \r
 450         stellaris_info->target_name = StellarisParts[i].partname;\r
 451         \r
 452         stellaris_info->did0 = did0;\r
 453         stellaris_info->did1 = did1;\r
 454 \r
 455         stellaris_info->num_lockbits = 1+stellaris_info->dc0&0xFFFF;\r
 456         stellaris_info->num_pages = 2*(1+stellaris_info->dc0&0xFFFF);\r
 457         stellaris_info->pagesize = 1024;\r
 458         bank->size = 1024*stellaris_info->num_pages;\r
 459         stellaris_info->pages_in_lockregion = 2;\r
 460         target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits);\r
 461 \r
 462         // Read main and master clock freqency register \r
 463         stellaris_read_clock_info(bank);\r
 464         \r
 465         status = stellaris_get_flash_status(bank);\r
 466         \r
 467         return ERROR_OK;\r
 468 }\r
 469 \r
 470 /***************************************************************************\r
 471 *       flash operations                                         *\r
 472 ***************************************************************************/\r
 473 \r
 474 int stellaris_erase_check(struct flash_bank_s *bank)\r
 475 {\r
 476         /* \r
 477         \r
 478         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 479         target_t *target = bank->target;\r
 480         int i;\r
 481         \r
 482         */\r
 483         \r
 484         return ERROR_OK;\r
 485 }\r
 486 \r
 487 int stellaris_protect_check(struct flash_bank_s *bank)\r
 488 {\r
 489         u32 status;\r
 490         \r
 491         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 492 \r
 493         if (stellaris_info->did1 == 0)\r
 494         {\r
 495                 stellaris_read_part_info(bank);\r
 496         }\r
 497 \r
 498         if (stellaris_info->did1 == 0)\r
 499         {\r
 500                 WARNING("Cannot identify target as an AT91SAM");\r
 501                 return ERROR_FLASH_OPERATION_FAILED;\r
 502         }\r
 503                 \r
 504         status = stellaris_get_flash_status(bank);\r
 505         stellaris_info->lockbits = status >> 16;\r
 506         \r
 507         return ERROR_OK;\r
 508 }\r
 509 \r
 510 int stellaris_erase(struct flash_bank_s *bank, int first, int last)\r
 511 {\r
 512         int banknr;\r
 513         u32 flash_fmc, flash_cris;\r
 514         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 515         target_t *target = bank->target;\r
 516         \r
 517         if (stellaris_info->did1 == 0)\r
 518         {\r
 519                 stellaris_read_part_info(bank);\r
 520         }\r
 521 \r
 522         if (stellaris_info->did1 == 0)\r
 523         {\r
 524         WARNING("Cannot identify target as Stellaris");\r
 525                 return ERROR_FLASH_OPERATION_FAILED;\r
 526         }       \r
 527         \r
 528         if ((first < 0) || (last < first) || (last >= stellaris_info->num_pages))\r
 529         {\r
 530                 return ERROR_FLASH_SECTOR_INVALID;\r
 531         }\r
 532 \r
 533         /* Configure the flash controller timing */\r
 534         stellaris_read_clock_info(bank);        \r
 535         stellaris_set_flash_mode(bank,0);\r
 536 \r
 537         /* Clear and disable flash programming interrupts */\r
 538         target_write_u32(target, FLASH_CIM, 0);\r
 539         target_write_u32(target, FLASH_MISC, PMISC|AMISC);\r
 540 \r
 541         if ((first == 0) && (last == (stellaris_info->num_pages-1)))\r
 542         {\r
 543         target_write_u32(target, FLASH_FMA, 0);\r
 544                 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);\r
 545                 /* Wait until erase complete */\r
 546                 do\r
 547                 {\r
 548                         target_read_u32(target, FLASH_FMC, &flash_fmc);\r
 549                 }\r
 550                 while(flash_fmc & FMC_MERASE);\r
 551                 \r
 552         /* if device has > 128k, then second erase cycle is needed */\r
 553         if(stellaris_info->num_pages * stellaris_info->pagesize > 0x20000)\r
 554         {\r
 555             target_write_u32(target, FLASH_FMA, 0x20000);\r
 556             target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);\r
 557             /* Wait until erase complete */\r
 558             do\r
 559             {\r
 560                 target_read_u32(target, FLASH_FMC, &flash_fmc);\r
 561             }\r
 562             while(flash_fmc & FMC_MERASE);\r
 563         }\r
 564 \r
 565                 return ERROR_OK;\r
 566         }\r
 567 \r
 568         for (banknr=first;banknr<=last;banknr++)\r
 569         {\r
 570                 /* Address is first word in page */\r
 571                 target_write_u32(target, FLASH_FMA, banknr*stellaris_info->pagesize);\r
 572                 /* Write erase command */\r
 573                 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_ERASE);\r
 574                 /* Wait until erase complete */\r
 575                 do\r
 576                 {\r
 577                         target_read_u32(target, FLASH_FMC, &flash_fmc);\r
 578                 }\r
 579                 while(flash_fmc & FMC_ERASE);\r
 580 \r
 581                 /* Check acess violations */\r
 582                 target_read_u32(target, FLASH_CRIS, &flash_cris);\r
 583                 if(flash_cris & (AMASK))\r
 584                 {\r
 585                         WARNING("Error erasing flash page %i,  flash_cris 0x%x", banknr, flash_cris);\r
 586                         target_write_u32(target, FLASH_CRIS, 0);\r
 587                         return ERROR_FLASH_OPERATION_FAILED;\r
 588                 }\r
 589         }\r
 590 \r
 591         return ERROR_OK;\r
 592 }\r
 593 \r
 594 int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last)\r
 595 {\r
 596         u32 fmppe, flash_fmc, flash_cris;\r
 597         int lockregion;\r
 598         \r
 599         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 600         target_t *target = bank->target;\r
 601         \r
 602         if (bank->target->state != TARGET_HALTED)\r
 603         {\r
 604                 return ERROR_TARGET_NOT_HALTED;\r
 605         }\r
 606         \r
 607         if ((first < 0) || (last < first) || (last >= stellaris_info->num_lockbits))\r
 608         {\r
 609                 return ERROR_FLASH_SECTOR_INVALID;\r
 610         }\r
 611         \r
 612         if (stellaris_info->did1 == 0)\r
 613         {\r
 614                 stellaris_read_part_info(bank);\r
 615         }\r
 616 \r
 617         if (stellaris_info->did1 == 0)\r
 618         {\r
 619                 WARNING("Cannot identify target as an Stellaris MCU");\r
 620                 return ERROR_FLASH_OPERATION_FAILED;\r
 621         }\r
 622         \r
 623         /* Configure the flash controller timing */\r
 624         stellaris_read_clock_info(bank);        \r
 625         stellaris_set_flash_mode(bank,0);\r
 626 \r
 627         fmppe = stellaris_info->lockbits;       \r
 628         for (lockregion=first;lockregion<=last;lockregion++) \r
 629         {\r
 630                 if (set)\r
 631                          fmppe &= ~(1<<lockregion); \r
 632                 else\r
 633                          fmppe |= (1<<lockregion); \r
 634         }\r
 635 \r
 636         /* Clear and disable flash programming interrupts */\r
 637         target_write_u32(target, FLASH_CIM, 0);\r
 638         target_write_u32(target, FLASH_MISC, PMISC|AMISC);\r
 639         \r
 640         DEBUG("fmppe 0x%x",fmppe);\r
 641         target_write_u32(target, SCB_BASE|FMPPE, fmppe);\r
 642         /* Commit FMPPE */\r
 643         target_write_u32(target, FLASH_FMA, 1);\r
 644         /* Write commit command */\r
 645         /* TODO safety check, sice this cannot be undone */\r
 646         WARNING("Flash protection cannot be removed once commited, commit is NOT executed !");\r
 647         /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */\r
 648         /* Wait until erase complete */\r
 649         do\r
 650         {\r
 651                 target_read_u32(target, FLASH_FMC, &flash_fmc);\r
 652         }\r
 653         while(flash_fmc & FMC_COMT);\r
 654 \r
 655         /* Check acess violations */\r
 656         target_read_u32(target, FLASH_CRIS, &flash_cris);\r
 657         if(flash_cris & (AMASK))\r
 658         {\r
 659                 WARNING("Error setting flash page protection,  flash_cris 0x%x", flash_cris);\r
 660                 target_write_u32(target, FLASH_CRIS, 0);\r
 661                 return ERROR_FLASH_OPERATION_FAILED;\r
 662         }\r
 663         \r
 664         target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits);\r
 665                 \r
 666         return ERROR_OK;\r
 667 }\r
 668 \r
 669 u8 stellaris_write_code[] = \r
 670 {\r
 671 /* \r
 672         Call with :     \r
 673         r0 = buffer address\r
 674         r1 = destination address\r
 675         r2 = bytecount (in) - endaddr (work) \r
 676         \r
 677         Used registers: \r
 678         r3 = pFLASH_CTRL_BASE\r
 679         r4 = FLASHWRITECMD\r
 680         r5 = #1\r
 681         r6 = bytes written\r
 682         r7 = temp reg\r
 683 */\r
 684         0x07,0x4B,              /* ldr r3,pFLASH_CTRL_BASE */\r
 685         0x08,0x4C,              /* ldr r4,FLASHWRITECMD */\r
 686         0x01,0x25,              /* movs r5, 1 */\r
 687         0x00,0x26,              /* movs r6, #0 */\r
 688 /* mainloop: */\r
 689         0x19,0x60,              /* str  r1, [r3, #0] */\r
 690         0x87,0x59,              /* ldr  r7, [r0, r6] */\r
 691         0x5F,0x60,              /* str  r7, [r3, #4] */\r
 692         0x9C,0x60,              /* str  r4, [r3, #8] */\r
 693 /* waitloop: */\r
 694         0x9F,0x68,              /* ldr  r7, [r3, #8] */\r
 695         0x2F,0x42,              /* tst  r7, r5 */\r
 696         0xFC,0xD1,              /* bne  waitloop */\r
 697         0x04,0x31,              /* adds r1, r1, #4 */\r
 698         0x04,0x36,              /* adds r6, r6, #4 */\r
 699         0x96,0x42,              /* cmp  r6, r2 */\r
 700         0xF4,0xD1,              /* bne  mainloop */\r
 701         0x00,0xBE,              /* bkpt #0 */\r
 702 /* pFLASH_CTRL_BASE: */\r
 703         0x00,0xD0,0x0F,0x40,    /* .word        0x400FD000 */\r
 704 /* FLASHWRITECMD: */\r
 705         0x01,0x00,0x42,0xA4     /* .word        0xA4420001 */\r
 706 };\r
 707 \r
 708 int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 wcount)\r
 709 {\r
 710 //      stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 711         target_t *target = bank->target;\r
 712         u32 buffer_size = 8192;\r
 713         working_area_t *source;\r
 714         working_area_t *write_algorithm;\r
 715         u32 address = bank->base + offset;\r
 716         reg_param_t reg_params[8];\r
 717         armv7m_algorithm_t armv7m_info;\r
 718         int retval;\r
 719         \r
 720         DEBUG("(bank=%08X buffer=%08X offset=%08X wcount=%08X)",\r
 721                         (unsigned int)bank, (unsigned int)buffer, offset, wcount);\r
 722 \r
 723         /* flash write code */\r
 724         if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)\r
 725                 {\r
 726                         WARNING("no working area available, can't do block memory writes");\r
 727                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;\r
 728                 };\r
 729 \r
 730         target_write_buffer(target, write_algorithm->address, sizeof(stellaris_write_code), stellaris_write_code);\r
 731 \r
 732         /* memory buffer */\r
 733         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)\r
 734         {\r
 735                 DEBUG("called target_alloc_working_area(target=%08X buffer_size=%08X source=%08X)",\r
 736                                 (unsigned int)target, buffer_size, (unsigned int)source); \r
 737                 buffer_size /= 2;\r
 738                 if (buffer_size <= 256)\r
 739                 {\r
 740                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */\r
 741                         if (write_algorithm)\r
 742                                 target_free_working_area(target, write_algorithm);\r
 743                         \r
 744                         WARNING("no large enough working area available, can't do block memory writes");\r
 745                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;\r
 746                 }\r
 747         };\r
 748         \r
 749         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;\r
 750         armv7m_info.core_mode = ARMV7M_MODE_ANY;\r
 751         armv7m_info.core_state = ARMV7M_STATE_THUMB;\r
 752         \r
 753         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);\r
 754         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);\r
 755         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);\r
 756         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);\r
 757         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);\r
 758         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);\r
 759         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);\r
 760         init_reg_param(&reg_params[7], "r7", 32, PARAM_OUT);\r
 761 \r
 762         while (wcount > 0)\r
 763         {\r
 764                 u32 thisrun_count = (wcount > (buffer_size / 4)) ? (buffer_size / 4) : wcount;\r
 765                 \r
 766                 target_write_buffer(target, source->address, thisrun_count * 4, buffer);\r
 767                 \r
 768                 buf_set_u32(reg_params[0].value, 0, 32, source->address);\r
 769                 buf_set_u32(reg_params[1].value, 0, 32, address);\r
 770                 buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);\r
 771                 WARNING("Algorithm flash write  %i words to 0x%x, %i remaining",thisrun_count,address, wcount);\r
 772                 DEBUG("Algorithm flash write  %i words to 0x%x, %i remaining",thisrun_count,address, wcount);\r
 773                 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)\r
 774                 {\r
 775                         ERROR("error executing stellaris flash write algorithm");\r
 776                         target_free_working_area(target, source);\r
 777                         destroy_reg_param(&reg_params[0]);\r
 778                         destroy_reg_param(&reg_params[1]);\r
 779                         destroy_reg_param(&reg_params[2]);\r
 780                         return ERROR_FLASH_OPERATION_FAILED;\r
 781                 }\r
 782         \r
 783                 buffer += thisrun_count * 4;\r
 784                 address += thisrun_count * 4;\r
 785                 wcount -= thisrun_count;\r
 786         }\r
 787         \r
 788 \r
 789         target_free_working_area(target, write_algorithm);\r
 790         target_free_working_area(target, source);\r
 791         \r
 792         destroy_reg_param(&reg_params[0]);\r
 793         destroy_reg_param(&reg_params[1]);\r
 794         destroy_reg_param(&reg_params[2]);\r
 795         destroy_reg_param(&reg_params[3]);\r
 796         destroy_reg_param(&reg_params[4]);\r
 797         destroy_reg_param(&reg_params[5]);\r
 798         destroy_reg_param(&reg_params[6]);\r
 799         destroy_reg_param(&reg_params[7]);\r
 800         \r
 801         return ERROR_OK;\r
 802 }\r
 803 \r
 804 int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)\r
 805 {\r
 806         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 807         target_t *target = bank->target;\r
 808         u32 address = offset;\r
 809         u32 flash_cris,flash_fmc;\r
 810         u32 retval;\r
 811         \r
 812         DEBUG("(bank=%08X buffer=%08X offset=%08X count=%08X)",\r
 813                         (unsigned int)bank, (unsigned int)buffer, offset, count);\r
 814 \r
 815         if (stellaris_info->did1 == 0)\r
 816         {\r
 817                 stellaris_read_part_info(bank);\r
 818         }\r
 819 \r
 820         if (stellaris_info->did1 == 0)\r
 821         {\r
 822                 WARNING("Cannot identify target as a Stellaris processor");\r
 823                 return ERROR_FLASH_OPERATION_FAILED;\r
 824         }\r
 825         \r
 826         if((offset & 3) || (count & 3))\r
 827         {\r
 828                 WARNING("offset size must be word aligned");\r
 829                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;\r
 830         }\r
 831         \r
 832         if (offset + count > bank->size)\r
 833                 return ERROR_FLASH_DST_OUT_OF_BANK;\r
 834 \r
 835         /* Configure the flash controller timing */     \r
 836         stellaris_read_clock_info(bank);        \r
 837         stellaris_set_flash_mode(bank,0);\r
 838 \r
 839         \r
 840         /* Clear and disable flash programming interrupts */\r
 841         target_write_u32(target, FLASH_CIM, 0);\r
 842         target_write_u32(target, FLASH_MISC, PMISC|AMISC);\r
 843 \r
 844         /* multiple words to be programmed? */\r
 845         if (count > 0) \r
 846         {\r
 847                 /* try using a block write */\r
 848                 if ((retval = stellaris_write_block(bank, buffer, offset, count/4)) != ERROR_OK)\r
 849                 {\r
 850                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)\r
 851                         {\r
 852                                 /* if block write failed (no sufficient working area),\r
 853                                  * we use normal (slow) single dword accesses */ \r
 854                                 WARNING("couldn't use block writes, falling back to single memory accesses");\r
 855                         }\r
 856                         else if (retval == ERROR_FLASH_OPERATION_FAILED)\r
 857                         {\r
 858                                 /* if an error occured, we examine the reason, and quit */\r
 859                                 target_read_u32(target, FLASH_CRIS, &flash_cris);\r
 860                                 \r
 861                                 ERROR("flash writing failed with CRIS: 0x%x", flash_cris);\r
 862                                 return ERROR_FLASH_OPERATION_FAILED;\r
 863                         }\r
 864                 }\r
 865                 else\r
 866                 {\r
 867                         buffer += count * 4;\r
 868                         address += count * 4;\r
 869                         count = 0;\r
 870                 }\r
 871         }\r
 872 \r
 873 \r
 874 \r
 875         while(count>0)\r
 876         {\r
 877                 if (!(address&0xff)) DEBUG("0x%x",address);\r
 878                 /* Program one word */\r
 879                 target_write_u32(target, FLASH_FMA, address);\r
 880                 target_write_buffer(target, FLASH_FMD, 4, buffer);\r
 881                 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);\r
 882                 //DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE);\r
 883                 /* Wait until write complete */\r
 884                 do\r
 885                 {\r
 886                         target_read_u32(target, FLASH_FMC, &flash_fmc);\r
 887                 }\r
 888                 while(flash_fmc & FMC_WRITE);\r
 889                 buffer += 4;\r
 890                 address += 4;\r
 891                 count -= 4;\r
 892         }\r
 893         /* Check acess violations */\r
 894         target_read_u32(target, FLASH_CRIS, &flash_cris);\r
 895         if(flash_cris & (AMASK))\r
 896         {\r
 897                 DEBUG("flash_cris 0x%x", flash_cris);\r
 898                 return ERROR_FLASH_OPERATION_FAILED;\r
 899         }\r
 900         return ERROR_OK;\r
 901 }\r
 902 \r
 903 \r
 904 int stellaris_probe(struct flash_bank_s *bank)\r
 905 {\r
 906         /* we can't probe on an stellaris\r
 907          * if this is an stellaris, it has the configured flash\r
 908          */\r
 909         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 910         \r
 911         stellaris_info->probed = 0;\r
 912         \r
 913         if (stellaris_info->did1 == 0)\r
 914         {\r
 915                 stellaris_read_part_info(bank);\r
 916         }\r
 917 \r
 918         if (stellaris_info->did1 == 0)\r
 919         {\r
 920                 WARNING("Cannot identify target as a LMI Stellaris");\r
 921                 return ERROR_FLASH_OPERATION_FAILED;\r
 922         }\r
 923         \r
 924         stellaris_info->probed = 1;\r
 925         \r
 926         return ERROR_OK;\r
 927 }\r
 928 \r
 929 int stellaris_auto_probe(struct flash_bank_s *bank)\r
 930 {\r
 931         stellaris_flash_bank_t *stellaris_info = bank->driver_priv;\r
 932         if (stellaris_info->probed)\r
 933                 return ERROR_OK;\r
 934         return stellaris_probe(bank);\r
 935 }\r