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   1 /***************************************************************************
   2  *   Copyright (C) 2007, 2008 by Ben Dooks                                 *
   3  *   ben@fluff.org                                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20
  21 #ifndef S3C24xx_NAND_H
  22 #define S3C24xx_NAND_H
  23
  24 /*
  25  * S3C24XX Series OpenOCD NAND Flash controller support.
  26  *
  27  * Many thanks to Simtec Electronics for sponsoring this work.
  28  */
  29
  30 #include "nand.h"
  31 #include "s3c24xx_regs_nand.h"
  32
  33 typedef struct s3c24xx_nand_controller_s
  34 {
  35         struct target_s *target;
  36
  37         /* register addresses */
  38         uint32_t                 cmd;
  39         uint32_t                 addr;
  40         uint32_t                 data;
  41         uint32_t                 nfstat;
  42 } s3c24xx_nand_controller_t;
  43
  44 /* Default to using the un-translated NAND register based address */
  45 #undef S3C2410_NFREG
  46 #define S3C2410_NFREG(x) ((x) + 0x4e000000)
  47
  48 s3c24xx_nand_controller_t *s3c24xx_nand_device_command(
  49                         struct command_context_s *cmd_ctx, char *cmd,
  50                         char **args, int argc, struct nand_device_s *nand);
  51
  52 int s3c24xx_register_commands(struct command_context_s *cmd_ctx);
  53
  54 int s3c24xx_reset(struct nand_device_s *nand);
  55
  56 int s3c24xx_command(struct nand_device_s *nand, uint8_t command);
  57 int s3c24xx_address(struct nand_device_s *nand, uint8_t address);
  58
  59 int s3c24xx_write_data(struct nand_device_s *nand, uint16_t data);
  60 int s3c24xx_read_data(struct nand_device_s *nand, void *data);
  61
  62 int s3c24xx_controller_ready(struct nand_device_s *nand, int tout);
  63
  64 #define s3c24xx_write_page NULL
  65 #define s3c24xx_read_page NULL
  66
  67 /* code shared between different controllers */
  68
  69 int s3c2440_nand_ready(struct nand_device_s *nand, int timeout);
  70
  71 int s3c2440_read_block_data(struct nand_device_s *nand,
  72                 uint8_t *data, int data_size);
  73 int s3c2440_write_block_data(struct nand_device_s *nand,
  74                 uint8_t *data, int data_size);
  75
  76 #endif // S3C24xx_NAND_H