The following patches was applied:
[fw/openocd] / src / flash / orion_nand.c
1 /***************************************************************************
2  *   Copyright (C) 2009 by Marvell Semiconductors, Inc.                    *
3  *   Written by Nicolas Pitre <nico at marvell.com>                           *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20
21 /*
22  * NAND controller interface for Marvell Orion/Kirkwood SoCs.
23  */
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "replacements.h"
30 #include "log.h"
31
32 #include <stdlib.h>
33 #include <string.h>
34
35 #include "nand.h"
36 #include "target.h"
37 #include "armv4_5.h"
38 #include "binarybuffer.h"
39
40 typedef struct orion_nand_controller_s
41 {
42         struct target_s *target;
43         working_area_t *copy_area;
44
45         u32             cmd;
46         u32             addr;
47         u32             data;
48 } orion_nand_controller_t;
49
50 #define CHECK_HALTED \
51         do { \
52                 if (target->state != TARGET_HALTED) { \
53                         LOG_ERROR("NAND flash access requires halted target"); \
54                         return ERROR_NAND_OPERATION_FAILED; \
55                 } \
56         } while (0)
57
58 static int orion_nand_command(struct nand_device_s *device, u8 command)
59 {
60         orion_nand_controller_t *hw = device->controller_priv;
61         target_t *target = hw->target;
62
63         CHECK_HALTED;
64         target_write_u8(target, hw->cmd, command);
65         return ERROR_OK;
66 }
67
68 static int orion_nand_address(struct nand_device_s *device, u8 address)
69 {
70         orion_nand_controller_t *hw = device->controller_priv;
71         target_t *target = hw->target;
72
73         CHECK_HALTED;
74         target_write_u8(target, hw->addr, address);
75         return ERROR_OK;
76 }
77
78 static int orion_nand_read(struct nand_device_s *device, void *data)
79 {
80         orion_nand_controller_t *hw = device->controller_priv;
81         target_t *target = hw->target;
82
83         CHECK_HALTED;
84         target_read_u8(target, hw->data, data);
85         return ERROR_OK;
86 }
87
88 static int orion_nand_write(struct nand_device_s *device, u16 data)
89 {
90         orion_nand_controller_t *hw = device->controller_priv;
91         target_t *target = hw->target;
92
93         CHECK_HALTED;
94         target_write_u8(target, hw->data, data);
95         return ERROR_OK;
96 }
97
98 static int orion_nand_slow_block_write(struct nand_device_s *device, u8 *data, int size)
99 {
100         while (size--)
101                 orion_nand_write(device, *data++);
102         return ERROR_OK;
103 }
104
105 static int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size)
106 {
107         orion_nand_controller_t *hw = device->controller_priv;
108         target_t *target = hw->target;
109         armv4_5_algorithm_t algo;
110         reg_param_t reg_params[3];
111         u32 target_buf;
112         int retval;
113
114         static const u32 code[] = {
115                 0xe4d13001,     /* ldrb r3, [r1], #1    */
116                 0xe5c03000,     /* strb r3, [r0]        */
117                 0xe2522001,     /* subs r2, r2, #1      */
118                 0x1afffffb,     /* bne  0               */
119                 0xeafffffe,     /* b    .               */
120         };
121         int code_size = sizeof(code);
122
123         if (!hw->copy_area) {
124                 u8 code_buf[code_size];
125                 int i;
126
127                 /* make sure we have a working area */
128                 if (target_alloc_working_area(target,
129                                               code_size + device->page_size,
130                                               &hw->copy_area) != ERROR_OK)
131                 {
132                         return orion_nand_slow_block_write(device, data, size);
133                 }
134
135                 /* copy target instructions to target endianness */
136                 for (i = 0; i < code_size/4; i++)
137                         target_buffer_set_u32(target, code_buf + i*4, code[i]);
138
139                 /* write code to working area */
140                 retval = target->type->write_memory(target,
141                                         hw->copy_area->address,
142                                         4, code_size/4, code_buf);
143                 if (retval != ERROR_OK)
144                         return retval;
145         }
146
147         /* copy data to target's memory */
148         target_buf = hw->copy_area->address + code_size;
149         retval = target->type->bulk_write_memory(target, target_buf,
150                                                  size/4, data);
151         if (retval == ERROR_OK && size & 3) {
152                 retval = target->type->write_memory(target,
153                                         target_buf + (size & ~3),
154                                         1, size & 3, data + (size & ~3));
155         }
156         if (retval != ERROR_OK)
157                 return retval;
158
159         algo.common_magic = ARMV4_5_COMMON_MAGIC;
160         algo.core_mode = ARMV4_5_MODE_SVC;
161         algo.core_state = ARMV4_5_STATE_ARM;
162
163         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
164         init_reg_param(&reg_params[1], "r1", 32, PARAM_IN);
165         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN);
166
167         buf_set_u32(reg_params[0].value, 0, 32, hw->data);
168         buf_set_u32(reg_params[1].value, 0, 32, target_buf);
169         buf_set_u32(reg_params[2].value, 0, 32, size);
170
171         retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
172                                         hw->copy_area->address,
173                                         hw->copy_area->address + code_size - 4,
174                                         1000, &algo);
175         if (retval != ERROR_OK)
176                 LOG_ERROR("error executing hosted NAND write");
177
178         destroy_reg_param(&reg_params[0]);
179         destroy_reg_param(&reg_params[1]);
180         destroy_reg_param(&reg_params[2]);
181         return retval;
182 }
183
184 static int orion_nand_reset(struct nand_device_s *device)
185 {
186         return orion_nand_command(device, NAND_CMD_RESET);
187 }
188
189 static int orion_nand_controller_ready(struct nand_device_s *device, int timeout)
190 {
191         return 1;
192 }
193
194 static int orion_nand_register_commands(struct command_context_s *cmd_ctx)
195 {
196         return ERROR_OK;
197 }
198
199 int orion_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
200                               char **args, int argc,
201                               struct nand_device_s *device)
202 {
203         orion_nand_controller_t *hw;
204         u32 base;
205         u8 ale, cle;
206
207         if (argc != 3) {
208                 LOG_ERROR("arguments must be: <target_number> <NAND_address>\n");
209                 return ERROR_NAND_DEVICE_INVALID;
210         }
211
212         hw = calloc(1, sizeof(*hw));
213         if (!hw) {
214                 LOG_ERROR("no memory for nand controller\n");
215                 return ERROR_NAND_DEVICE_INVALID;
216         }
217
218         device->controller_priv = hw;
219         hw->target = get_target_by_num(strtoul(args[1], NULL, 0));
220         if (!hw->target) {
221                 LOG_ERROR("no target '%s' configured", args[1]);
222                 free(hw);
223                 return ERROR_NAND_DEVICE_INVALID;
224         }
225
226         base = strtoul(args[2], NULL, 0);
227         cle = 0;
228         ale = 1;
229
230         hw->data = base;
231         hw->cmd = base + (1 << cle);
232         hw->addr = base + (1 << ale);
233
234         return ERROR_OK;
235 }
236
237 static int orion_nand_init(struct nand_device_s *device)
238 {
239         return ERROR_OK;
240 }
241
242 nand_flash_controller_t orion_nand_controller =
243 {
244         .name                   = "orion",
245         .command                = orion_nand_command,
246         .address                = orion_nand_address,
247         .read_data              = orion_nand_read,
248         .write_data             = orion_nand_write,
249         .write_block_data       = orion_nand_fast_block_write,
250         .reset                  = orion_nand_reset,
251         .controller_ready       = orion_nand_controller_ready,
252         .nand_device_command    = orion_nand_device_command,
253         .register_commands      = orion_nand_register_commands,
254         .init                   = orion_nand_init,
255 };
256