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   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Marvell Semiconductors, Inc.                    *
   3  *   Written by Nicolas Pitre <nico at marvell.com>                           *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20
  21 /*
  22  * NAND controller interface for Marvell Orion/Kirkwood SoCs.
  23  */
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "nand.h"
  30 #include "armv4_5.h"
  31 #include "binarybuffer.h"
  32
  33
  34 typedef struct orion_nand_controller_s
  35 {
  36         struct target_s *target;
  37         working_area_t *copy_area;
  38
  39         u32             cmd;
  40         u32             addr;
  41         u32             data;
  42 } orion_nand_controller_t;
  43
  44 #define CHECK_HALTED \
  45         do { \
  46                 if (target->state != TARGET_HALTED) { \
  47                         LOG_ERROR("NAND flash access requires halted target"); \
  48                         return ERROR_NAND_OPERATION_FAILED; \
  49                 } \
  50         } while (0)
  51
  52 static int orion_nand_command(struct nand_device_s *device, uint8_t command)
  53 {
  54         orion_nand_controller_t *hw = device->controller_priv;
  55         target_t *target = hw->target;
  56
  57         CHECK_HALTED;
  58         target_write_u8(target, hw->cmd, command);
  59         return ERROR_OK;
  60 }
  61
  62 static int orion_nand_address(struct nand_device_s *device, uint8_t address)
  63 {
  64         orion_nand_controller_t *hw = device->controller_priv;
  65         target_t *target = hw->target;
  66
  67         CHECK_HALTED;
  68         target_write_u8(target, hw->addr, address);
  69         return ERROR_OK;
  70 }
  71
  72 static int orion_nand_read(struct nand_device_s *device, void *data)
  73 {
  74         orion_nand_controller_t *hw = device->controller_priv;
  75         target_t *target = hw->target;
  76
  77         CHECK_HALTED;
  78         target_read_u8(target, hw->data, data);
  79         return ERROR_OK;
  80 }
  81
  82 static int orion_nand_write(struct nand_device_s *device, uint16_t data)
  83 {
  84         orion_nand_controller_t *hw = device->controller_priv;
  85         target_t *target = hw->target;
  86
  87         CHECK_HALTED;
  88         target_write_u8(target, hw->data, data);
  89         return ERROR_OK;
  90 }
  91
  92 static int orion_nand_slow_block_write(struct nand_device_s *device, uint8_t *data, int size)
  93 {
  94         while (size--)
  95                 orion_nand_write(device, *data++);
  96         return ERROR_OK;
  97 }
  98
  99 static int orion_nand_fast_block_write(struct nand_device_s *device, uint8_t *data, int size)
 100 {
 101         orion_nand_controller_t *hw = device->controller_priv;
 102         target_t *target = hw->target;
 103         armv4_5_algorithm_t algo;
 104         reg_param_t reg_params[3];
 105         u32 target_buf;
 106         int retval;
 107
 108         static const u32 code[] = {
 109                 0xe4d13001,     /* ldrb r3, [r1], #1    */
 110                 0xe5c03000,     /* strb r3, [r0]        */
 111                 0xe2522001,     /* subs r2, r2, #1      */
 112                 0x1afffffb,     /* bne  0               */
 113                 0xeafffffe,     /* b    .               */
 114         };
 115         int code_size = sizeof(code);
 116
 117         if (!hw->copy_area) {
 118                 uint8_t code_buf[code_size];
 119                 int i;
 120
 121                 /* make sure we have a working area */
 122                 if (target_alloc_working_area(target,
 123                                               code_size + device->page_size,
 124                                               &hw->copy_area) != ERROR_OK)
 125                 {
 126                         return orion_nand_slow_block_write(device, data, size);
 127                 }
 128
 129                 /* copy target instructions to target endianness */
 130                 for (i = 0; i < code_size/4; i++)
 131                         target_buffer_set_u32(target, code_buf + i*4, code[i]);
 132
 133                 /* write code to working area */
 134                 retval = target_write_memory(target,
 135                                         hw->copy_area->address,
 136                                         4, code_size/4, code_buf);
 137                 if (retval != ERROR_OK)
 138                         return retval;
 139         }
 140
 141         /* copy data to target's memory */
 142         target_buf = hw->copy_area->address + code_size;
 143         retval = target_bulk_write_memory(target, target_buf, size/4, data);
 144         if (retval == ERROR_OK && size & 3) {
 145                 retval = target_write_memory(target,
 146                                         target_buf + (size & ~3),
 147                                         1, size & 3, data + (size & ~3));
 148         }
 149         if (retval != ERROR_OK)
 150                 return retval;
 151
 152         algo.common_magic = ARMV4_5_COMMON_MAGIC;
 153         algo.core_mode = ARMV4_5_MODE_SVC;
 154         algo.core_state = ARMV4_5_STATE_ARM;
 155
 156         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
 157         init_reg_param(&reg_params[1], "r1", 32, PARAM_IN);
 158         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN);
 159
 160         buf_set_u32(reg_params[0].value, 0, 32, hw->data);
 161         buf_set_u32(reg_params[1].value, 0, 32, target_buf);
 162         buf_set_u32(reg_params[2].value, 0, 32, size);
 163
 164         retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 165                                         hw->copy_area->address,
 166                                         hw->copy_area->address + code_size - 4,
 167                                         1000, &algo);
 168         if (retval != ERROR_OK)
 169                 LOG_ERROR("error executing hosted NAND write");
 170
 171         destroy_reg_param(&reg_params[0]);
 172         destroy_reg_param(&reg_params[1]);
 173         destroy_reg_param(&reg_params[2]);
 174         return retval;
 175 }
 176
 177 static int orion_nand_reset(struct nand_device_s *device)
 178 {
 179         return orion_nand_command(device, NAND_CMD_RESET);
 180 }
 181
 182 static int orion_nand_controller_ready(struct nand_device_s *device, int timeout)
 183 {
 184         return 1;
 185 }
 186
 187 static int orion_nand_register_commands(struct command_context_s *cmd_ctx)
 188 {
 189         return ERROR_OK;
 190 }
 191
 192 int orion_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
 193                               char **args, int argc,
 194                               struct nand_device_s *device)
 195 {
 196         orion_nand_controller_t *hw;
 197         u32 base;
 198         uint8_t ale, cle;
 199
 200         if (argc != 3) {
 201                 LOG_ERROR("arguments must be: <target_number> <NAND_address>\n");
 202                 return ERROR_NAND_DEVICE_INVALID;
 203         }
 204
 205         hw = calloc(1, sizeof(*hw));
 206         if (!hw) {
 207                 LOG_ERROR("no memory for nand controller\n");
 208                 return ERROR_NAND_DEVICE_INVALID;
 209         }
 210
 211         device->controller_priv = hw;
 212         hw->target = get_target(args[1]);
 213         if (!hw->target) {
 214                 LOG_ERROR("target '%s' not defined", args[1]);
 215                 free(hw);
 216                 return ERROR_NAND_DEVICE_INVALID;
 217         }
 218
 219         base = strtoul(args[2], NULL, 0);
 220         cle = 0;
 221         ale = 1;
 222
 223         hw->data = base;
 224         hw->cmd = base + (1 << cle);
 225         hw->addr = base + (1 << ale);
 226
 227         return ERROR_OK;
 228 }
 229
 230 static int orion_nand_init(struct nand_device_s *device)
 231 {
 232         return ERROR_OK;
 233 }
 234
 235 nand_flash_controller_t orion_nand_controller =
 236 {
 237         .name                   = "orion",
 238         .command                = orion_nand_command,
 239         .address                = orion_nand_address,
 240         .read_data              = orion_nand_read,
 241         .write_data             = orion_nand_write,
 242         .write_block_data       = orion_nand_fast_block_write,
 243         .reset                  = orion_nand_reset,
 244         .controller_ready       = orion_nand_controller_ready,
 245         .nand_device_command    = orion_nand_device_command,
 246         .register_commands      = orion_nand_register_commands,
 247         .init                   = orion_nand_init,
 248 };
 249