xmc4xxx: Improve xmc4xxx_blank_check_memory() error handling
[fw/openocd] / src / flash / nor / xmc4xxx.c
1 /**************************************************************************
2 *   Copyright (C) 2015 Jeff Ciesielski <jeffciesielski@gmail.com>         *
3 *                                                                         *
4 *   This program is free software; you can redistribute it and/or modify  *
5 *   it under the terms of the GNU General Public License as published by  *
6 *   the Free Software Foundation; either version 2 of the License, or     *
7 *   (at your option) any later version.                                   *
8 *                                                                         *
9 *   This program is distributed in the hope that it will be useful,       *
10 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
11 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
12 *   GNU General Public License for more details.                          *
13 *                                                                         *
14 ***************************************************************************/
15
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19
20 #include "imp.h"
21 #include <helper/binarybuffer.h>
22 #include <target/algorithm.h>
23 #include <target/armv7m.h>
24
25 /* Maximum number of sectors */
26 #define MAX_XMC_SECTORS 12
27
28 /* System control unit registers */
29 #define SCU_REG_BASE 0x50004000
30
31 #define SCU_ID_CHIP 0x04
32
33 /* Base of the non-cached flash memory */
34 #define PFLASH_BASE     0x0C000000
35
36 /* User configuration block offsets */
37 #define UCB0_BASE       0x00000000
38 #define UCB1_BASE       0x00000400
39 #define UCB2_BASE       0x00000800
40
41 /* Flash register base */
42 #define FLASH_REG_BASE 0x58000000
43
44 /* PMU ID Registers */
45 #define FLASH_REG_PMU_ID        (FLASH_REG_BASE | 0x0508)
46
47 /* PMU Fields */
48 #define PMU_MOD_REV_MASK        0xFF
49 #define PMU_MOD_TYPE_MASK       0xFF00
50 #define PMU_MOD_NO_MASK         0xFFFF0000
51
52 /* Prefetch Config */
53 #define FLASH_REG_PREF_PCON     (FLASH_REG_BASE | 0x4000)
54
55 /* Prefetch Fields */
56 #define PCON_IBYP       (1 << 0)
57 #define PCON_IINV       (1 << 1)
58
59 /* Flash ID Register */
60 #define FLASH_REG_FLASH0_ID     (FLASH_REG_BASE | 0x2008)
61
62 /* Flash Status Register */
63 #define FLASH_REG_FLASH0_FSR    (FLASH_REG_BASE | 0x2010)
64
65 #define FSR_PBUSY       (0)
66 #define FSR_FABUSY      (1)
67 #define FSR_PROG        (4)
68 #define FSR_ERASE       (5)
69 #define FSR_PFPAGE      (6)
70 #define FSR_PFOPER      (8)
71 #define FSR_SQER        (10)
72 #define FSR_PROER       (11)
73 #define FSR_PFSBER      (12)
74 #define FSR_PFDBER      (14)
75 #define FSR_PROIN       (16)
76 #define FSR_RPROIN      (18)
77 #define FSR_RPRODIS     (19)
78 #define FSR_WPROIN0     (21)
79 #define FSR_WPROIN1     (22)
80 #define FSR_WPROIN2     (23)
81 #define FSR_WPRODIS0    (25)
82 #define FSR_WPRODIS1    (26)
83 #define FSR_SLM         (28)
84 #define FSR_VER         (31)
85
86 #define FSR_PBUSY_MASK          (0x01 << FSR_PBUSY)
87 #define FSR_FABUSY_MASK         (0x01 << FSR_FABUSY)
88 #define FSR_PROG_MASK           (0x01 << FSR_PROG)
89 #define FSR_ERASE_MASK          (0x01 << FSR_ERASE)
90 #define FSR_PFPAGE_MASK         (0x01 << FSR_PFPAGE)
91 #define FSR_PFOPER_MASK         (0x01 << FSR_PFOPER)
92 #define FSR_SQER_MASK           (0x01 << FSR_SQER)
93 #define FSR_PROER_MASK          (0x01 << FSR_PROER)
94 #define FSR_PFSBER_MASK         (0x01 << FSR_PFSBER)
95 #define FSR_PFDBER_MASK         (0x01 << FSR_PFDBER)
96 #define FSR_PROIN_MASK          (0x01 << FSR_PROIN)
97 #define FSR_RPROIN_MASK         (0x01 << FSR_RPROIN)
98 #define FSR_RPRODIS_MASK        (0x01 << FSR_RPRODIS)
99 #define FSR_WPROIN0_MASK        (0x01 << FSR_WPROIN0)
100 #define FSR_WPROIN1_MASK        (0x01 << FSR_WPROIN1)
101 #define FSR_WPROIN2_MASK        (0x01 << FSR_WPROIN2)
102 #define FSR_WPRODIS0_MASK       (0x01 << FSR_WPRODIS0)
103 #define FSR_WPRODIS1_MASK       (0x01 << FSR_WPRODIS1)
104 #define FSR_SLM_MASK            (0x01 << FSR_SLM)
105 #define FSR_VER_MASK            (0x01 << FSR_VER)
106
107 /* Flash Config Register */
108 #define FLASH_REG_FLASH0_FCON   (FLASH_REG_BASE | 0x2014)
109
110 #define FCON_WSPFLASH           (0)
111 #define FCON_WSECPF             (4)
112 #define FCON_IDLE               (13)
113 #define FCON_ESLDIS             (14)
114 #define FCON_SLEEP              (15)
115 #define FCON_RPA                (16)
116 #define FCON_DCF                (17)
117 #define FCON_DDF                (18)
118 #define FCON_VOPERM             (24)
119 #define FCON_SQERM              (25)
120 #define FCON_PROERM             (26)
121 #define FCON_PFSBERM            (27)
122 #define FCON_PFDBERM            (29)
123 #define FCON_EOBM               (31)
124
125 #define FCON_WSPFLASH_MASK      (0x0f << FCON_WSPFLASH)
126 #define FCON_WSECPF_MASK        (0x01 << FCON_WSECPF)
127 #define FCON_IDLE_MASK          (0x01 << FCON_IDLE)
128 #define FCON_ESLDIS_MASK        (0x01 << FCON_ESLDIS)
129 #define FCON_SLEEP_MASK         (0x01 << FCON_SLEEP)
130 #define FCON_RPA_MASK           (0x01 << FCON_RPA)
131 #define FCON_DCF_MASK           (0x01 << FCON_DCF)
132 #define FCON_DDF_MASK           (0x01 << FCON_DDF)
133 #define FCON_VOPERM_MASK        (0x01 << FCON_VOPERM)
134 #define FCON_SQERM_MASK         (0x01 << FCON_SQERM)
135 #define FCON_PROERM_MASK        (0x01 << FCON_PROERM)
136 #define FCON_PFSBERM_MASK       (0x01 << FCON_PFSBERM)
137 #define FCON_PFDBERM_MASK       (0x01 << FCON_PFDBERM)
138 #define FCON_EOBM_MASK          (0x01 << FCON_EOBM)
139
140 /* Flash Margin Control Register */
141 #define FLASH_REG_FLASH0_MARP   (FLASH_REG_BASE | 0x2018)
142
143 #define MARP_MARGIN             (0)
144 #define MARP_TRAPDIS            (15)
145
146 #define MARP_MARGIN_MASK        (0x0f << MARP_MARGIN)
147 #define MARP_TRAPDIS_MASK       (0x01 << MARP_TRAPDIS)
148
149 /* Flash Protection Registers */
150 #define FLASH_REG_FLASH0_PROCON0        (FLASH_REG_BASE | 0x2020)
151 #define FLASH_REG_FLASH0_PROCON1        (FLASH_REG_BASE | 0x2024)
152 #define FLASH_REG_FLASH0_PROCON2        (FLASH_REG_BASE | 0x2028)
153
154 #define PROCON_S0L             (0)
155 #define PROCON_S1L             (1)
156 #define PROCON_S2L             (2)
157 #define PROCON_S3L             (3)
158 #define PROCON_S4L             (4)
159 #define PROCON_S5L             (5)
160 #define PROCON_S6L             (6)
161 #define PROCON_S7L             (7)
162 #define PROCON_S8L             (8)
163 #define PROCON_S9L             (9)
164 #define PROCON_S10_S11L        (10)
165 #define PROCON_RPRO            (15)
166
167 #define PROCON_S0L_MASK        (0x01 << PROCON_S0L)
168 #define PROCON_S1L_MASK        (0x01 << PROCON_S1L)
169 #define PROCON_S2L_MASK        (0x01 << PROCON_S2L)
170 #define PROCON_S3L_MASK        (0x01 << PROCON_S3L)
171 #define PROCON_S4L_MASK        (0x01 << PROCON_S4L)
172 #define PROCON_S5L_MASK        (0x01 << PROCON_S5L)
173 #define PROCON_S6L_MASK        (0x01 << PROCON_S6L)
174 #define PROCON_S7L_MASK        (0x01 << PROCON_S7L)
175 #define PROCON_S8L_MASK        (0x01 << PROCON_S8L)
176 #define PROCON_S9L_MASK        (0x01 << PROCON_S9L)
177 #define PROCON_S10_S11L_MASK   (0x01 << PROCON_S10_S11L)
178 #define PROCON_RPRO_MASK       (0x01 << PROCON_RPRO)
179
180 #define FLASH_PROTECT_CONFIRMATION_CODE 0x8AFE15C3
181
182 /* Flash controller configuration values */
183 #define FLASH_ID_XMC4500        0xA2
184 #define FLASH_ID_XMC4700_4800   0x92
185 #define FLASH_ID_XMC4100_4200   0x9C
186 #define FLASH_ID_XMC4400        0x9F
187
188 /* Timeouts */
189 #define FLASH_OP_TIMEOUT 5000
190
191 /* Flash commands (write/erase/protect) are performed using special
192  * command sequences that are written to magic addresses in the flash controller */
193 /* Command sequence addresses.  See reference manual, section 8: Flash Command Sequences */
194 #define FLASH_CMD_ERASE_1 0x0C005554
195 #define FLASH_CMD_ERASE_2 0x0C00AAA8
196 #define FLASH_CMD_ERASE_3 FLASH_CMD_ERASE_1
197 #define FLASH_CMD_ERASE_4 FLASH_CMD_ERASE_1
198 #define FLASH_CMD_ERASE_5 FLASH_CMD_ERASE_2
199 /* ERASE_6 is the sector base address */
200
201 #define FLASH_CMD_CLEAR_STATUS FLASH_CMD_ERASE_1
202
203 #define FLASH_CMD_ENTER_PAGEMODE FLASH_CMD_ERASE_1
204
205 #define FLASH_CMD_LOAD_PAGE_1 0x0C0055F0
206 #define FLASH_CMD_LOAD_PAGE_2 0x0C0055F4
207
208 #define FLASH_CMD_WRITE_PAGE_1 FLASH_CMD_ERASE_1
209 #define FLASH_CMD_WRITE_PAGE_2 FLASH_CMD_ERASE_2
210 #define FLASH_CMD_WRITE_PAGE_3 FLASH_CMD_ERASE_1
211 /* WRITE_PAGE_4 is the page base address */
212
213 #define FLASH_CMD_TEMP_UNPROT_1 FLASH_CMD_ERASE_1
214 #define FLASH_CMD_TEMP_UNPROT_2 FLASH_CMD_ERASE_2
215 #define FLASH_CMD_TEMP_UNPROT_3 0x0C00553C
216 #define FLASH_CMD_TEMP_UNPROT_4 FLASH_CMD_ERASE_2
217 #define FLASH_CMD_TEMP_UNPROT_5 FLASH_CMD_ERASE_2
218 #define FLASH_CMD_TEMP_UNPROT_6 0x0C005558
219
220 struct xmc4xxx_flash_bank {
221         bool probed;
222
223         /* We need the flash controller ID to choose the sector layout */
224         uint32_t fcon_id;
225
226         /* Passwords used for protection operations */
227         uint32_t pw1;
228         uint32_t pw2;
229         bool pw_set;
230
231         /* Protection flags */
232         bool read_protected;
233
234         bool write_prot_otp[MAX_XMC_SECTORS];
235 };
236
237 struct xmc4xxx_command_seq {
238         uint32_t address;
239         uint32_t magic;
240 };
241
242 /* Sector capacities.  See section 8 of xmc4x00_rm */
243 static const unsigned int sector_capacity_8[8] = {
244         16, 16, 16, 16, 16, 16, 16, 128
245 };
246
247 static const unsigned int sector_capacity_9[9] = {
248         16, 16, 16, 16, 16, 16, 16, 128, 256
249 };
250
251 static const unsigned int sector_capacity_12[12] = {
252         16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256
253 };
254
255 static const unsigned int sector_capacity_16[16] = {
256         16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256, 256, 256, 256, 256
257 };
258
259 static int xmc4xxx_write_command_sequence(struct flash_bank *bank,
260                                          struct xmc4xxx_command_seq *seq,
261                                          int seq_len)
262 {
263         int res = ERROR_OK;
264
265         for (int i = 0; i < seq_len; i++) {
266                 res = target_write_u32(bank->target, seq[i].address,
267                                        seq[i].magic);
268                 if (res != ERROR_OK)
269                         return res;
270         }
271
272         return ERROR_OK;
273 }
274
275 static int xmc4xxx_load_bank_layout(struct flash_bank *bank)
276 {
277         const unsigned int *capacity = NULL;
278
279         /* At this point, we know which flash controller ID we're
280          * talking to and simply need to fill out the bank structure accordingly */
281         LOG_DEBUG("%d sectors", bank->num_sectors);
282
283         switch (bank->num_sectors) {
284         case 8:
285                 capacity = sector_capacity_8;
286                 break;
287         case 9:
288                 capacity = sector_capacity_9;
289                 break;
290         case 12:
291                 capacity = sector_capacity_12;
292                 break;
293         case 16:
294                 capacity = sector_capacity_16;
295                 break;
296         default:
297                 LOG_ERROR("Unexpected number of sectors, %d\n",
298                           bank->num_sectors);
299                 return ERROR_FAIL;
300         }
301
302         /* This looks like a bank that we understand, now we know the
303          * corresponding sector capacities and we can add those up into the
304          * bank size. */
305         uint32_t total_offset = 0;
306         bank->sectors = calloc(bank->num_sectors,
307                                sizeof(struct flash_sector));
308         for (int i = 0; i < bank->num_sectors; i++) {
309                 bank->sectors[i].size = capacity[i] * 1024;
310                 bank->sectors[i].offset = total_offset;
311                 bank->sectors[i].is_erased = -1;
312                 bank->sectors[i].is_protected = -1;
313
314                 bank->size += bank->sectors[i].size;
315                 LOG_DEBUG("\t%d: %uk", i, capacity[i]);
316                 total_offset += bank->sectors[i].size;
317         }
318
319         /* This part doesn't follow the typical standard of 0xff
320          * being the default padding value.*/
321         bank->default_padded_value = 0x00;
322
323         return ERROR_OK;
324 }
325
326 static int xmc4xxx_probe(struct flash_bank *bank)
327 {
328         int res;
329         uint32_t devid, config;
330         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
331         uint8_t flash_id;
332
333         if (fb->probed)
334                 return ERROR_OK;
335
336         /* It's not possible for the DAP to access the OTP locations needed for
337          * probing the part info and Flash geometry so we require that the target
338          * be halted before proceeding. */
339         if (bank->target->state != TARGET_HALTED) {
340                 LOG_WARNING("Cannot communicate... target not halted.");
341                 return ERROR_TARGET_NOT_HALTED;
342         }
343
344         /* The SCU registers contain the ID of the chip */
345         res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &devid);
346         if (res != ERROR_OK) {
347                 LOG_ERROR("Cannot read device identification register.");
348                 return res;
349         }
350
351         /* Make sure this is a XMC4000 family device */
352         if ((devid & 0xF0000) != 0x40000 && devid != 0) {
353                 LOG_ERROR("Platform ID doesn't match XMC4xxx: 0x%08" PRIx32, devid);
354                 return ERROR_FAIL;
355         }
356
357         LOG_DEBUG("Found XMC4xxx with devid: 0x%08" PRIx32, devid);
358
359         /* Now sanity-check the Flash controller itself. */
360         res = target_read_u32(bank->target, FLASH_REG_FLASH0_ID,
361                         &config);
362         if (res != ERROR_OK) {
363                 LOG_ERROR("Cannot read Flash bank configuration.");
364                 return res;
365         }
366         flash_id = (config & 0xff0000) >> 16;
367
368         /* The Flash configuration register is our only means of
369          * determining the sector layout. We need to make sure that
370          * we understand the type of controller we're dealing with */
371         switch (flash_id) {
372         case FLASH_ID_XMC4100_4200:
373                 bank->num_sectors = 8;
374                 LOG_DEBUG("XMC4xxx: XMC4100/4200 detected.");
375                 break;
376         case FLASH_ID_XMC4400:
377                 bank->num_sectors = 9;
378                 LOG_DEBUG("XMC4xxx: XMC4400 detected.");
379                 break;
380         case FLASH_ID_XMC4500:
381                 bank->num_sectors = 12;
382                 LOG_DEBUG("XMC4xxx: XMC4500 detected.");
383                 break;
384         case FLASH_ID_XMC4700_4800:
385                 bank->num_sectors = 16;
386                 LOG_DEBUG("XMC4xxx: XMC4700/4800 detected.");
387                 break;
388         default:
389                 LOG_ERROR("XMC4xxx: Unexpected flash ID. got %02" PRIx8,
390                           flash_id);
391                 return ERROR_FAIL;
392         }
393
394         /* Retrieve information about the particular bank we're probing and fill in
395          * the bank structure accordingly. */
396         res = xmc4xxx_load_bank_layout(bank);
397         if (res == ERROR_OK) {
398                 /* We're done */
399                 fb->probed = true;
400         } else {
401                 LOG_ERROR("Unable to load bank information.");
402                 return ERROR_FAIL;
403         }
404
405         return ERROR_OK;
406 }
407
408 static int xmc4xxx_get_sector_start_addr(struct flash_bank *bank,
409                                          int sector, uint32_t *ret_addr)
410 {
411         /* Make sure we understand this sector */
412         if (sector > bank->num_sectors)
413                 return ERROR_FAIL;
414
415         *ret_addr = bank->base + bank->sectors[sector].offset;
416
417         return ERROR_OK;
418
419 }
420
421 static int xmc4xxx_clear_flash_status(struct flash_bank *bank)
422 {
423         int res;
424         /* TODO: Do we need to check for sequence error? */
425         LOG_INFO("Clearing flash status");
426         res = target_write_u32(bank->target, FLASH_CMD_CLEAR_STATUS,
427                                0xF5);
428         if (res != ERROR_OK) {
429                 LOG_ERROR("Unable to write erase command sequence");
430                 return res;
431         }
432
433         return ERROR_OK;
434 }
435
436 static int xmc4xxx_get_flash_status(struct flash_bank *bank, uint32_t *status)
437 {
438         int res;
439
440         res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, status);
441
442         if (res != ERROR_OK)
443                 LOG_ERROR("Cannot read flash status register.");
444
445         return res;
446 }
447
448 static int xmc4xxx_wait_status_busy(struct flash_bank *bank, int timeout)
449 {
450         int res;
451         uint32_t status;
452
453         res = xmc4xxx_get_flash_status(bank, &status);
454         if (res != ERROR_OK)
455                 return res;
456
457         /* While the flash controller is busy, wait */
458         while (status & FSR_PBUSY_MASK) {
459                 res = xmc4xxx_get_flash_status(bank, &status);
460                 if (res != ERROR_OK)
461                         return res;
462
463                 if (timeout-- <= 0) {
464                         LOG_ERROR("Timed out waiting for flash");
465                         return ERROR_FAIL;
466                 }
467                 alive_sleep(1);
468                 keep_alive();
469         }
470
471         if (status & FSR_PROER_MASK) {
472                 LOG_ERROR("XMC4xxx flash protected");
473                 res = ERROR_FAIL;
474         }
475
476         return res;
477 }
478
479 static int xmc4xxx_erase_sector(struct flash_bank *bank, uint32_t address,
480                                 bool user_config)
481 {
482         int res;
483         uint32_t status;
484
485         /* See reference manual table 8.4: Command Sequences for Flash Control */
486         struct xmc4xxx_command_seq erase_cmd_seq[6] = {
487                 {FLASH_CMD_ERASE_1, 0xAA},
488                 {FLASH_CMD_ERASE_2, 0x55},
489                 {FLASH_CMD_ERASE_3, 0x80},
490                 {FLASH_CMD_ERASE_4, 0xAA},
491                 {FLASH_CMD_ERASE_5, 0x55},
492                 {0xFF,              0xFF} /* Needs filled in */
493         };
494
495         /* We need to fill in the base address of the sector we'll be
496          * erasing, as well as the magic code that determines whether
497          * this is a standard flash sector or a user configuration block */
498
499         erase_cmd_seq[5].address = address;
500         if (user_config) {
501                 /* Removing flash protection requires the addition of
502                  * the base address */
503                 erase_cmd_seq[5].address += bank->base;
504                 erase_cmd_seq[5].magic = 0xC0;
505         } else {
506                 erase_cmd_seq[5].magic = 0x30;
507         }
508
509         res = xmc4xxx_write_command_sequence(bank, erase_cmd_seq,
510                                              ARRAY_SIZE(erase_cmd_seq));
511         if (res != ERROR_OK)
512                 return res;
513
514         /* Read the flash status register */
515         res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, &status);
516         if (res != ERROR_OK) {
517                 LOG_ERROR("Cannot read flash status register.");
518                 return res;
519         }
520
521         /* Check for a sequence error */
522         if (status & FSR_SQER_MASK) {
523                 LOG_ERROR("Error with flash erase sequence");
524                 return ERROR_FAIL;
525         }
526
527         /* Make sure a flash erase was triggered */
528         if (!(status & FSR_ERASE_MASK)) {
529                 LOG_ERROR("Flash failed to erase");
530                 return ERROR_FAIL;
531         }
532
533         /* Now we must wait for the erase operation to end */
534         res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
535
536         return res;
537 }
538
539 static int xmc4xxx_erase(struct flash_bank *bank, int first, int last)
540 {
541         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
542         int res;
543
544         if (bank->target->state != TARGET_HALTED) {
545                 LOG_ERROR("Unable to erase, target is not halted");
546                 return ERROR_TARGET_NOT_HALTED;
547         }
548
549         if (!fb->probed) {
550                 res = xmc4xxx_probe(bank);
551                 if (res != ERROR_OK)
552                         return res;
553         }
554
555         uint32_t tmp_addr;
556         /* Loop through the sectors and erase each one */
557         for (int i = first; i <= last; i++) {
558                 res = xmc4xxx_get_sector_start_addr(bank, i, &tmp_addr);
559                 if (res != ERROR_OK) {
560                         LOG_ERROR("Invalid sector %d", i);
561                         return res;
562                 }
563
564                 LOG_DEBUG("Erasing sector %d @ 0x%08"PRIx32, i, tmp_addr);
565
566                 res = xmc4xxx_erase_sector(bank, tmp_addr, false);
567                 if (res != ERROR_OK) {
568                         LOG_ERROR("Unable to write erase command sequence");
569                         goto clear_status_and_exit;
570                 }
571
572                 /* Now we must wait for the erase operation to end */
573                 res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
574
575                 if (res != ERROR_OK)
576                         goto clear_status_and_exit;
577
578                 bank->sectors[i].is_erased = 1;
579         }
580
581 clear_status_and_exit:
582         res = xmc4xxx_clear_flash_status(bank);
583         return res;
584
585 }
586
587 static int xmc4xxx_enter_page_mode(struct flash_bank *bank)
588 {
589         int res;
590         uint32_t status;
591
592         res = target_write_u32(bank->target, FLASH_CMD_ENTER_PAGEMODE, 0x50);
593         if (res != ERROR_OK) {
594                 LOG_ERROR("Unable to write enter page mode command");
595                 return ERROR_FAIL;
596         }
597
598         res = xmc4xxx_get_flash_status(bank, &status);
599
600         if (res != ERROR_OK)
601                 return res;
602
603         /* Make sure we're in page mode */
604         if (!(status & FSR_PFPAGE_MASK)) {
605                 LOG_ERROR("Unable to enter page mode");
606                 return ERROR_FAIL;
607         }
608
609         /* Make sure we didn't encounter a sequence error */
610         if (status & FSR_SQER_MASK) {
611                 LOG_ERROR("Sequence error while entering page mode");
612                 return ERROR_FAIL;
613         }
614
615         return res;
616 }
617
618 /* The logical erase value of an xmc4xxx memory cell is 0x00,
619  * therefore, we cannot use the built in flash blank check and must
620  * implement our own */
621
622 /** Checks whether a memory region is zeroed. */
623 static int xmc4xxx_blank_check_memory(struct target *target,
624         uint32_t address, uint32_t count, uint32_t *blank)
625 {
626         struct working_area *erase_check_algorithm;
627         struct reg_param reg_params[3];
628         struct armv7m_algorithm armv7m_info;
629         int retval;
630
631         static const uint8_t erase_check_code[] = {
632 #include "../../../contrib/loaders/erase_check/armv7m_0_erase_check.inc"
633         };
634
635         /* make sure we have a working area */
636         if (target_alloc_working_area(target, sizeof(erase_check_code),
637                 &erase_check_algorithm) != ERROR_OK)
638                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
639
640         retval = target_write_buffer(target, erase_check_algorithm->address,
641                         sizeof(erase_check_code), (uint8_t *)erase_check_code);
642         if (retval != ERROR_OK)
643                 goto cleanup;
644
645         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
646         armv7m_info.core_mode = ARM_MODE_THREAD;
647
648         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
649         buf_set_u32(reg_params[0].value, 0, 32, address);
650
651         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
652         buf_set_u32(reg_params[1].value, 0, 32, count);
653
654         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
655         buf_set_u32(reg_params[2].value, 0, 32, 0x00);
656
657         retval = target_run_algorithm(target,
658                                       0,
659                                       NULL,
660                                       3,
661                                       reg_params,
662                                       erase_check_algorithm->address,
663                                       erase_check_algorithm->address + (sizeof(erase_check_code) - 2),
664                                       10000,
665                                       &armv7m_info);
666
667         if (retval == ERROR_OK)
668                 *blank = buf_get_u32(reg_params[2].value, 0, 32);
669
670         destroy_reg_param(&reg_params[0]);
671         destroy_reg_param(&reg_params[1]);
672         destroy_reg_param(&reg_params[2]);
673
674 cleanup:
675         target_free_working_area(target, erase_check_algorithm);
676
677         return retval;
678 }
679
680 static int xmc4xxx_flash_blank_check(struct flash_bank *bank)
681 {
682         struct target *target = bank->target;
683         int i;
684         int retval = ERROR_OK;
685         uint32_t blank;
686
687         if (bank->target->state != TARGET_HALTED) {
688                 LOG_ERROR("Target not halted");
689                 return ERROR_TARGET_NOT_HALTED;
690         }
691
692         for (i = 0; i < bank->num_sectors; i++) {
693                 uint32_t address = bank->base + bank->sectors[i].offset;
694                 uint32_t size = bank->sectors[i].size;
695
696                 LOG_DEBUG("Erase checking 0x%08"PRIx32, address);
697                 retval = xmc4xxx_blank_check_memory(target, address, size, &blank);
698
699                 if (retval != ERROR_OK)
700                         break;
701
702                 if (blank == 0x00)
703                         bank->sectors[i].is_erased = 1;
704                 else
705                         bank->sectors[i].is_erased = 0;
706         }
707
708         return retval;
709 }
710
711 static int xmc4xxx_write_page(struct flash_bank *bank, const uint8_t *pg_buf,
712                               uint32_t offset, bool user_config)
713 {
714         int res;
715         uint32_t status;
716
717         /* Base of the flash write command */
718         struct xmc4xxx_command_seq write_cmd_seq[4] = {
719                 {FLASH_CMD_WRITE_PAGE_1, 0xAA},
720                 {FLASH_CMD_WRITE_PAGE_2, 0x55},
721                 {FLASH_CMD_WRITE_PAGE_3, 0xFF}, /* Needs filled in */
722                 {0xFF,                   0xFF}  /* Needs filled in */
723         };
724
725         /* The command sequence differs depending on whether this is
726          * being written to standard flash or the user configuration
727          * area */
728         if (user_config)
729                 write_cmd_seq[2].magic = 0xC0;
730         else
731                 write_cmd_seq[2].magic = 0xA0;
732
733         /* Finally, we need to add the address that this page will be
734          * written to */
735         write_cmd_seq[3].address = bank->base + offset;
736         write_cmd_seq[3].magic = 0xAA;
737
738
739         /* Flash pages are written 256 bytes at a time.  For each 256
740          * byte chunk, we need to:
741          * 1. Enter page mode. This activates the flash write buffer
742          * 2. Load the page buffer with data (2x 32 bit words at a time)
743          * 3. Burn the page buffer into its intended location
744          * If the starting offset is not on a 256 byte boundary, we
745          * will need to pad the beginning of the write buffer
746          * accordingly. Likewise, if the last page does not fill the
747          * buffer, we should pad it to avoid leftover data from being
748          * written to flash
749          */
750         res = xmc4xxx_enter_page_mode(bank);
751         if (res != ERROR_OK)
752                 return res;
753
754         /* Copy the data into the page buffer*/
755         for (int i = 0; i < 256; i += 8) {
756                 uint32_t w_lo = target_buffer_get_u32(bank->target, &pg_buf[i]);
757                 uint32_t w_hi = target_buffer_get_u32(bank->target, &pg_buf[i + 4]);
758                 LOG_DEBUG("WLO: %08"PRIx32, w_lo);
759                 LOG_DEBUG("WHI: %08"PRIx32, w_hi);
760
761                 /* Data is loaded 2x 32 bit words at a time */
762                 res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_1, w_lo);
763                 if (res != ERROR_OK)
764                         return res;
765
766                 res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_2, w_hi);
767                 if (res != ERROR_OK)
768                         return res;
769
770                 /* Check for an error */
771                 res = xmc4xxx_get_flash_status(bank, &status);
772                 if (res != ERROR_OK)
773                         return res;
774
775                 if (status & FSR_SQER_MASK) {
776                         LOG_ERROR("Error loading page buffer");
777                         return ERROR_FAIL;
778                 }
779         }
780
781         /* The page buffer is now full, time to commit it to flash */
782
783         res = xmc4xxx_write_command_sequence(bank, write_cmd_seq, ARRAY_SIZE(write_cmd_seq));
784         if (res != ERROR_OK) {
785                 LOG_ERROR("Unable to enter write command sequence");
786                 return res;
787         }
788
789         /* Read the flash status register */
790         res = xmc4xxx_get_flash_status(bank, &status);
791         if (res != ERROR_OK)
792                 return res;
793
794         /* Check for a sequence error */
795         if (status & FSR_SQER_MASK) {
796                 LOG_ERROR("Error with flash write sequence");
797                 return ERROR_FAIL;
798         }
799
800         /* Make sure a flash write was triggered */
801         if (!(status & FSR_PROG_MASK)) {
802                 LOG_ERROR("Failed to write flash page");
803                 return ERROR_FAIL;
804         }
805
806         /* Wait for the write operation to end */
807         res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
808         if (res != ERROR_OK)
809                 return res;
810
811         /* TODO: Verify that page was written without error */
812         return res;
813 }
814
815 static int xmc4xxx_write(struct flash_bank *bank, const uint8_t *buffer,
816                          uint32_t offset, uint32_t count)
817 {
818         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
819         int res = ERROR_OK;
820
821         if (bank->target->state != TARGET_HALTED) {
822                 LOG_ERROR("Unable to erase, target is not halted");
823                 return ERROR_TARGET_NOT_HALTED;
824         }
825
826         if (!fb->probed) {
827                 res = xmc4xxx_probe(bank);
828                 if (res != ERROR_OK)
829                         return res;
830         }
831
832         /* Make sure we won't run off the end of the flash bank */
833         if ((offset + count) > (bank->size)) {
834                 LOG_ERROR("Attempting to write past the end of flash");
835                 return ERROR_FAIL;
836         }
837
838
839         /* Attempt to write the passed in buffer to flash */
840         /* Pages are written 256 bytes at a time, we need to handle
841          * scenarios where padding is required at the beginning and
842          * end of a page */
843         while (count) {
844                 /* page working area */
845                 uint8_t tmp_buf[256] = {0};
846
847                 /* Amount of data we'll be writing to this page */
848                 int remaining;
849                 int end_pad;
850
851                 remaining = MIN(count, sizeof(tmp_buf));
852                 end_pad   = sizeof(tmp_buf) - remaining;
853
854                 /* Make sure we're starting on a page boundary */
855                 int start_pad = offset % 256;
856                 if (start_pad) {
857                         LOG_INFO("Write does not start on a 256 byte boundary. "
858                                  "Padding by %d bytes", start_pad);
859                         memset(tmp_buf, 0xff, start_pad);
860                         /* Subtract the amount of start offset from
861                          * the amount of data we'll need to write */
862                         remaining -= start_pad;
863                 }
864
865                 /* Remove the amount we'll be writing from the total count */
866                 count -= remaining;
867
868                 /* Now copy in the remaining data */
869                 memcpy(&tmp_buf[start_pad], buffer, remaining);
870
871                 if (end_pad) {
872                         LOG_INFO("Padding end of page @%08"PRIx32" by %d bytes",
873                                  bank->base + offset, end_pad);
874                         memset(&tmp_buf[256 - end_pad], 0xff, end_pad);
875                 }
876
877                 /* Now commit this page to flash, if there was start
878                  * padding, we should subtract that from the target offset */
879                 res = xmc4xxx_write_page(bank, tmp_buf, (offset - start_pad), false);
880                 if (res != ERROR_OK) {
881                         LOG_ERROR("Unable to write flash page");
882                         goto abort_write_and_exit;
883                 }
884
885                 /* Advance the buffer pointer */
886                 buffer += remaining;
887
888                 /* Advance the offset */
889                 offset += remaining;
890         }
891
892 abort_write_and_exit:
893         xmc4xxx_clear_flash_status(bank);
894         return res;
895
896 }
897
898 static int xmc4xxx_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
899 {
900         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
901         uint32_t scu_idcode;
902
903         if (bank->target->state != TARGET_HALTED) {
904                 LOG_WARNING("Cannot communicate... target not halted.");
905                 return ERROR_TARGET_NOT_HALTED;
906         }
907
908         /* The SCU registers contain the ID of the chip */
909         int res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &scu_idcode);
910         if (res != ERROR_OK) {
911                 LOG_ERROR("Cannot read device identification register.");
912                 return res;
913         }
914
915         uint16_t dev_id = (scu_idcode & 0xfff0) >> 4;
916         uint16_t rev_id = scu_idcode & 0xf;
917         const char *dev_str;
918         const char *rev_str = NULL;
919
920         switch (dev_id) {
921         case 0x100:
922                 dev_str = "XMC4100";
923
924                 switch (rev_id) {
925                 case 0x1:
926                         rev_str = "AA";
927                         break;
928                 case 0x2:
929                         rev_str = "AB";
930                         break;
931                 }
932                 break;
933         case 0x200:
934                 dev_str = "XMC4200";
935
936                 switch (rev_id) {
937                 case 0x1:
938                         rev_str = "AA";
939                         break;
940                 case 0x2:
941                         rev_str = "AB";
942                         break;
943                 }
944                 break;
945         case 0x400:
946                 dev_str = "XMC4400";
947
948                 switch (rev_id) {
949                 case 0x1:
950                         rev_str = "AA";
951                         break;
952                 case 0x2:
953                         rev_str = "AB";
954                         break;
955                 }
956                 break;
957         case 0:
958                 /* XMC4500 EES AA13 with date codes before GE212
959                  * had zero SCU_IDCHIP
960                  */
961                 dev_str = "XMC4500 EES";
962                 rev_str = "AA13";
963                 break;
964         case 0x500:
965                 dev_str = "XMC4500";
966
967                 switch (rev_id) {
968                 case 0x2:
969                         rev_str = "AA";
970                         break;
971                 case 0x3:
972                         rev_str = "AB";
973                         break;
974                 case 0x4:
975                         rev_str = "AC";
976                         break;
977                 }
978                 break;
979         case 0x700:
980                 dev_str = "XMC4700";
981
982                 switch (rev_id) {
983                 case 0x1:
984                         rev_str = "EES-AA";
985                         break;
986                 }
987                 break;
988         case 0x800:
989                 dev_str = "XMC4800";
990
991                 switch (rev_id) {
992                 case 0x1:
993                         rev_str = "EES-AA";
994                         break;
995                 }
996                 break;
997
998         default:
999                 snprintf(buf, buf_size,
1000                          "Cannot identify target as an XMC4xxx. SCU_ID: %"PRIx32"\n",
1001                          scu_idcode);
1002                 return ERROR_OK;
1003         }
1004
1005         /* String to declare protection data held in the private driver */
1006         char prot_str[512] = {0};
1007         if (fb->read_protected)
1008                 snprintf(prot_str, sizeof(prot_str), "\nFlash is read protected");
1009
1010         bool otp_enabled = false;
1011         for (int i = 0; i < bank->num_sectors; i++)
1012                 if (fb->write_prot_otp[i])
1013                         otp_enabled = true;
1014
1015         /* If OTP Write protection is enabled (User 2), list each
1016          * sector that has it enabled */
1017         char otp_str[8];
1018         if (otp_enabled) {
1019                 strcat(prot_str, "\nOTP Protection is enabled for sectors:\n");
1020                 for (int i = 0; i < bank->num_sectors; i++) {
1021                         if (fb->write_prot_otp[i]) {
1022                                 snprintf(otp_str, sizeof(otp_str), "- %d\n", i);
1023                                 strncat(prot_str, otp_str, ARRAY_SIZE(otp_str));
1024                         }
1025                 }
1026         }
1027
1028         if (rev_str != NULL)
1029                 snprintf(buf, buf_size, "%s - Rev: %s%s",
1030                          dev_str, rev_str, prot_str);
1031         else
1032                 snprintf(buf, buf_size, "%s - Rev: unknown (0x%01x)%s",
1033                          dev_str, rev_id, prot_str);
1034
1035         return ERROR_OK;
1036 }
1037
1038 static int xmc4xxx_temp_unprotect(struct flash_bank *bank, int user_level)
1039 {
1040         struct xmc4xxx_flash_bank *fb;
1041         int res = ERROR_OK;
1042         uint32_t status = 0;
1043
1044         struct xmc4xxx_command_seq temp_unprot_seq[6] = {
1045                 {FLASH_CMD_TEMP_UNPROT_1, 0xAA},
1046                 {FLASH_CMD_TEMP_UNPROT_2, 0x55},
1047                 {FLASH_CMD_TEMP_UNPROT_3, 0xFF}, /* Needs filled in */
1048                 {FLASH_CMD_TEMP_UNPROT_4, 0xFF}, /* Needs filled in */
1049                 {FLASH_CMD_TEMP_UNPROT_5, 0xFF}, /* Needs filled in */
1050                 {FLASH_CMD_TEMP_UNPROT_6, 0x05}
1051         };
1052
1053         if (user_level < 0 || user_level > 2) {
1054                 LOG_ERROR("Invalid user level, must be 0-2");
1055                 return ERROR_FAIL;
1056         }
1057
1058         fb = bank->driver_priv;
1059
1060         /* Fill in the user level and passwords */
1061         temp_unprot_seq[2].magic = user_level;
1062         temp_unprot_seq[3].magic = fb->pw1;
1063         temp_unprot_seq[4].magic = fb->pw2;
1064
1065         res = xmc4xxx_write_command_sequence(bank, temp_unprot_seq,
1066                                              ARRAY_SIZE(temp_unprot_seq));
1067         if (res != ERROR_OK) {
1068                 LOG_ERROR("Unable to write temp unprotect sequence");
1069                 return res;
1070         }
1071
1072         res = xmc4xxx_get_flash_status(bank, &status);
1073         if (res != ERROR_OK)
1074                 return res;
1075
1076         if (status & FSR_WPRODIS0) {
1077                 LOG_INFO("Flash is temporarily unprotected");
1078         } else {
1079                 LOG_INFO("Unable to disable flash protection");
1080                 res = ERROR_FAIL;
1081         }
1082
1083
1084         return res;
1085 }
1086
1087 static int xmc4xxx_flash_unprotect(struct flash_bank *bank, int32_t level)
1088 {
1089         uint32_t addr;
1090         int res;
1091
1092         if ((level < 0) || (level > 1)) {
1093                 LOG_ERROR("Invalid user level. Must be 0-1");
1094                 return ERROR_FAIL;
1095         }
1096
1097         switch (level) {
1098         case 0:
1099                 addr = UCB0_BASE;
1100                 break;
1101         case 1:
1102                 addr = UCB1_BASE;
1103                 break;
1104         }
1105
1106         res = xmc4xxx_erase_sector(bank, addr, true);
1107
1108         if (res != ERROR_OK)
1109                 LOG_ERROR("Error erasing user configuration block");
1110
1111         return res;
1112 }
1113
1114 /* Reference: "XMC4500 Flash Protection.pptx" app note */
1115 static int xmc4xxx_flash_protect(struct flash_bank *bank, int level, bool read_protect,
1116                                  int first, int last)
1117 {
1118         /* User configuration block buffers */
1119         uint8_t ucp0_buf[8 * sizeof(uint32_t)] = {0};
1120         uint32_t ucb_base = 0;
1121         uint32_t procon = 0;
1122         int res = ERROR_OK;
1123         uint32_t status = 0;
1124         bool proin = false;
1125
1126         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1127
1128         /* Read protect only works for user 0, make sure we don't try
1129          * to do something silly */
1130         if (level != 0 && read_protect) {
1131                 LOG_ERROR("Read protection is for user level 0 only!");
1132                 return ERROR_FAIL;
1133         }
1134
1135         /* Check to see if protection is already installed for the
1136          * specified user level.  If it is, the user configuration
1137          * block will need to be erased before we can continue */
1138
1139         /* Grab the flash status register*/
1140         res = xmc4xxx_get_flash_status(bank, &status);
1141         if (res != ERROR_OK)
1142                 return res;
1143
1144         switch (level) {
1145         case 0:
1146                 if ((status & FSR_RPROIN_MASK) || (status & FSR_WPROIN0_MASK))
1147                         proin = true;
1148                 break;
1149         case 1:
1150                 if (status & FSR_WPROIN1_MASK)
1151                         proin = true;
1152                 break;
1153         case 2:
1154                 if (status & FSR_WPROIN2_MASK)
1155                         proin = true;
1156                 break;
1157         }
1158
1159         if (proin) {
1160                 LOG_ERROR("Flash protection is installed for user %d"
1161                           " and must be removed before continuing", level);
1162                 return ERROR_FAIL;
1163         }
1164
1165         /* If this device has 12 flash sectors, protection for
1166          * sectors 10 & 11 are handled jointly. If we are trying to
1167          * write all sectors, we should decrement
1168          * last to ensure we don't write to a register bit that
1169          * doesn't exist*/
1170         if ((bank->num_sectors == 12) && (last == 12))
1171                 last--;
1172
1173         /*  We need to fill out the procon register representation
1174          *   that we will be writing to the device */
1175         for (int i = first; i <= last; i++)
1176                 procon |= 1 << i;
1177
1178         /* If read protection is requested, set the appropriate bit
1179          * (we checked that this is allowed above) */
1180         if (read_protect)
1181                 procon |= PROCON_RPRO_MASK;
1182
1183         LOG_DEBUG("Setting flash protection with procon:");
1184         LOG_DEBUG("PROCON: %"PRIx32, procon);
1185
1186         /* First we need to copy in the procon register to the buffer
1187          * we're going to attempt to write.  This is written twice */
1188         target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], procon);
1189         target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], procon);
1190
1191         /* Now we must copy in both flash passwords.  As with the
1192          * procon data, this must be written twice (4 total words
1193          * worth of data) */
1194         target_buffer_set_u32(bank->target, &ucp0_buf[4 * 4], fb->pw1);
1195         target_buffer_set_u32(bank->target, &ucp0_buf[5 * 4], fb->pw2);
1196         target_buffer_set_u32(bank->target, &ucp0_buf[6 * 4], fb->pw1);
1197         target_buffer_set_u32(bank->target, &ucp0_buf[7 * 4], fb->pw2);
1198
1199         /* Finally, (if requested) we copy in the confirmation
1200          * code so that the protection is permanent and will
1201          * require a password to undo. */
1202         target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
1203         target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
1204
1205         /* Now that the data is copied into place, we must write
1206          * these pages into flash */
1207
1208         /* The user configuration block base depends on what level of
1209          * protection we're trying to install, select the proper one */
1210         switch (level) {
1211         case 0:
1212                 ucb_base = UCB0_BASE;
1213                 break;
1214         case 1:
1215                 ucb_base = UCB1_BASE;
1216                 break;
1217         case 2:
1218                 ucb_base = UCB2_BASE;
1219                 break;
1220         }
1221
1222         /* Write the user config pages */
1223         res = xmc4xxx_write_page(bank, ucp0_buf, ucb_base, true);
1224         if (res != ERROR_OK) {
1225                 LOG_ERROR("Error writing user configuration block 0");
1226                 return res;
1227         }
1228
1229         return ERROR_OK;
1230 }
1231
1232 static int xmc4xxx_protect(struct flash_bank *bank, int set, int first, int last)
1233 {
1234         int ret;
1235         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1236
1237         /* Check for flash passwords */
1238         if (!fb->pw_set) {
1239                 LOG_ERROR("Flash passwords not set, use xmc4xxx flash_password to set them");
1240                 return ERROR_FAIL;
1241         }
1242
1243         /* We want to clear flash protection temporarily*/
1244         if (set == 0) {
1245                 LOG_WARNING("Flash protection will be temporarily disabled"
1246                             " for all pages (User 0 only)!");
1247                 ret = xmc4xxx_temp_unprotect(bank, 0);
1248                 return ret;
1249         }
1250
1251         /* Install write protection for user 0 on the specified pages */
1252         ret = xmc4xxx_flash_protect(bank, 0, false, first, last);
1253
1254         return ret;
1255 }
1256
1257 static int xmc4xxx_protect_check(struct flash_bank *bank)
1258 {
1259         int ret;
1260         uint32_t protection[3] = {0};
1261         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1262
1263         ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON0, &protection[0]);
1264         if (ret != ERROR_OK) {
1265                 LOG_ERROR("Unable to read flash User0 protection register");
1266                 return ret;
1267         }
1268
1269         ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON1, &protection[1]);
1270         if (ret != ERROR_OK) {
1271                 LOG_ERROR("Unable to read flash User1 protection register");
1272                 return ret;
1273         }
1274
1275         ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON2, &protection[2]);
1276         if (ret != ERROR_OK) {
1277                 LOG_ERROR("Unable to read flash User2 protection register");
1278                 return ret;
1279         }
1280
1281         int sectors = bank->num_sectors;
1282
1283         /* On devices with 12 sectors, sectors 10 & 11 are ptected
1284          * together instead of individually */
1285         if (sectors == 12)
1286                 sectors--;
1287
1288         /* Clear the protection status */
1289         for (int i = 0; i < bank->num_sectors; i++) {
1290                 bank->sectors[i].is_protected = 0;
1291                 fb->write_prot_otp[i] = false;
1292         }
1293         fb->read_protected = false;
1294
1295         /* The xmc4xxx series supports 3 levels of user protection
1296          * (User0, User1 (low priority), and User 2(OTP), we need to
1297          * check all 3 */
1298         for (unsigned int i = 0; i < ARRAY_SIZE(protection); i++) {
1299
1300                 /* Check for write protection on every available
1301                 *  sector */
1302                 for (int j = 0; j < sectors; j++) {
1303                         int set = (protection[i] & (1 << j)) ? 1 : 0;
1304                         bank->sectors[j].is_protected |= set;
1305
1306                         /* Handle sector 11 */
1307                         if (j == 10)
1308                                 bank->sectors[j + 1].is_protected |= set;
1309
1310                         /* User 2 indicates this protection is
1311                          * permanent, make note in the private driver structure */
1312                         if (i == 2 && set) {
1313                                 fb->write_prot_otp[j] = true;
1314
1315                                 /* Handle sector 11 */
1316                                 if (j == 10)
1317                                         fb->write_prot_otp[j + 1] = true;
1318                         }
1319
1320                 }
1321         }
1322
1323         /* XMC4xxx also supports read proptection, make a note
1324          * in the private driver structure */
1325         if (protection[0] & PROCON_RPRO_MASK)
1326                 fb->read_protected = true;
1327
1328         return ERROR_OK;
1329 }
1330
1331 FLASH_BANK_COMMAND_HANDLER(xmc4xxx_flash_bank_command)
1332 {
1333         bank->driver_priv = malloc(sizeof(struct xmc4xxx_flash_bank));
1334
1335         if (!bank->driver_priv)
1336                 return ERROR_FLASH_OPERATION_FAILED;
1337
1338         (void)memset(bank->driver_priv, 0, sizeof(struct xmc4xxx_flash_bank));
1339
1340         return ERROR_OK;
1341 }
1342
1343 COMMAND_HANDLER(xmc4xxx_handle_flash_password_command)
1344 {
1345         int res;
1346         struct flash_bank *bank;
1347
1348         if (CMD_ARGC < 3)
1349                 return ERROR_COMMAND_SYNTAX_ERROR;
1350
1351         res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1352         if (res != ERROR_OK)
1353                 return res;
1354
1355         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1356
1357         errno = 0;
1358
1359         /* We skip over the flash bank */
1360         fb->pw1 = strtol(CMD_ARGV[1], NULL, 16);
1361
1362         if (errno)
1363                 return ERROR_COMMAND_SYNTAX_ERROR;
1364
1365         fb->pw2 = strtol(CMD_ARGV[2], NULL, 16);
1366
1367         if (errno)
1368                 return ERROR_COMMAND_SYNTAX_ERROR;
1369
1370         fb->pw_set = true;
1371
1372         command_print(CMD_CTX, "XMC4xxx flash passwords set to:\n");
1373         command_print(CMD_CTX, "-0x%08"PRIx32"\n", fb->pw1);
1374         command_print(CMD_CTX, "-0x%08"PRIx32"\n", fb->pw2);
1375         return ERROR_OK;
1376 }
1377
1378 COMMAND_HANDLER(xmc4xxx_handle_flash_unprotect_command)
1379 {
1380         struct flash_bank *bank;
1381         int res;
1382         int32_t level;
1383
1384         if (CMD_ARGC < 2)
1385                 return ERROR_COMMAND_SYNTAX_ERROR;
1386
1387         res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1388         if (res != ERROR_OK)
1389                 return res;
1390
1391         COMMAND_PARSE_NUMBER(s32, CMD_ARGV[1], level);
1392
1393         res = xmc4xxx_flash_unprotect(bank, level);
1394
1395         return res;
1396 }
1397
1398 static const struct command_registration xmc4xxx_exec_command_handlers[] = {
1399         {
1400                 .name = "flash_password",
1401                 .handler = xmc4xxx_handle_flash_password_command,
1402                 .mode = COMMAND_EXEC,
1403                 .usage = "bank_id password1 password2",
1404                 .help = "Set the flash passwords used for protect operations. "
1405                 "Passwords should be in standard hex form (0x00000000). "
1406                 "(You must call this before any other protect commands) "
1407                 "NOTE: The xmc4xxx's UCB area only allows for FOUR cycles. "
1408                 "Please use protection carefully!",
1409         },
1410         {
1411                 .name = "flash_unprotect",
1412                 .handler = xmc4xxx_handle_flash_unprotect_command,
1413                 .mode = COMMAND_EXEC,
1414                 .usage = "bank_id user_level[0-1]",
1415                 .help = "Permanently Removes flash protection (read and write) "
1416                 "for the specified user level",
1417         },      COMMAND_REGISTRATION_DONE
1418 };
1419
1420 static const struct command_registration xmc4xxx_command_handlers[] = {
1421         {
1422                 .name = "xmc4xxx",
1423                 .mode = COMMAND_ANY,
1424                 .help = "xmc4xxx flash command group",
1425                 .usage = "",
1426                 .chain = xmc4xxx_exec_command_handlers,
1427         },
1428         COMMAND_REGISTRATION_DONE
1429 };
1430
1431 struct flash_driver xmc4xxx_flash = {
1432         .name = "xmc4xxx",
1433         .commands = xmc4xxx_command_handlers,
1434         .flash_bank_command = xmc4xxx_flash_bank_command,
1435         .erase = xmc4xxx_erase,
1436         .write = xmc4xxx_write,
1437         .read = default_flash_read,
1438         .probe = xmc4xxx_probe,
1439         .auto_probe = xmc4xxx_probe,
1440         .erase_check = xmc4xxx_flash_blank_check,
1441         .info = xmc4xxx_get_info_command,
1442         .protect_check = xmc4xxx_protect_check,
1443         .protect = xmc4xxx_protect,
1444 };