1 /**************************************************************************
2 * Copyright (C) 2015 Jeff Ciesielski <jeffciesielski@gmail.com> *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 ***************************************************************************/
21 #include <helper/binarybuffer.h>
22 #include <target/algorithm.h>
23 #include <target/armv7m.h>
25 /* Maximum number of sectors */
26 #define MAX_XMC_SECTORS 12
28 /* System control unit registers */
29 #define SCU_REG_BASE 0x50004000
31 #define SCU_ID_CHIP 0x04
33 /* Base of the non-cached flash memory */
34 #define PFLASH_BASE 0x0C000000
36 /* User configuration block offsets */
37 #define UCB0_BASE 0x00000000
38 #define UCB1_BASE 0x00000400
39 #define UCB2_BASE 0x00000800
41 /* Flash register base */
42 #define FLASH_REG_BASE 0x58000000
44 /* PMU ID Registers */
45 #define FLASH_REG_PMU_ID (FLASH_REG_BASE | 0x0508)
48 #define PMU_MOD_REV_MASK 0xFF
49 #define PMU_MOD_TYPE_MASK 0xFF00
50 #define PMU_MOD_NO_MASK 0xFFFF0000
53 #define FLASH_REG_PREF_PCON (FLASH_REG_BASE | 0x4000)
56 #define PCON_IBYP (1 << 0)
57 #define PCON_IINV (1 << 1)
59 /* Flash ID Register */
60 #define FLASH_REG_FLASH0_ID (FLASH_REG_BASE | 0x2008)
62 /* Flash Status Register */
63 #define FLASH_REG_FLASH0_FSR (FLASH_REG_BASE | 0x2010)
66 #define FSR_FABUSY (1)
69 #define FSR_PFPAGE (6)
70 #define FSR_PFOPER (8)
72 #define FSR_PROER (11)
73 #define FSR_PFSBER (12)
74 #define FSR_PFDBER (14)
75 #define FSR_PROIN (16)
76 #define FSR_RPROIN (18)
77 #define FSR_RPRODIS (19)
78 #define FSR_WPROIN0 (21)
79 #define FSR_WPROIN1 (22)
80 #define FSR_WPROIN2 (23)
81 #define FSR_WPRODIS0 (25)
82 #define FSR_WPRODIS1 (26)
86 #define FSR_PBUSY_MASK (0x01 << FSR_PBUSY)
87 #define FSR_FABUSY_MASK (0x01 << FSR_FABUSY)
88 #define FSR_PROG_MASK (0x01 << FSR_PROG)
89 #define FSR_ERASE_MASK (0x01 << FSR_ERASE)
90 #define FSR_PFPAGE_MASK (0x01 << FSR_PFPAGE)
91 #define FSR_PFOPER_MASK (0x01 << FSR_PFOPER)
92 #define FSR_SQER_MASK (0x01 << FSR_SQER)
93 #define FSR_PROER_MASK (0x01 << FSR_PROER)
94 #define FSR_PFSBER_MASK (0x01 << FSR_PFSBER)
95 #define FSR_PFDBER_MASK (0x01 << FSR_PFDBER)
96 #define FSR_PROIN_MASK (0x01 << FSR_PROIN)
97 #define FSR_RPROIN_MASK (0x01 << FSR_RPROIN)
98 #define FSR_RPRODIS_MASK (0x01 << FSR_RPRODIS)
99 #define FSR_WPROIN0_MASK (0x01 << FSR_WPROIN0)
100 #define FSR_WPROIN1_MASK (0x01 << FSR_WPROIN1)
101 #define FSR_WPROIN2_MASK (0x01 << FSR_WPROIN2)
102 #define FSR_WPRODIS0_MASK (0x01 << FSR_WPRODIS0)
103 #define FSR_WPRODIS1_MASK (0x01 << FSR_WPRODIS1)
104 #define FSR_SLM_MASK (0x01 << FSR_SLM)
105 #define FSR_VER_MASK (0x01 << FSR_VER)
107 /* Flash Config Register */
108 #define FLASH_REG_FLASH0_FCON (FLASH_REG_BASE | 0x2014)
110 #define FCON_WSPFLASH (0)
111 #define FCON_WSECPF (4)
112 #define FCON_IDLE (13)
113 #define FCON_ESLDIS (14)
114 #define FCON_SLEEP (15)
115 #define FCON_RPA (16)
116 #define FCON_DCF (17)
117 #define FCON_DDF (18)
118 #define FCON_VOPERM (24)
119 #define FCON_SQERM (25)
120 #define FCON_PROERM (26)
121 #define FCON_PFSBERM (27)
122 #define FCON_PFDBERM (29)
123 #define FCON_EOBM (31)
125 #define FCON_WSPFLASH_MASK (0x0f << FCON_WSPFLASH)
126 #define FCON_WSECPF_MASK (0x01 << FCON_WSECPF)
127 #define FCON_IDLE_MASK (0x01 << FCON_IDLE)
128 #define FCON_ESLDIS_MASK (0x01 << FCON_ESLDIS)
129 #define FCON_SLEEP_MASK (0x01 << FCON_SLEEP)
130 #define FCON_RPA_MASK (0x01 << FCON_RPA)
131 #define FCON_DCF_MASK (0x01 << FCON_DCF)
132 #define FCON_DDF_MASK (0x01 << FCON_DDF)
133 #define FCON_VOPERM_MASK (0x01 << FCON_VOPERM)
134 #define FCON_SQERM_MASK (0x01 << FCON_SQERM)
135 #define FCON_PROERM_MASK (0x01 << FCON_PROERM)
136 #define FCON_PFSBERM_MASK (0x01 << FCON_PFSBERM)
137 #define FCON_PFDBERM_MASK (0x01 << FCON_PFDBERM)
138 #define FCON_EOBM_MASK (0x01 << FCON_EOBM)
140 /* Flash Margin Control Register */
141 #define FLASH_REG_FLASH0_MARP (FLASH_REG_BASE | 0x2018)
143 #define MARP_MARGIN (0)
144 #define MARP_TRAPDIS (15)
146 #define MARP_MARGIN_MASK (0x0f << MARP_MARGIN)
147 #define MARP_TRAPDIS_MASK (0x01 << MARP_TRAPDIS)
149 /* Flash Protection Registers */
150 #define FLASH_REG_FLASH0_PROCON0 (FLASH_REG_BASE | 0x2020)
151 #define FLASH_REG_FLASH0_PROCON1 (FLASH_REG_BASE | 0x2024)
152 #define FLASH_REG_FLASH0_PROCON2 (FLASH_REG_BASE | 0x2028)
154 #define PROCON_S0L (0)
155 #define PROCON_S1L (1)
156 #define PROCON_S2L (2)
157 #define PROCON_S3L (3)
158 #define PROCON_S4L (4)
159 #define PROCON_S5L (5)
160 #define PROCON_S6L (6)
161 #define PROCON_S7L (7)
162 #define PROCON_S8L (8)
163 #define PROCON_S9L (9)
164 #define PROCON_S10_S11L (10)
165 #define PROCON_RPRO (15)
167 #define PROCON_S0L_MASK (0x01 << PROCON_S0L)
168 #define PROCON_S1L_MASK (0x01 << PROCON_S1L)
169 #define PROCON_S2L_MASK (0x01 << PROCON_S2L)
170 #define PROCON_S3L_MASK (0x01 << PROCON_S3L)
171 #define PROCON_S4L_MASK (0x01 << PROCON_S4L)
172 #define PROCON_S5L_MASK (0x01 << PROCON_S5L)
173 #define PROCON_S6L_MASK (0x01 << PROCON_S6L)
174 #define PROCON_S7L_MASK (0x01 << PROCON_S7L)
175 #define PROCON_S8L_MASK (0x01 << PROCON_S8L)
176 #define PROCON_S9L_MASK (0x01 << PROCON_S9L)
177 #define PROCON_S10_S11L_MASK (0x01 << PROCON_S10_S11L)
178 #define PROCON_RPRO_MASK (0x01 << PROCON_RPRO)
180 #define FLASH_PROTECT_CONFIRMATION_CODE 0x8AFE15C3
182 /* Flash controller configuration values */
183 #define FLASH_ID_XMC4500 0xA2
184 #define FLASH_ID_XMC4100_4200 0x9C
185 #define FLASH_ID_XMC4400 0x9F
188 #define FLASH_OP_TIMEOUT 5000
190 /* Flash commands (write/erase/protect) are performed using special
191 * command sequences that are written to magic addresses in the flash controller */
192 /* Command sequence addresses. See reference manual, section 8: Flash Command Sequences */
193 #define FLASH_CMD_ERASE_1 0x0C005554
194 #define FLASH_CMD_ERASE_2 0x0C00AAA8
195 #define FLASH_CMD_ERASE_3 FLASH_CMD_ERASE_1
196 #define FLASH_CMD_ERASE_4 FLASH_CMD_ERASE_1
197 #define FLASH_CMD_ERASE_5 FLASH_CMD_ERASE_2
198 /* ERASE_6 is the sector base address */
200 #define FLASH_CMD_CLEAR_STATUS FLASH_CMD_ERASE_1
202 #define FLASH_CMD_ENTER_PAGEMODE FLASH_CMD_ERASE_1
204 #define FLASH_CMD_LOAD_PAGE_1 0x0C0055F0
205 #define FLASH_CMD_LOAD_PAGE_2 0x0C0055F4
207 #define FLASH_CMD_WRITE_PAGE_1 FLASH_CMD_ERASE_1
208 #define FLASH_CMD_WRITE_PAGE_2 FLASH_CMD_ERASE_2
209 #define FLASH_CMD_WRITE_PAGE_3 FLASH_CMD_ERASE_1
210 /* WRITE_PAGE_4 is the page base address */
212 #define FLASH_CMD_TEMP_UNPROT_1 FLASH_CMD_ERASE_1
213 #define FLASH_CMD_TEMP_UNPROT_2 FLASH_CMD_ERASE_2
214 #define FLASH_CMD_TEMP_UNPROT_3 0x0C00553C
215 #define FLASH_CMD_TEMP_UNPROT_4 FLASH_CMD_ERASE_2
216 #define FLASH_CMD_TEMP_UNPROT_5 FLASH_CMD_ERASE_2
217 #define FLASH_CMD_TEMP_UNPROT_6 0x0C005558
219 struct xmc4xxx_flash_bank {
222 /* We need the flash controller ID to choose the sector layout */
225 /* Passwords used for protection operations */
230 /* Protection flags */
233 bool write_prot_otp[MAX_XMC_SECTORS];
236 struct xmc4xxx_command_seq {
241 /* Sector capacities. See section 8 of xmc4x00_rm */
242 static const unsigned int sector_capacity_8[8] = {
243 16, 16, 16, 16, 16, 16, 16, 128
246 static const unsigned int sector_capacity_9[9] = {
247 16, 16, 16, 16, 16, 16, 16, 128, 256
250 static const unsigned int sector_capacity_12[12] = {
251 16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256
254 static int xmc4xxx_write_command_sequence(struct flash_bank *bank,
255 struct xmc4xxx_command_seq *seq,
260 for (int i = 0; i < seq_len; i++) {
261 res = target_write_u32(bank->target, seq[i].address,
270 static int xmc4xxx_load_bank_layout(struct flash_bank *bank)
272 const unsigned int *capacity = NULL;
274 /* At this point, we know which flash controller ID we're
275 * talking to and simply need to fill out the bank structure accordingly */
276 LOG_DEBUG("%d sectors", bank->num_sectors);
278 switch (bank->num_sectors) {
280 capacity = sector_capacity_8;
283 capacity = sector_capacity_9;
286 capacity = sector_capacity_12;
289 LOG_ERROR("Unexpected number of sectors, %d\n",
294 /* This looks like a bank that we understand, now we know the
295 * corresponding sector capacities and we can add those up into the
297 uint32_t total_offset = 0;
298 bank->sectors = calloc(bank->num_sectors,
299 sizeof(struct flash_sector));
300 for (int i = 0; i < bank->num_sectors; i++) {
301 bank->sectors[i].size = capacity[i] * 1024;
302 bank->sectors[i].offset = total_offset;
303 bank->sectors[i].is_erased = -1;
304 bank->sectors[i].is_protected = -1;
306 bank->size += bank->sectors[i].size;
307 LOG_DEBUG("\t%d: %uk", i, capacity[i]);
308 total_offset += bank->sectors[i].size;
311 /* This part doesn't follow the typical standard of 0xff
312 * being the default padding value.*/
313 bank->default_padded_value = 0x00;
318 static int xmc4xxx_probe(struct flash_bank *bank)
321 uint32_t devid, config;
322 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
328 /* It's not possible for the DAP to access the OTP locations needed for
329 * probing the part info and Flash geometry so we require that the target
330 * be halted before proceeding. */
331 if (bank->target->state != TARGET_HALTED) {
332 LOG_WARNING("Cannot communicate... target not halted.");
333 return ERROR_TARGET_NOT_HALTED;
336 /* The SCU registers contain the ID of the chip */
337 res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &devid);
338 if (res != ERROR_OK) {
339 LOG_ERROR("Cannot read device identification register.");
343 /* Make sure this is a XMC4000 family device */
344 if ((devid & 0xF0000) != 0x40000 && devid != 0) {
345 LOG_ERROR("Platform ID doesn't match XMC4xxx: 0x%08" PRIx32, devid);
349 LOG_DEBUG("Found XMC4xxx with devid: 0x%08" PRIx32, devid);
351 /* Now sanity-check the Flash controller itself. */
352 res = target_read_u32(bank->target, FLASH_REG_FLASH0_ID,
354 if (res != ERROR_OK) {
355 LOG_ERROR("Cannot read Flash bank configuration.");
358 flash_id = (config & 0xff0000) >> 16;
360 /* The Flash configuration register is our only means of
361 * determining the sector layout. We need to make sure that
362 * we understand the type of controller we're dealing with */
364 case FLASH_ID_XMC4100_4200:
365 bank->num_sectors = 8;
366 LOG_DEBUG("XMC4xxx: XMC4100/4200 detected.");
368 case FLASH_ID_XMC4400:
369 bank->num_sectors = 9;
370 LOG_DEBUG("XMC4xxx: XMC4400 detected.");
372 case FLASH_ID_XMC4500:
373 bank->num_sectors = 12;
374 LOG_DEBUG("XMC4xxx: XMC4500 detected.");
377 LOG_ERROR("XMC4xxx: Unexpected flash ID. got %02" PRIx8,
382 /* Retrieve information about the particular bank we're probing and fill in
383 * the bank structure accordingly. */
384 res = xmc4xxx_load_bank_layout(bank);
385 if (res == ERROR_OK) {
389 LOG_ERROR("Unable to load bank information.");
396 static int xmc4xxx_get_sector_start_addr(struct flash_bank *bank,
397 int sector, uint32_t *ret_addr)
399 /* Make sure we understand this sector */
400 if (sector > bank->num_sectors)
403 *ret_addr = bank->base + bank->sectors[sector].offset;
409 static int xmc4xxx_clear_flash_status(struct flash_bank *bank)
412 /* TODO: Do we need to check for sequence error? */
413 LOG_INFO("Clearing flash status");
414 res = target_write_u32(bank->target, FLASH_CMD_CLEAR_STATUS,
416 if (res != ERROR_OK) {
417 LOG_ERROR("Unable to write erase command sequence");
424 static int xmc4xxx_get_flash_status(struct flash_bank *bank, uint32_t *status)
428 res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, status);
431 LOG_ERROR("Cannot read flash status register.");
436 static int xmc4xxx_wait_status_busy(struct flash_bank *bank, int timeout)
441 res = xmc4xxx_get_flash_status(bank, &status);
445 /* While the flash controller is busy, wait */
446 while (status & FSR_PBUSY_MASK) {
447 res = xmc4xxx_get_flash_status(bank, &status);
451 if (timeout-- <= 0) {
452 LOG_ERROR("Timed out waiting for flash");
459 if (status & FSR_PROER_MASK) {
460 LOG_ERROR("XMC4xxx flash protected");
467 static int xmc4xxx_erase_sector(struct flash_bank *bank, uint32_t address,
473 /* See reference manual table 8.4: Command Sequences for Flash Control */
474 struct xmc4xxx_command_seq erase_cmd_seq[6] = {
475 {FLASH_CMD_ERASE_1, 0xAA},
476 {FLASH_CMD_ERASE_2, 0x55},
477 {FLASH_CMD_ERASE_3, 0x80},
478 {FLASH_CMD_ERASE_4, 0xAA},
479 {FLASH_CMD_ERASE_5, 0x55},
480 {0xFF, 0xFF} /* Needs filled in */
483 /* We need to fill in the base address of the sector we'll be
484 * erasing, as well as the magic code that determines whether
485 * this is a standard flash sector or a user configuration block */
487 erase_cmd_seq[5].address = address;
489 /* Removing flash protection requires the addition of
490 * the base address */
491 erase_cmd_seq[5].address += bank->base;
492 erase_cmd_seq[5].magic = 0xC0;
494 erase_cmd_seq[5].magic = 0x30;
497 res = xmc4xxx_write_command_sequence(bank, erase_cmd_seq,
498 ARRAY_SIZE(erase_cmd_seq));
502 /* Read the flash status register */
503 res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, &status);
504 if (res != ERROR_OK) {
505 LOG_ERROR("Cannot read flash status register.");
509 /* Check for a sequence error */
510 if (status & FSR_SQER_MASK) {
511 LOG_ERROR("Error with flash erase sequence");
515 /* Make sure a flash erase was triggered */
516 if (!(status & FSR_ERASE_MASK)) {
517 LOG_ERROR("Flash failed to erase");
521 /* Now we must wait for the erase operation to end */
522 res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
527 static int xmc4xxx_erase(struct flash_bank *bank, int first, int last)
529 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
532 if (bank->target->state != TARGET_HALTED) {
533 LOG_ERROR("Unable to erase, target is not halted");
534 return ERROR_TARGET_NOT_HALTED;
538 res = xmc4xxx_probe(bank);
544 /* Loop through the sectors and erase each one */
545 for (int i = first; i <= last; i++) {
546 res = xmc4xxx_get_sector_start_addr(bank, i, &tmp_addr);
547 if (res != ERROR_OK) {
548 LOG_ERROR("Invalid sector %d", i);
552 LOG_DEBUG("Erasing sector %d @ 0x%08"PRIx32, i, tmp_addr);
554 res = xmc4xxx_erase_sector(bank, tmp_addr, false);
555 if (res != ERROR_OK) {
556 LOG_ERROR("Unable to write erase command sequence");
557 goto clear_status_and_exit;
560 /* Now we must wait for the erase operation to end */
561 res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
564 goto clear_status_and_exit;
566 bank->sectors[i].is_erased = 1;
569 clear_status_and_exit:
570 res = xmc4xxx_clear_flash_status(bank);
575 static int xmc4xxx_enter_page_mode(struct flash_bank *bank)
580 res = target_write_u32(bank->target, FLASH_CMD_ENTER_PAGEMODE, 0x50);
581 if (res != ERROR_OK) {
582 LOG_ERROR("Unable to write enter page mode command");
586 res = xmc4xxx_get_flash_status(bank, &status);
591 /* Make sure we're in page mode */
592 if (!(status & FSR_PFPAGE_MASK)) {
593 LOG_ERROR("Unable to enter page mode");
597 /* Make sure we didn't encounter a sequence error */
598 if (status & FSR_SQER_MASK) {
599 LOG_ERROR("Sequence error while entering page mode");
606 /* The logical erase value of an xmc4xxx memory cell is 0x00,
607 * therefore, we cannot use the built in flash blank check and must
608 * implement our own */
610 /** Checks whether a memory region is zeroed. */
611 int xmc4xxx_blank_check_memory(struct target *target,
612 uint32_t address, uint32_t count, uint32_t *blank)
614 struct working_area *erase_check_algorithm;
615 struct reg_param reg_params[3];
616 struct armv7m_algorithm armv7m_info;
619 /* see contrib/loaders/erase_check/armv7m_0_erase_check.s for src */
621 static const uint8_t erase_check_code[] = {
623 0x03, 0x78, /* ldrb r3, [r0] */
624 0x01, 0x30, /* adds r0, #1 */
625 0x1A, 0x43, /* orrs r2, r2, r3 */
626 0x01, 0x39, /* subs r1, r1, #1 */
627 0xFA, 0xD1, /* bne loop */
628 0x00, 0xBE /* bkpt #0 */
631 /* make sure we have a working area */
632 if (target_alloc_working_area(target, sizeof(erase_check_code),
633 &erase_check_algorithm) != ERROR_OK)
634 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
636 retval = target_write_buffer(target, erase_check_algorithm->address,
637 sizeof(erase_check_code), (uint8_t *)erase_check_code);
638 if (retval != ERROR_OK)
641 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
642 armv7m_info.core_mode = ARM_MODE_THREAD;
644 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
645 buf_set_u32(reg_params[0].value, 0, 32, address);
647 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
648 buf_set_u32(reg_params[1].value, 0, 32, count);
650 init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
651 buf_set_u32(reg_params[2].value, 0, 32, 0x00);
653 retval = target_run_algorithm(target,
658 erase_check_algorithm->address,
659 erase_check_algorithm->address + (sizeof(erase_check_code) - 2),
663 if (retval == ERROR_OK)
664 *blank = buf_get_u32(reg_params[2].value, 0, 32);
666 destroy_reg_param(®_params[0]);
667 destroy_reg_param(®_params[1]);
668 destroy_reg_param(®_params[2]);
670 target_free_working_area(target, erase_check_algorithm);
675 static int xmc4xxx_flash_blank_check(struct flash_bank *bank)
677 struct target *target = bank->target;
682 if (bank->target->state != TARGET_HALTED) {
683 LOG_ERROR("Target not halted");
684 return ERROR_TARGET_NOT_HALTED;
687 for (i = 0; i < bank->num_sectors; i++) {
688 uint32_t address = bank->base + bank->sectors[i].offset;
689 uint32_t size = bank->sectors[i].size;
691 LOG_DEBUG("Erase checking 0x%08"PRIx32, address);
692 retval = xmc4xxx_blank_check_memory(target, address, size, &blank);
694 if (retval != ERROR_OK)
698 bank->sectors[i].is_erased = 1;
700 bank->sectors[i].is_erased = 0;
706 static int xmc4xxx_write_page(struct flash_bank *bank, const uint8_t *pg_buf,
707 uint32_t offset, bool user_config)
712 /* Base of the flash write command */
713 struct xmc4xxx_command_seq write_cmd_seq[4] = {
714 {FLASH_CMD_WRITE_PAGE_1, 0xAA},
715 {FLASH_CMD_WRITE_PAGE_2, 0x55},
716 {FLASH_CMD_WRITE_PAGE_3, 0xFF}, /* Needs filled in */
717 {0xFF, 0xFF} /* Needs filled in */
720 /* The command sequence differs depending on whether this is
721 * being written to standard flash or the user configuration
724 write_cmd_seq[2].magic = 0xC0;
726 write_cmd_seq[2].magic = 0xA0;
728 /* Finally, we need to add the address that this page will be
730 write_cmd_seq[3].address = bank->base + offset;
731 write_cmd_seq[3].magic = 0xAA;
734 /* Flash pages are written 256 bytes at a time. For each 256
735 * byte chunk, we need to:
736 * 1. Enter page mode. This activates the flash write buffer
737 * 2. Load the page buffer with data (2x 32 bit words at a time)
738 * 3. Burn the page buffer into its intended location
739 * If the starting offset is not on a 256 byte boundary, we
740 * will need to pad the beginning of the write buffer
741 * accordingly. Likewise, if the last page does not fill the
742 * buffer, we should pad it to avoid leftover data from being
745 res = xmc4xxx_enter_page_mode(bank);
749 /* Copy the data into the page buffer*/
750 for (int i = 0; i < 256; i += 8) {
751 uint32_t w_lo = target_buffer_get_u32(bank->target, &pg_buf[i]);
752 uint32_t w_hi = target_buffer_get_u32(bank->target, &pg_buf[i + 4]);
753 LOG_DEBUG("WLO: %08"PRIx32, w_lo);
754 LOG_DEBUG("WHI: %08"PRIx32, w_hi);
756 /* Data is loaded 2x 32 bit words at a time */
757 res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_1, w_lo);
761 res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_2, w_hi);
765 /* Check for an error */
766 res = xmc4xxx_get_flash_status(bank, &status);
770 if (status & FSR_SQER_MASK) {
771 LOG_ERROR("Error loading page buffer");
776 /* The page buffer is now full, time to commit it to flash */
778 res = xmc4xxx_write_command_sequence(bank, write_cmd_seq, ARRAY_SIZE(write_cmd_seq));
779 if (res != ERROR_OK) {
780 LOG_ERROR("Unable to enter write command sequence");
784 /* Read the flash status register */
785 res = xmc4xxx_get_flash_status(bank, &status);
789 /* Check for a sequence error */
790 if (status & FSR_SQER_MASK) {
791 LOG_ERROR("Error with flash write sequence");
795 /* Make sure a flash write was triggered */
796 if (!(status & FSR_PROG_MASK)) {
797 LOG_ERROR("Failed to write flash page");
801 /* Wait for the write operation to end */
802 res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
806 /* TODO: Verify that page was written without error */
810 static int xmc4xxx_write(struct flash_bank *bank, const uint8_t *buffer,
811 uint32_t offset, uint32_t count)
813 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
816 if (bank->target->state != TARGET_HALTED) {
817 LOG_ERROR("Unable to erase, target is not halted");
818 return ERROR_TARGET_NOT_HALTED;
822 res = xmc4xxx_probe(bank);
827 /* Make sure we won't run off the end of the flash bank */
828 if ((offset + count) > (bank->size)) {
829 LOG_ERROR("Attempting to write past the end of flash");
834 /* Attempt to write the passed in buffer to flash */
835 /* Pages are written 256 bytes at a time, we need to handle
836 * scenarios where padding is required at the beginning and
839 /* page working area */
840 uint8_t tmp_buf[256] = {0};
842 /* Amount of data we'll be writing to this page */
846 remaining = MIN(count, sizeof(tmp_buf));
847 end_pad = sizeof(tmp_buf) - remaining;
849 /* Make sure we're starting on a page boundary */
850 int start_pad = offset % 256;
852 LOG_INFO("Write does not start on a 256 byte boundary. "
853 "Padding by %d bytes", start_pad);
854 memset(tmp_buf, 0xff, start_pad);
855 /* Subtract the amount of start offset from
856 * the amount of data we'll need to write */
857 remaining -= start_pad;
860 /* Remove the amount we'll be writing from the total count */
863 /* Now copy in the remaining data */
864 memcpy(&tmp_buf[start_pad], buffer, remaining);
867 LOG_INFO("Padding end of page @%08"PRIx32" by %d bytes",
868 bank->base + offset, end_pad);
869 memset(&tmp_buf[256 - end_pad], 0xff, end_pad);
872 /* Now commit this page to flash, if there was start
873 * padding, we should subtract that from the target offset */
874 res = xmc4xxx_write_page(bank, tmp_buf, (offset - start_pad), false);
875 if (res != ERROR_OK) {
876 LOG_ERROR("Unable to write flash page");
877 goto abort_write_and_exit;
880 /* Advance the buffer pointer */
883 /* Advance the offset */
887 abort_write_and_exit:
888 xmc4xxx_clear_flash_status(bank);
893 static int xmc4xxx_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
895 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
898 if (bank->target->state != TARGET_HALTED) {
899 LOG_WARNING("Cannot communicate... target not halted.");
900 return ERROR_TARGET_NOT_HALTED;
903 /* The SCU registers contain the ID of the chip */
904 int res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &scu_idcode);
905 if (res != ERROR_OK) {
906 LOG_ERROR("Cannot read device identification register.");
910 uint16_t dev_id = (scu_idcode & 0xfff0) >> 4;
911 uint16_t rev_id = scu_idcode & 0xf;
913 const char *rev_str = NULL;
953 /* XMC4500 EES AA13 with date codes before GE212
954 * had zero SCU_IDCHIP
956 dev_str = "XMC4500 EES";
976 snprintf(buf, buf_size,
977 "Cannot identify target as an XMC4xxx. SCU_ID: %"PRIx32"\n",
982 /* String to declare protection data held in the private driver */
983 char prot_str[512] = {0};
984 if (fb->read_protected)
985 snprintf(prot_str, sizeof(prot_str), "\nFlash is read protected");
987 bool otp_enabled = false;
988 for (int i = 0; i < bank->num_sectors; i++)
989 if (fb->write_prot_otp[i])
992 /* If OTP Write protection is enabled (User 2), list each
993 * sector that has it enabled */
996 strcat(prot_str, "\nOTP Protection is enabled for sectors:\n");
997 for (int i = 0; i < bank->num_sectors; i++) {
998 if (fb->write_prot_otp[i]) {
999 snprintf(otp_str, sizeof(otp_str), "- %d\n", i);
1000 strncat(prot_str, otp_str, ARRAY_SIZE(otp_str));
1005 if (rev_str != NULL)
1006 snprintf(buf, buf_size, "%s - Rev: %s%s",
1007 dev_str, rev_str, prot_str);
1009 snprintf(buf, buf_size, "%s - Rev: unknown (0x%01x)%s",
1010 dev_str, rev_id, prot_str);
1015 static int xmc4xxx_temp_unprotect(struct flash_bank *bank, int user_level)
1017 struct xmc4xxx_flash_bank *fb;
1019 uint32_t status = 0;
1021 struct xmc4xxx_command_seq temp_unprot_seq[6] = {
1022 {FLASH_CMD_TEMP_UNPROT_1, 0xAA},
1023 {FLASH_CMD_TEMP_UNPROT_2, 0x55},
1024 {FLASH_CMD_TEMP_UNPROT_3, 0xFF}, /* Needs filled in */
1025 {FLASH_CMD_TEMP_UNPROT_4, 0xFF}, /* Needs filled in */
1026 {FLASH_CMD_TEMP_UNPROT_5, 0xFF}, /* Needs filled in */
1027 {FLASH_CMD_TEMP_UNPROT_6, 0x05}
1030 if (user_level < 0 || user_level > 2) {
1031 LOG_ERROR("Invalid user level, must be 0-2");
1035 fb = bank->driver_priv;
1037 /* Fill in the user level and passwords */
1038 temp_unprot_seq[2].magic = user_level;
1039 temp_unprot_seq[3].magic = fb->pw1;
1040 temp_unprot_seq[4].magic = fb->pw2;
1042 res = xmc4xxx_write_command_sequence(bank, temp_unprot_seq,
1043 ARRAY_SIZE(temp_unprot_seq));
1044 if (res != ERROR_OK) {
1045 LOG_ERROR("Unable to write temp unprotect sequence");
1049 res = xmc4xxx_get_flash_status(bank, &status);
1050 if (res != ERROR_OK)
1053 if (status & FSR_WPRODIS0) {
1054 LOG_INFO("Flash is temporarily unprotected");
1056 LOG_INFO("Unable to disable flash protection");
1064 static int xmc4xxx_flash_unprotect(struct flash_bank *bank, int32_t level)
1069 if ((level < 0) || (level > 1)) {
1070 LOG_ERROR("Invalid user level. Must be 0-1");
1083 res = xmc4xxx_erase_sector(bank, addr, true);
1085 if (res != ERROR_OK)
1086 LOG_ERROR("Error erasing user configuration block");
1091 /* Reference: "XMC4500 Flash Protection.pptx" app note */
1092 static int xmc4xxx_flash_protect(struct flash_bank *bank, int level, bool read_protect,
1093 int first, int last)
1095 /* User configuration block buffers */
1096 uint8_t ucp0_buf[8 * sizeof(uint32_t)] = {0};
1097 uint32_t ucb_base = 0;
1098 uint32_t procon = 0;
1100 uint32_t status = 0;
1103 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1105 /* Read protect only works for user 0, make sure we don't try
1106 * to do something silly */
1107 if (level != 0 && read_protect) {
1108 LOG_ERROR("Read protection is for user level 0 only!");
1112 /* Check to see if protection is already installed for the
1113 * specified user level. If it is, the user configuration
1114 * block will need to be erased before we can continue */
1116 /* Grab the flash status register*/
1117 res = xmc4xxx_get_flash_status(bank, &status);
1118 if (res != ERROR_OK)
1123 if ((status & FSR_RPROIN_MASK) || (status & FSR_WPROIN0_MASK))
1127 if (status & FSR_WPROIN1_MASK)
1131 if (status & FSR_WPROIN2_MASK)
1137 LOG_ERROR("Flash protection is installed for user %d"
1138 " and must be removed before continuing", level);
1142 /* If this device has 12 flash sectors, protection for
1143 * sectors 10 & 11 are handled jointly. If we are trying to
1144 * write all sectors, we should decrement
1145 * last to ensure we don't write to a register bit that
1147 if ((bank->num_sectors == 12) && (last == 12))
1150 /* We need to fill out the procon register representation
1151 * that we will be writing to the device */
1152 for (int i = first; i <= last; i++)
1155 /* If read protection is requested, set the appropriate bit
1156 * (we checked that this is allowed above) */
1158 procon |= PROCON_RPRO_MASK;
1160 LOG_DEBUG("Setting flash protection with procon:");
1161 LOG_DEBUG("PROCON: %"PRIx32, procon);
1163 /* First we need to copy in the procon register to the buffer
1164 * we're going to attempt to write. This is written twice */
1165 target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], procon);
1166 target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], procon);
1168 /* Now we must copy in both flash passwords. As with the
1169 * procon data, this must be written twice (4 total words
1171 target_buffer_set_u32(bank->target, &ucp0_buf[4 * 4], fb->pw1);
1172 target_buffer_set_u32(bank->target, &ucp0_buf[5 * 4], fb->pw2);
1173 target_buffer_set_u32(bank->target, &ucp0_buf[6 * 4], fb->pw1);
1174 target_buffer_set_u32(bank->target, &ucp0_buf[7 * 4], fb->pw2);
1176 /* Finally, (if requested) we copy in the confirmation
1177 * code so that the protection is permanent and will
1178 * require a password to undo. */
1179 target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
1180 target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
1182 /* Now that the data is copied into place, we must write
1183 * these pages into flash */
1185 /* The user configuration block base depends on what level of
1186 * protection we're trying to install, select the proper one */
1189 ucb_base = UCB0_BASE;
1192 ucb_base = UCB1_BASE;
1195 ucb_base = UCB2_BASE;
1199 /* Write the user config pages */
1200 res = xmc4xxx_write_page(bank, ucp0_buf, ucb_base, true);
1201 if (res != ERROR_OK) {
1202 LOG_ERROR("Error writing user configuration block 0");
1209 static int xmc4xxx_protect(struct flash_bank *bank, int set, int first, int last)
1212 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1214 /* Check for flash passwords */
1216 LOG_ERROR("Flash passwords not set, use xmc4xxx flash_password to set them");
1220 /* We want to clear flash protection temporarily*/
1222 LOG_WARNING("Flash protection will be temporarily disabled"
1223 " for all pages (User 0 only)!");
1224 ret = xmc4xxx_temp_unprotect(bank, 0);
1228 /* Install write protection for user 0 on the specified pages */
1229 ret = xmc4xxx_flash_protect(bank, 0, false, first, last);
1234 static int xmc4xxx_protect_check(struct flash_bank *bank)
1237 uint32_t protection[3] = {0};
1238 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1240 ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON0, &protection[0]);
1241 if (ret != ERROR_OK) {
1242 LOG_ERROR("Unable to read flash User0 protection register");
1246 ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON1, &protection[1]);
1247 if (ret != ERROR_OK) {
1248 LOG_ERROR("Unable to read flash User1 protection register");
1252 ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON2, &protection[2]);
1253 if (ret != ERROR_OK) {
1254 LOG_ERROR("Unable to read flash User2 protection register");
1258 int sectors = bank->num_sectors;
1260 /* On devices with 12 sectors, sectors 10 & 11 are ptected
1261 * together instead of individually */
1265 /* Clear the protection status */
1266 for (int i = 0; i < bank->num_sectors; i++) {
1267 bank->sectors[i].is_protected = 0;
1268 fb->write_prot_otp[i] = false;
1270 fb->read_protected = false;
1272 /* The xmc4xxx series supports 3 levels of user protection
1273 * (User0, User1 (low priority), and User 2(OTP), we need to
1275 for (unsigned int i = 0; i < ARRAY_SIZE(protection); i++) {
1277 /* Check for write protection on every available
1279 for (int j = 0; j < sectors; j++) {
1280 int set = (protection[i] & (1 << j)) ? 1 : 0;
1281 bank->sectors[j].is_protected |= set;
1283 /* Handle sector 11 */
1285 bank->sectors[j + 1].is_protected |= set;
1287 /* User 2 indicates this protection is
1288 * permanent, make note in the private driver structure */
1289 if (i == 2 && set) {
1290 fb->write_prot_otp[j] = true;
1292 /* Handle sector 11 */
1294 fb->write_prot_otp[j + 1] = true;
1300 /* XMC4xxx also supports read proptection, make a note
1301 * in the private driver structure */
1302 if (protection[0] & PROCON_RPRO_MASK)
1303 fb->read_protected = true;
1308 FLASH_BANK_COMMAND_HANDLER(xmc4xxx_flash_bank_command)
1310 bank->driver_priv = malloc(sizeof(struct xmc4xxx_flash_bank));
1312 if (!bank->driver_priv)
1313 return ERROR_FLASH_OPERATION_FAILED;
1315 (void)memset(bank->driver_priv, 0, sizeof(struct xmc4xxx_flash_bank));
1320 COMMAND_HANDLER(xmc4xxx_handle_flash_password_command)
1323 struct flash_bank *bank;
1326 return ERROR_COMMAND_SYNTAX_ERROR;
1328 res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1329 if (res != ERROR_OK)
1332 struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1336 /* We skip over the flash bank */
1337 fb->pw1 = strtol(CMD_ARGV[1], NULL, 16);
1340 return ERROR_COMMAND_SYNTAX_ERROR;
1342 fb->pw2 = strtol(CMD_ARGV[2], NULL, 16);
1345 return ERROR_COMMAND_SYNTAX_ERROR;
1349 command_print(CMD_CTX, "XMC4xxx flash passwords set to:\n");
1350 command_print(CMD_CTX, "-0x%08"PRIx32"\n", fb->pw1);
1351 command_print(CMD_CTX, "-0x%08"PRIx32"\n", fb->pw2);
1355 COMMAND_HANDLER(xmc4xxx_handle_flash_unprotect_command)
1357 struct flash_bank *bank;
1362 return ERROR_COMMAND_SYNTAX_ERROR;
1364 res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1365 if (res != ERROR_OK)
1368 COMMAND_PARSE_NUMBER(s32, CMD_ARGV[1], level);
1370 res = xmc4xxx_flash_unprotect(bank, level);
1375 static const struct command_registration xmc4xxx_exec_command_handlers[] = {
1377 .name = "flash_password",
1378 .handler = xmc4xxx_handle_flash_password_command,
1379 .mode = COMMAND_EXEC,
1380 .usage = "bank_id password1 password2",
1381 .help = "Set the flash passwords used for protect operations. "
1382 "Passwords should be in standard hex form (0x00000000). "
1383 "(You must call this before any other protect commands) "
1384 "NOTE: The xmc4xxx's UCB area only allows for FOUR cycles. "
1385 "Please use protection carefully!",
1388 .name = "flash_unprotect",
1389 .handler = xmc4xxx_handle_flash_unprotect_command,
1390 .mode = COMMAND_EXEC,
1391 .usage = "bank_id user_level[0-1]",
1392 .help = "Permanently Removes flash protection (read and write) "
1393 "for the specified user level",
1394 }, COMMAND_REGISTRATION_DONE
1397 static const struct command_registration xmc4xxx_command_handlers[] = {
1400 .mode = COMMAND_ANY,
1401 .help = "xmc4xxx flash command group",
1403 .chain = xmc4xxx_exec_command_handlers,
1405 COMMAND_REGISTRATION_DONE
1408 struct flash_driver xmc4xxx_flash = {
1410 .commands = xmc4xxx_command_handlers,
1411 .flash_bank_command = xmc4xxx_flash_bank_command,
1412 .erase = xmc4xxx_erase,
1413 .write = xmc4xxx_write,
1414 .read = default_flash_read,
1415 .probe = xmc4xxx_probe,
1416 .auto_probe = xmc4xxx_probe,
1417 .erase_check = xmc4xxx_flash_blank_check,
1418 .info = xmc4xxx_get_info_command,
1419 .protect_check = xmc4xxx_protect_check,
1420 .protect = xmc4xxx_protect,