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   1 /**************************************************************************
   2 *   Copyright (C) 2015 Jeff Ciesielski <jeffciesielski@gmail.com>         *
   3 *                                                                         *
   4 *   This program is free software; you can redistribute it and/or modify  *
   5 *   it under the terms of the GNU General Public License as published by  *
   6 *   the Free Software Foundation; either version 2 of the License, or     *
   7 *   (at your option) any later version.                                   *
   8 *                                                                         *
   9 *   This program is distributed in the hope that it will be useful,       *
  10 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12 *   GNU General Public License for more details.                          *
  13 *                                                                         *
  14 *   You should have received a copy of the GNU General Public License     *
  15 *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  16 ***************************************************************************/
  17
  18 #ifdef HAVE_CONFIG_H
  19 #include "config.h"
  20 #endif
  21
  22 #include "imp.h"
  23 #include <helper/binarybuffer.h>
  24 #include <target/algorithm.h>
  25 #include <target/armv7m.h>
  26
  27 /* Maximum number of sectors */
  28 #define MAX_XMC_SECTORS 12
  29
  30 /* System control unit registers */
  31 #define SCU_REG_BASE 0x50004000
  32
  33 #define SCU_ID_CHIP 0x04
  34
  35 /* Base of the non-cached flash memory */
  36 #define PFLASH_BASE     0x0C000000
  37
  38 /* User configuration block offsets */
  39 #define UCB0_BASE       0x00000000
  40 #define UCB1_BASE       0x00000400
  41 #define UCB2_BASE       0x00000800
  42
  43 /* Flash register base */
  44 #define FLASH_REG_BASE 0x58000000
  45
  46 /* PMU ID Registers */
  47 #define FLASH_REG_PMU_ID        (FLASH_REG_BASE | 0x0508)
  48
  49 /* PMU Fields */
  50 #define PMU_MOD_REV_MASK        0xFF
  51 #define PMU_MOD_TYPE_MASK       0xFF00
  52 #define PMU_MOD_NO_MASK         0xFFFF0000
  53
  54 /* Prefetch Config */
  55 #define FLASH_REG_PREF_PCON     (FLASH_REG_BASE | 0x4000)
  56
  57 /* Prefetch Fields */
  58 #define PCON_IBYP       (1 << 0)
  59 #define PCON_IINV       (1 << 1)
  60
  61 /* Flash ID Register */
  62 #define FLASH_REG_FLASH0_ID     (FLASH_REG_BASE | 0x2008)
  63
  64 /* Flash Status Register */
  65 #define FLASH_REG_FLASH0_FSR    (FLASH_REG_BASE | 0x2010)
  66
  67 #define FSR_PBUSY       (0)
  68 #define FSR_FABUSY      (1)
  69 #define FSR_PROG        (4)
  70 #define FSR_ERASE       (5)
  71 #define FSR_PFPAGE      (6)
  72 #define FSR_PFOPER      (8)
  73 #define FSR_SQER        (10)
  74 #define FSR_PROER       (11)
  75 #define FSR_PFSBER      (12)
  76 #define FSR_PFDBER      (14)
  77 #define FSR_PROIN       (16)
  78 #define FSR_RPROIN      (18)
  79 #define FSR_RPRODIS     (19)
  80 #define FSR_WPROIN0     (21)
  81 #define FSR_WPROIN1     (22)
  82 #define FSR_WPROIN2     (23)
  83 #define FSR_WPRODIS0    (25)
  84 #define FSR_WPRODIS1    (26)
  85 #define FSR_SLM         (28)
  86 #define FSR_VER         (31)
  87
  88 #define FSR_PBUSY_MASK          (0x01 << FSR_PBUSY)
  89 #define FSR_FABUSY_MASK         (0x01 << FSR_FABUSY)
  90 #define FSR_PROG_MASK           (0x01 << FSR_PROG)
  91 #define FSR_ERASE_MASK          (0x01 << FSR_ERASE)
  92 #define FSR_PFPAGE_MASK         (0x01 << FSR_PFPAGE)
  93 #define FSR_PFOPER_MASK         (0x01 << FSR_PFOPER)
  94 #define FSR_SQER_MASK           (0x01 << FSR_SQER)
  95 #define FSR_PROER_MASK          (0x01 << FSR_PROER)
  96 #define FSR_PFSBER_MASK         (0x01 << FSR_PFSBER)
  97 #define FSR_PFDBER_MASK         (0x01 << FSR_PFDBER)
  98 #define FSR_PROIN_MASK          (0x01 << FSR_PROIN)
  99 #define FSR_RPROIN_MASK         (0x01 << FSR_RPROIN)
 100 #define FSR_RPRODIS_MASK        (0x01 << FSR_RPRODIS)
 101 #define FSR_WPROIN0_MASK        (0x01 << FSR_WPROIN0)
 102 #define FSR_WPROIN1_MASK        (0x01 << FSR_WPROIN1)
 103 #define FSR_WPROIN2_MASK        (0x01 << FSR_WPROIN2)
 104 #define FSR_WPRODIS0_MASK       (0x01 << FSR_WPRODIS0)
 105 #define FSR_WPRODIS1_MASK       (0x01 << FSR_WPRODIS1)
 106 #define FSR_SLM_MASK            (0x01 << FSR_SLM)
 107 #define FSR_VER_MASK            (0x01 << FSR_VER)
 108
 109 /* Flash Config Register */
 110 #define FLASH_REG_FLASH0_FCON   (FLASH_REG_BASE | 0x2014)
 111
 112 #define FCON_WSPFLASH           (0)
 113 #define FCON_WSECPF             (4)
 114 #define FCON_IDLE               (13)
 115 #define FCON_ESLDIS             (14)
 116 #define FCON_SLEEP              (15)
 117 #define FCON_RPA                (16)
 118 #define FCON_DCF                (17)
 119 #define FCON_DDF                (18)
 120 #define FCON_VOPERM             (24)
 121 #define FCON_SQERM              (25)
 122 #define FCON_PROERM             (26)
 123 #define FCON_PFSBERM            (27)
 124 #define FCON_PFDBERM            (29)
 125 #define FCON_EOBM               (31)
 126
 127 #define FCON_WSPFLASH_MASK      (0x0f << FCON_WSPFLASH)
 128 #define FCON_WSECPF_MASK        (0x01 << FCON_WSECPF)
 129 #define FCON_IDLE_MASK          (0x01 << FCON_IDLE)
 130 #define FCON_ESLDIS_MASK        (0x01 << FCON_ESLDIS)
 131 #define FCON_SLEEP_MASK         (0x01 << FCON_SLEEP)
 132 #define FCON_RPA_MASK           (0x01 << FCON_RPA)
 133 #define FCON_DCF_MASK           (0x01 << FCON_DCF)
 134 #define FCON_DDF_MASK           (0x01 << FCON_DDF)
 135 #define FCON_VOPERM_MASK        (0x01 << FCON_VOPERM)
 136 #define FCON_SQERM_MASK         (0x01 << FCON_SQERM)
 137 #define FCON_PROERM_MASK        (0x01 << FCON_PROERM)
 138 #define FCON_PFSBERM_MASK       (0x01 << FCON_PFSBERM)
 139 #define FCON_PFDBERM_MASK       (0x01 << FCON_PFDBERM)
 140 #define FCON_EOBM_MASK          (0x01 << FCON_EOBM)
 141
 142 /* Flash Margin Control Register */
 143 #define FLASH_REG_FLASH0_MARP   (FLASH_REG_BASE | 0x2018)
 144
 145 #define MARP_MARGIN             (0)
 146 #define MARP_TRAPDIS            (15)
 147
 148 #define MARP_MARGIN_MASK        (0x0f << MARP_MARGIN)
 149 #define MARP_TRAPDIS_MASK       (0x01 << MARP_TRAPDIS)
 150
 151 /* Flash Protection Registers */
 152 #define FLASH_REG_FLASH0_PROCON0        (FLASH_REG_BASE | 0x2020)
 153 #define FLASH_REG_FLASH0_PROCON1        (FLASH_REG_BASE | 0x2024)
 154 #define FLASH_REG_FLASH0_PROCON2        (FLASH_REG_BASE | 0x2028)
 155
 156 #define PROCON_S0L             (0)
 157 #define PROCON_S1L             (1)
 158 #define PROCON_S2L             (2)
 159 #define PROCON_S3L             (3)
 160 #define PROCON_S4L             (4)
 161 #define PROCON_S5L             (5)
 162 #define PROCON_S6L             (6)
 163 #define PROCON_S7L             (7)
 164 #define PROCON_S8L             (8)
 165 #define PROCON_S9L             (9)
 166 #define PROCON_S10_S11L        (10)
 167 #define PROCON_RPRO            (15)
 168
 169 #define PROCON_S0L_MASK        (0x01 << PROCON_S0L)
 170 #define PROCON_S1L_MASK        (0x01 << PROCON_S1L)
 171 #define PROCON_S2L_MASK        (0x01 << PROCON_S2L)
 172 #define PROCON_S3L_MASK        (0x01 << PROCON_S3L)
 173 #define PROCON_S4L_MASK        (0x01 << PROCON_S4L)
 174 #define PROCON_S5L_MASK        (0x01 << PROCON_S5L)
 175 #define PROCON_S6L_MASK        (0x01 << PROCON_S6L)
 176 #define PROCON_S7L_MASK        (0x01 << PROCON_S7L)
 177 #define PROCON_S8L_MASK        (0x01 << PROCON_S8L)
 178 #define PROCON_S9L_MASK        (0x01 << PROCON_S9L)
 179 #define PROCON_S10_S11L_MASK   (0x01 << PROCON_S10_S11L)
 180 #define PROCON_RPRO_MASK       (0x01 << PROCON_RPRO)
 181
 182 #define FLASH_PROTECT_CONFIRMATION_CODE 0x8AFE15C3
 183
 184 /* Flash controller configuration values */
 185 #define FLASH_ID_XMC4500        0xA2
 186 #define FLASH_ID_XMC4300_XMC4700_4800   0x92
 187 #define FLASH_ID_XMC4100_4200   0x9C
 188 #define FLASH_ID_XMC4400        0x9F
 189
 190 /* Timeouts */
 191 #define FLASH_OP_TIMEOUT 5000
 192
 193 /* Flash commands (write/erase/protect) are performed using special
 194  * command sequences that are written to magic addresses in the flash controller */
 195 /* Command sequence addresses.  See reference manual, section 8: Flash Command Sequences */
 196 #define FLASH_CMD_ERASE_1 0x0C005554
 197 #define FLASH_CMD_ERASE_2 0x0C00AAA8
 198 #define FLASH_CMD_ERASE_3 FLASH_CMD_ERASE_1
 199 #define FLASH_CMD_ERASE_4 FLASH_CMD_ERASE_1
 200 #define FLASH_CMD_ERASE_5 FLASH_CMD_ERASE_2
 201 /* ERASE_6 is the sector base address */
 202
 203 #define FLASH_CMD_CLEAR_STATUS FLASH_CMD_ERASE_1
 204
 205 #define FLASH_CMD_ENTER_PAGEMODE FLASH_CMD_ERASE_1
 206
 207 #define FLASH_CMD_LOAD_PAGE_1 0x0C0055F0
 208 #define FLASH_CMD_LOAD_PAGE_2 0x0C0055F4
 209
 210 #define FLASH_CMD_WRITE_PAGE_1 FLASH_CMD_ERASE_1
 211 #define FLASH_CMD_WRITE_PAGE_2 FLASH_CMD_ERASE_2
 212 #define FLASH_CMD_WRITE_PAGE_3 FLASH_CMD_ERASE_1
 213 /* WRITE_PAGE_4 is the page base address */
 214
 215 #define FLASH_CMD_TEMP_UNPROT_1 FLASH_CMD_ERASE_1
 216 #define FLASH_CMD_TEMP_UNPROT_2 FLASH_CMD_ERASE_2
 217 #define FLASH_CMD_TEMP_UNPROT_3 0x0C00553C
 218 #define FLASH_CMD_TEMP_UNPROT_4 FLASH_CMD_ERASE_2
 219 #define FLASH_CMD_TEMP_UNPROT_5 FLASH_CMD_ERASE_2
 220 #define FLASH_CMD_TEMP_UNPROT_6 0x0C005558
 221
 222 struct xmc4xxx_flash_bank {
 223         bool probed;
 224
 225         /* We need the flash controller ID to choose the sector layout */
 226         uint32_t fcon_id;
 227
 228         /* Passwords used for protection operations */
 229         uint32_t pw1;
 230         uint32_t pw2;
 231         bool pw_set;
 232
 233         /* Protection flags */
 234         bool read_protected;
 235
 236         bool write_prot_otp[MAX_XMC_SECTORS];
 237 };
 238
 239 struct xmc4xxx_command_seq {
 240         uint32_t address;
 241         uint32_t magic;
 242 };
 243
 244 /* Sector capacities.  See section 8 of xmc4x00_rm */
 245 static const unsigned int sector_capacity_8[8] = {
 246         16, 16, 16, 16, 16, 16, 16, 128
 247 };
 248
 249 static const unsigned int sector_capacity_9[9] = {
 250         16, 16, 16, 16, 16, 16, 16, 128, 256
 251 };
 252
 253 static const unsigned int sector_capacity_12[12] = {
 254         16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256
 255 };
 256
 257 static const unsigned int sector_capacity_16[16] = {
 258         16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256, 256, 256, 256, 256
 259 };
 260
 261 static int xmc4xxx_write_command_sequence(struct flash_bank *bank,
 262                                          struct xmc4xxx_command_seq *seq,
 263                                          int seq_len)
 264 {
 265         int res = ERROR_OK;
 266
 267         for (int i = 0; i < seq_len; i++) {
 268                 res = target_write_u32(bank->target, seq[i].address,
 269                                        seq[i].magic);
 270                 if (res != ERROR_OK)
 271                         return res;
 272         }
 273
 274         return ERROR_OK;
 275 }
 276
 277 static int xmc4xxx_load_bank_layout(struct flash_bank *bank)
 278 {
 279         const unsigned int *capacity = NULL;
 280
 281         /* At this point, we know which flash controller ID we're
 282          * talking to and simply need to fill out the bank structure accordingly */
 283         LOG_DEBUG("%u sectors", bank->num_sectors);
 284
 285         switch (bank->num_sectors) {
 286         case 8:
 287                 capacity = sector_capacity_8;
 288                 break;
 289         case 9:
 290                 capacity = sector_capacity_9;
 291                 break;
 292         case 12:
 293                 capacity = sector_capacity_12;
 294                 break;
 295         case 16:
 296                 capacity = sector_capacity_16;
 297                 break;
 298         default:
 299                 LOG_ERROR("Unexpected number of sectors, %u\n",
 300                           bank->num_sectors);
 301                 return ERROR_FAIL;
 302         }
 303
 304         /* This looks like a bank that we understand, now we know the
 305          * corresponding sector capacities and we can add those up into the
 306          * bank size. */
 307         uint32_t total_offset = 0;
 308         bank->sectors = calloc(bank->num_sectors,
 309                                sizeof(struct flash_sector));
 310         for (unsigned int i = 0; i < bank->num_sectors; i++) {
 311                 bank->sectors[i].size = capacity[i] * 1024;
 312                 bank->sectors[i].offset = total_offset;
 313                 bank->sectors[i].is_erased = -1;
 314                 bank->sectors[i].is_protected = -1;
 315
 316                 bank->size += bank->sectors[i].size;
 317                 LOG_DEBUG("\t%d: %uk", i, capacity[i]);
 318                 total_offset += bank->sectors[i].size;
 319         }
 320
 321         /* This part doesn't follow the typical standard of 0xff
 322          * being the erased value.*/
 323         bank->default_padded_value = bank->erased_value = 0x00;
 324
 325         return ERROR_OK;
 326 }
 327
 328 static int xmc4xxx_probe(struct flash_bank *bank)
 329 {
 330         int res;
 331         uint32_t devid, config;
 332         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
 333         uint8_t flash_id;
 334
 335         if (fb->probed)
 336                 return ERROR_OK;
 337
 338         /* It's not possible for the DAP to access the OTP locations needed for
 339          * probing the part info and Flash geometry so we require that the target
 340          * be halted before proceeding. */
 341         if (bank->target->state != TARGET_HALTED) {
 342                 LOG_WARNING("Cannot communicate... target not halted.");
 343                 return ERROR_TARGET_NOT_HALTED;
 344         }
 345
 346         /* The SCU registers contain the ID of the chip */
 347         res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &devid);
 348         if (res != ERROR_OK) {
 349                 LOG_ERROR("Cannot read device identification register.");
 350                 return res;
 351         }
 352
 353         /* Make sure this is a XMC4000 family device */
 354         if ((devid & 0xF0000) != 0x40000 && devid != 0) {
 355                 LOG_ERROR("Platform ID doesn't match XMC4xxx: 0x%08" PRIx32, devid);
 356                 return ERROR_FAIL;
 357         }
 358
 359         LOG_DEBUG("Found XMC4xxx with devid: 0x%08" PRIx32, devid);
 360
 361         /* Now sanity-check the Flash controller itself. */
 362         res = target_read_u32(bank->target, FLASH_REG_FLASH0_ID,
 363                         &config);
 364         if (res != ERROR_OK) {
 365                 LOG_ERROR("Cannot read Flash bank configuration.");
 366                 return res;
 367         }
 368         flash_id = (config & 0xff0000) >> 16;
 369
 370         /* The Flash configuration register is our only means of
 371          * determining the sector layout. We need to make sure that
 372          * we understand the type of controller we're dealing with */
 373         switch (flash_id) {
 374         case FLASH_ID_XMC4100_4200:
 375                 bank->num_sectors = 8;
 376                 LOG_DEBUG("XMC4xxx: XMC4100/4200 detected.");
 377                 break;
 378         case FLASH_ID_XMC4400:
 379                 bank->num_sectors = 9;
 380                 LOG_DEBUG("XMC4xxx: XMC4400 detected.");
 381                 break;
 382         case FLASH_ID_XMC4500:
 383                 bank->num_sectors = 12;
 384                 LOG_DEBUG("XMC4xxx: XMC4500 detected.");
 385                 break;
 386         case FLASH_ID_XMC4300_XMC4700_4800:
 387                 bank->num_sectors = 16;
 388                 LOG_DEBUG("XMC4xxx: XMC4700/4800 detected.");
 389                 break;
 390         default:
 391                 LOG_ERROR("XMC4xxx: Unexpected flash ID. got %02" PRIx8,
 392                           flash_id);
 393                 return ERROR_FAIL;
 394         }
 395
 396         /* Retrieve information about the particular bank we're probing and fill in
 397          * the bank structure accordingly. */
 398         res = xmc4xxx_load_bank_layout(bank);
 399         if (res == ERROR_OK) {
 400                 /* We're done */
 401                 fb->probed = true;
 402         } else {
 403                 LOG_ERROR("Unable to load bank information.");
 404                 return ERROR_FAIL;
 405         }
 406
 407         return ERROR_OK;
 408 }
 409
 410 static int xmc4xxx_get_sector_start_addr(struct flash_bank *bank,
 411                 unsigned int sector, uint32_t *ret_addr)
 412 {
 413         /* Make sure we understand this sector */
 414         if (sector > bank->num_sectors)
 415                 return ERROR_FAIL;
 416
 417         *ret_addr = bank->base + bank->sectors[sector].offset;
 418
 419         return ERROR_OK;
 420
 421 }
 422
 423 static int xmc4xxx_clear_flash_status(struct flash_bank *bank)
 424 {
 425         int res;
 426         /* TODO: Do we need to check for sequence error? */
 427         LOG_INFO("Clearing flash status");
 428         res = target_write_u32(bank->target, FLASH_CMD_CLEAR_STATUS,
 429                                0xF5);
 430         if (res != ERROR_OK) {
 431                 LOG_ERROR("Unable to write erase command sequence");
 432                 return res;
 433         }
 434
 435         return ERROR_OK;
 436 }
 437
 438 static int xmc4xxx_get_flash_status(struct flash_bank *bank, uint32_t *status)
 439 {
 440         int res;
 441
 442         res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, status);
 443
 444         if (res != ERROR_OK)
 445                 LOG_ERROR("Cannot read flash status register.");
 446
 447         return res;
 448 }
 449
 450 static int xmc4xxx_wait_status_busy(struct flash_bank *bank, int timeout)
 451 {
 452         int res;
 453         uint32_t status;
 454
 455         res = xmc4xxx_get_flash_status(bank, &status);
 456         if (res != ERROR_OK)
 457                 return res;
 458
 459         /* While the flash controller is busy, wait */
 460         while (status & FSR_PBUSY_MASK) {
 461                 res = xmc4xxx_get_flash_status(bank, &status);
 462                 if (res != ERROR_OK)
 463                         return res;
 464
 465                 if (timeout-- <= 0) {
 466                         LOG_ERROR("Timed out waiting for flash");
 467                         return ERROR_FAIL;
 468                 }
 469                 alive_sleep(1);
 470                 keep_alive();
 471         }
 472
 473         if (status & FSR_PROER_MASK) {
 474                 LOG_ERROR("XMC4xxx flash protected");
 475                 res = ERROR_FAIL;
 476         }
 477
 478         return res;
 479 }
 480
 481 static int xmc4xxx_erase_sector(struct flash_bank *bank, uint32_t address,
 482                                 bool user_config)
 483 {
 484         int res;
 485         uint32_t status;
 486
 487         /* See reference manual table 8.4: Command Sequences for Flash Control */
 488         struct xmc4xxx_command_seq erase_cmd_seq[6] = {
 489                 {FLASH_CMD_ERASE_1, 0xAA},
 490                 {FLASH_CMD_ERASE_2, 0x55},
 491                 {FLASH_CMD_ERASE_3, 0x80},
 492                 {FLASH_CMD_ERASE_4, 0xAA},
 493                 {FLASH_CMD_ERASE_5, 0x55},
 494                 {0xFF,              0xFF} /* Needs filled in */
 495         };
 496
 497         /* We need to fill in the base address of the sector we'll be
 498          * erasing, as well as the magic code that determines whether
 499          * this is a standard flash sector or a user configuration block */
 500
 501         erase_cmd_seq[5].address = address;
 502         if (user_config) {
 503                 /* Removing flash protection requires the addition of
 504                  * the base address */
 505                 erase_cmd_seq[5].address += bank->base;
 506                 erase_cmd_seq[5].magic = 0xC0;
 507         } else {
 508                 erase_cmd_seq[5].magic = 0x30;
 509         }
 510
 511         res = xmc4xxx_write_command_sequence(bank, erase_cmd_seq,
 512                                              ARRAY_SIZE(erase_cmd_seq));
 513         if (res != ERROR_OK)
 514                 return res;
 515
 516         /* Read the flash status register */
 517         res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, &status);
 518         if (res != ERROR_OK) {
 519                 LOG_ERROR("Cannot read flash status register.");
 520                 return res;
 521         }
 522
 523         /* Check for a sequence error */
 524         if (status & FSR_SQER_MASK) {
 525                 LOG_ERROR("Error with flash erase sequence");
 526                 return ERROR_FAIL;
 527         }
 528
 529         /* Make sure a flash erase was triggered */
 530         if (!(status & FSR_ERASE_MASK)) {
 531                 LOG_ERROR("Flash failed to erase");
 532                 return ERROR_FAIL;
 533         }
 534
 535         /* Now we must wait for the erase operation to end */
 536         res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
 537
 538         return res;
 539 }
 540
 541 static int xmc4xxx_erase(struct flash_bank *bank, unsigned int first,
 542                 unsigned int last)
 543 {
 544         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
 545         int res;
 546
 547         if (bank->target->state != TARGET_HALTED) {
 548                 LOG_ERROR("Unable to erase, target is not halted");
 549                 return ERROR_TARGET_NOT_HALTED;
 550         }
 551
 552         if (!fb->probed) {
 553                 res = xmc4xxx_probe(bank);
 554                 if (res != ERROR_OK)
 555                         return res;
 556         }
 557
 558         uint32_t tmp_addr;
 559         /* Loop through the sectors and erase each one */
 560         for (unsigned int i = first; i <= last; i++) {
 561                 res = xmc4xxx_get_sector_start_addr(bank, i, &tmp_addr);
 562                 if (res != ERROR_OK) {
 563                         LOG_ERROR("Invalid sector %u", i);
 564                         return res;
 565                 }
 566
 567                 LOG_DEBUG("Erasing sector %u @ 0x%08"PRIx32, i, tmp_addr);
 568
 569                 res = xmc4xxx_erase_sector(bank, tmp_addr, false);
 570                 if (res != ERROR_OK) {
 571                         LOG_ERROR("Unable to write erase command sequence");
 572                         goto clear_status_and_exit;
 573                 }
 574
 575                 /* Now we must wait for the erase operation to end */
 576                 res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
 577
 578                 if (res != ERROR_OK)
 579                         goto clear_status_and_exit;
 580
 581                 bank->sectors[i].is_erased = 1;
 582         }
 583
 584 clear_status_and_exit:
 585         res = xmc4xxx_clear_flash_status(bank);
 586         return res;
 587
 588 }
 589
 590 static int xmc4xxx_enter_page_mode(struct flash_bank *bank)
 591 {
 592         int res;
 593         uint32_t status;
 594
 595         res = target_write_u32(bank->target, FLASH_CMD_ENTER_PAGEMODE, 0x50);
 596         if (res != ERROR_OK) {
 597                 LOG_ERROR("Unable to write enter page mode command");
 598                 return ERROR_FAIL;
 599         }
 600
 601         res = xmc4xxx_get_flash_status(bank, &status);
 602
 603         if (res != ERROR_OK)
 604                 return res;
 605
 606         /* Make sure we're in page mode */
 607         if (!(status & FSR_PFPAGE_MASK)) {
 608                 LOG_ERROR("Unable to enter page mode");
 609                 return ERROR_FAIL;
 610         }
 611
 612         /* Make sure we didn't encounter a sequence error */
 613         if (status & FSR_SQER_MASK) {
 614                 LOG_ERROR("Sequence error while entering page mode");
 615                 return ERROR_FAIL;
 616         }
 617
 618         return res;
 619 }
 620
 621 static int xmc4xxx_write_page(struct flash_bank *bank, const uint8_t *pg_buf,
 622                               uint32_t offset, bool user_config)
 623 {
 624         int res;
 625         uint32_t status;
 626
 627         /* Base of the flash write command */
 628         struct xmc4xxx_command_seq write_cmd_seq[4] = {
 629                 {FLASH_CMD_WRITE_PAGE_1, 0xAA},
 630                 {FLASH_CMD_WRITE_PAGE_2, 0x55},
 631                 {FLASH_CMD_WRITE_PAGE_3, 0xFF}, /* Needs filled in */
 632                 {0xFF,                   0xFF}  /* Needs filled in */
 633         };
 634
 635         /* The command sequence differs depending on whether this is
 636          * being written to standard flash or the user configuration
 637          * area */
 638         if (user_config)
 639                 write_cmd_seq[2].magic = 0xC0;
 640         else
 641                 write_cmd_seq[2].magic = 0xA0;
 642
 643         /* Finally, we need to add the address that this page will be
 644          * written to */
 645         write_cmd_seq[3].address = bank->base + offset;
 646         write_cmd_seq[3].magic = 0xAA;
 647
 648
 649         /* Flash pages are written 256 bytes at a time.  For each 256
 650          * byte chunk, we need to:
 651          * 1. Enter page mode. This activates the flash write buffer
 652          * 2. Load the page buffer with data (2x 32 bit words at a time)
 653          * 3. Burn the page buffer into its intended location
 654          * If the starting offset is not on a 256 byte boundary, we
 655          * will need to pad the beginning of the write buffer
 656          * accordingly. Likewise, if the last page does not fill the
 657          * buffer, we should pad it to avoid leftover data from being
 658          * written to flash
 659          */
 660         res = xmc4xxx_enter_page_mode(bank);
 661         if (res != ERROR_OK)
 662                 return res;
 663
 664         /* Copy the data into the page buffer*/
 665         for (int i = 0; i < 256; i += 8) {
 666                 uint32_t w_lo = target_buffer_get_u32(bank->target, &pg_buf[i]);
 667                 uint32_t w_hi = target_buffer_get_u32(bank->target, &pg_buf[i + 4]);
 668                 LOG_DEBUG("WLO: %08"PRIx32, w_lo);
 669                 LOG_DEBUG("WHI: %08"PRIx32, w_hi);
 670
 671                 /* Data is loaded 2x 32 bit words at a time */
 672                 res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_1, w_lo);
 673                 if (res != ERROR_OK)
 674                         return res;
 675
 676                 res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_2, w_hi);
 677                 if (res != ERROR_OK)
 678                         return res;
 679
 680                 /* Check for an error */
 681                 res = xmc4xxx_get_flash_status(bank, &status);
 682                 if (res != ERROR_OK)
 683                         return res;
 684
 685                 if (status & FSR_SQER_MASK) {
 686                         LOG_ERROR("Error loading page buffer");
 687                         return ERROR_FAIL;
 688                 }
 689         }
 690
 691         /* The page buffer is now full, time to commit it to flash */
 692
 693         res = xmc4xxx_write_command_sequence(bank, write_cmd_seq, ARRAY_SIZE(write_cmd_seq));
 694         if (res != ERROR_OK) {
 695                 LOG_ERROR("Unable to enter write command sequence");
 696                 return res;
 697         }
 698
 699         /* Read the flash status register */
 700         res = xmc4xxx_get_flash_status(bank, &status);
 701         if (res != ERROR_OK)
 702                 return res;
 703
 704         /* Check for a sequence error */
 705         if (status & FSR_SQER_MASK) {
 706                 LOG_ERROR("Error with flash write sequence");
 707                 return ERROR_FAIL;
 708         }
 709
 710         /* Make sure a flash write was triggered */
 711         if (!(status & FSR_PROG_MASK)) {
 712                 LOG_ERROR("Failed to write flash page");
 713                 return ERROR_FAIL;
 714         }
 715
 716         /* Wait for the write operation to end */
 717         res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
 718         if (res != ERROR_OK)
 719                 return res;
 720
 721         /* TODO: Verify that page was written without error */
 722         return res;
 723 }
 724
 725 static int xmc4xxx_write(struct flash_bank *bank, const uint8_t *buffer,
 726                          uint32_t offset, uint32_t count)
 727 {
 728         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
 729         int res = ERROR_OK;
 730
 731         if (bank->target->state != TARGET_HALTED) {
 732                 LOG_ERROR("Unable to erase, target is not halted");
 733                 return ERROR_TARGET_NOT_HALTED;
 734         }
 735
 736         if (!fb->probed) {
 737                 res = xmc4xxx_probe(bank);
 738                 if (res != ERROR_OK)
 739                         return res;
 740         }
 741
 742         /* Make sure we won't run off the end of the flash bank */
 743         if ((offset + count) > (bank->size)) {
 744                 LOG_ERROR("Attempting to write past the end of flash");
 745                 return ERROR_FAIL;
 746         }
 747
 748
 749         /* Attempt to write the passed in buffer to flash */
 750         /* Pages are written 256 bytes at a time, we need to handle
 751          * scenarios where padding is required at the beginning and
 752          * end of a page */
 753         while (count) {
 754                 /* page working area */
 755                 uint8_t tmp_buf[256] = {0};
 756
 757                 /* Amount of data we'll be writing to this page */
 758                 int remaining;
 759                 int end_pad;
 760
 761                 remaining = MIN(count, sizeof(tmp_buf));
 762                 end_pad   = sizeof(tmp_buf) - remaining;
 763
 764                 /* Make sure we're starting on a page boundary */
 765                 int start_pad = offset % 256;
 766                 if (start_pad) {
 767                         LOG_INFO("Write does not start on a 256 byte boundary. "
 768                                  "Padding by %d bytes", start_pad);
 769                         memset(tmp_buf, 0xff, start_pad);
 770                         /* Subtract the amount of start offset from
 771                          * the amount of data we'll need to write */
 772                         remaining -= start_pad;
 773                 }
 774
 775                 /* Remove the amount we'll be writing from the total count */
 776                 count -= remaining;
 777
 778                 /* Now copy in the remaining data */
 779                 memcpy(&tmp_buf[start_pad], buffer, remaining);
 780
 781                 if (end_pad) {
 782                         LOG_INFO("Padding end of page @" TARGET_ADDR_FMT " by %d bytes",
 783                                  bank->base + offset, end_pad);
 784                         memset(&tmp_buf[256 - end_pad], 0xff, end_pad);
 785                 }
 786
 787                 /* Now commit this page to flash, if there was start
 788                  * padding, we should subtract that from the target offset */
 789                 res = xmc4xxx_write_page(bank, tmp_buf, (offset - start_pad), false);
 790                 if (res != ERROR_OK) {
 791                         LOG_ERROR("Unable to write flash page");
 792                         goto abort_write_and_exit;
 793                 }
 794
 795                 /* Advance the buffer pointer */
 796                 buffer += remaining;
 797
 798                 /* Advance the offset */
 799                 offset += remaining;
 800         }
 801
 802 abort_write_and_exit:
 803         xmc4xxx_clear_flash_status(bank);
 804         return res;
 805
 806 }
 807
 808 static int xmc4xxx_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
 809 {
 810         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
 811         uint32_t scu_idcode;
 812
 813         if (bank->target->state != TARGET_HALTED) {
 814                 LOG_WARNING("Cannot communicate... target not halted.");
 815                 return ERROR_TARGET_NOT_HALTED;
 816         }
 817
 818         /* The SCU registers contain the ID of the chip */
 819         int res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &scu_idcode);
 820         if (res != ERROR_OK) {
 821                 LOG_ERROR("Cannot read device identification register.");
 822                 return res;
 823         }
 824
 825         uint16_t dev_id = (scu_idcode & 0xfff0) >> 4;
 826         uint16_t rev_id = scu_idcode & 0xf;
 827         const char *dev_str;
 828         const char *rev_str = NULL;
 829
 830         switch (dev_id) {
 831         case 0x100:
 832                 dev_str = "XMC4100";
 833
 834                 switch (rev_id) {
 835                 case 0x1:
 836                         rev_str = "AA";
 837                         break;
 838                 case 0x2:
 839                         rev_str = "AB";
 840                         break;
 841                 }
 842                 break;
 843         case 0x200:
 844                 dev_str = "XMC4200";
 845
 846                 switch (rev_id) {
 847                 case 0x1:
 848                         rev_str = "AA";
 849                         break;
 850                 case 0x2:
 851                         rev_str = "AB";
 852                         break;
 853                 }
 854                 break;
 855         case 0x300:
 856                 dev_str = "XMC4300";
 857
 858                 switch (rev_id) {
 859                 case 0x1:
 860                         rev_str = "AA";
 861                 }
 862                 break;
 863         case 0x400:
 864                 dev_str = "XMC4400";
 865
 866                 switch (rev_id) {
 867                 case 0x1:
 868                         rev_str = "AA";
 869                         break;
 870                 case 0x2:
 871                         rev_str = "AB";
 872                         break;
 873                 }
 874                 break;
 875         case 0:
 876                 /* XMC4500 EES AA13 with date codes before GE212
 877                  * had zero SCU_IDCHIP
 878                  */
 879                 dev_str = "XMC4500 EES";
 880                 rev_str = "AA13";
 881                 break;
 882         case 0x500:
 883                 dev_str = "XMC4500";
 884
 885                 switch (rev_id) {
 886                 case 0x2:
 887                         rev_str = "AA";
 888                         break;
 889                 case 0x3:
 890                         rev_str = "AB";
 891                         break;
 892                 case 0x4:
 893                         rev_str = "AC";
 894                         break;
 895                 }
 896                 break;
 897         case 0x700:
 898                 dev_str = "XMC4700";
 899
 900                 switch (rev_id) {
 901                 case 0x1:
 902                         rev_str = "EES-AA";
 903                         break;
 904                 }
 905                 break;
 906         case 0x800:
 907                 dev_str = "XMC4800";
 908
 909                 switch (rev_id) {
 910                 case 0x1:
 911                         rev_str = "EES-AA";
 912                         break;
 913                 }
 914                 break;
 915
 916         default:
 917                 snprintf(buf, buf_size,
 918                          "Cannot identify target as an XMC4xxx. SCU_ID: %"PRIx32"\n",
 919                          scu_idcode);
 920                 return ERROR_OK;
 921         }
 922
 923         /* String to declare protection data held in the private driver */
 924         char prot_str[512] = {0};
 925         if (fb->read_protected)
 926                 snprintf(prot_str, sizeof(prot_str), "\nFlash is read protected");
 927
 928         bool otp_enabled = false;
 929         for (unsigned int i = 0; i < bank->num_sectors; i++)
 930                 if (fb->write_prot_otp[i])
 931                         otp_enabled = true;
 932
 933         /* If OTP Write protection is enabled (User 2), list each
 934          * sector that has it enabled */
 935         char otp_str[14];
 936         if (otp_enabled) {
 937                 strcat(prot_str, "\nOTP Protection is enabled for sectors:\n");
 938                 for (unsigned int i = 0; i < bank->num_sectors; i++) {
 939                         if (fb->write_prot_otp[i]) {
 940                                 snprintf(otp_str, sizeof(otp_str), "- %d\n", i);
 941                                 strncat(prot_str, otp_str, sizeof(prot_str) - strlen(prot_str) - 1);
 942                         }
 943                 }
 944         }
 945
 946         if (rev_str != NULL)
 947                 snprintf(buf, buf_size, "%s - Rev: %s%s",
 948                          dev_str, rev_str, prot_str);
 949         else
 950                 snprintf(buf, buf_size, "%s - Rev: unknown (0x%01x)%s",
 951                          dev_str, rev_id, prot_str);
 952
 953         return ERROR_OK;
 954 }
 955
 956 static int xmc4xxx_temp_unprotect(struct flash_bank *bank, int user_level)
 957 {
 958         struct xmc4xxx_flash_bank *fb;
 959         int res = ERROR_OK;
 960         uint32_t status = 0;
 961
 962         struct xmc4xxx_command_seq temp_unprot_seq[6] = {
 963                 {FLASH_CMD_TEMP_UNPROT_1, 0xAA},
 964                 {FLASH_CMD_TEMP_UNPROT_2, 0x55},
 965                 {FLASH_CMD_TEMP_UNPROT_3, 0xFF}, /* Needs filled in */
 966                 {FLASH_CMD_TEMP_UNPROT_4, 0xFF}, /* Needs filled in */
 967                 {FLASH_CMD_TEMP_UNPROT_5, 0xFF}, /* Needs filled in */
 968                 {FLASH_CMD_TEMP_UNPROT_6, 0x05}
 969         };
 970
 971         if (user_level < 0 || user_level > 2) {
 972                 LOG_ERROR("Invalid user level, must be 0-2");
 973                 return ERROR_FAIL;
 974         }
 975
 976         fb = bank->driver_priv;
 977
 978         /* Fill in the user level and passwords */
 979         temp_unprot_seq[2].magic = user_level;
 980         temp_unprot_seq[3].magic = fb->pw1;
 981         temp_unprot_seq[4].magic = fb->pw2;
 982
 983         res = xmc4xxx_write_command_sequence(bank, temp_unprot_seq,
 984                                              ARRAY_SIZE(temp_unprot_seq));
 985         if (res != ERROR_OK) {
 986                 LOG_ERROR("Unable to write temp unprotect sequence");
 987                 return res;
 988         }
 989
 990         res = xmc4xxx_get_flash_status(bank, &status);
 991         if (res != ERROR_OK)
 992                 return res;
 993
 994         if (status & FSR_WPRODIS0) {
 995                 LOG_INFO("Flash is temporarily unprotected");
 996         } else {
 997                 LOG_INFO("Unable to disable flash protection");
 998                 res = ERROR_FAIL;
 999         }
1000
1001
1002         return res;
1003 }
1004
1005 static int xmc4xxx_flash_unprotect(struct flash_bank *bank, int32_t level)
1006 {
1007         uint32_t addr;
1008         int res;
1009
1010         switch (level) {
1011         case 0:
1012                 addr = UCB0_BASE;
1013                 break;
1014         case 1:
1015                 addr = UCB1_BASE;
1016                 break;
1017         default:
1018                 LOG_ERROR("Invalid user level. Must be 0-1");
1019                 return ERROR_FAIL;
1020         }
1021
1022         res = xmc4xxx_erase_sector(bank, addr, true);
1023
1024         if (res != ERROR_OK)
1025                 LOG_ERROR("Error erasing user configuration block");
1026
1027         return res;
1028 }
1029
1030 /* Reference: "XMC4500 Flash Protection.pptx" app note */
1031 static int xmc4xxx_flash_protect(struct flash_bank *bank, int level, bool read_protect,
1032                 unsigned int first, unsigned int last)
1033 {
1034         /* User configuration block buffers */
1035         uint8_t ucp0_buf[8 * sizeof(uint32_t)] = {0};
1036         uint32_t ucb_base = 0;
1037         uint32_t procon = 0;
1038         int res = ERROR_OK;
1039         uint32_t status = 0;
1040         bool proin = false;
1041
1042         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1043
1044         /* Read protect only works for user 0, make sure we don't try
1045          * to do something silly */
1046         if (level != 0 && read_protect) {
1047                 LOG_ERROR("Read protection is for user level 0 only!");
1048                 return ERROR_FAIL;
1049         }
1050
1051         /* Check to see if protection is already installed for the
1052          * specified user level.  If it is, the user configuration
1053          * block will need to be erased before we can continue */
1054
1055         /* Grab the flash status register*/
1056         res = xmc4xxx_get_flash_status(bank, &status);
1057         if (res != ERROR_OK)
1058                 return res;
1059
1060         switch (level) {
1061         case 0:
1062                 if ((status & FSR_RPROIN_MASK) || (status & FSR_WPROIN0_MASK))
1063                         proin = true;
1064                 break;
1065         case 1:
1066                 if (status & FSR_WPROIN1_MASK)
1067                         proin = true;
1068                 break;
1069         case 2:
1070                 if (status & FSR_WPROIN2_MASK)
1071                         proin = true;
1072                 break;
1073         }
1074
1075         if (proin) {
1076                 LOG_ERROR("Flash protection is installed for user %d"
1077                           " and must be removed before continuing", level);
1078                 return ERROR_FAIL;
1079         }
1080
1081         /* If this device has 12 flash sectors, protection for
1082          * sectors 10 & 11 are handled jointly. If we are trying to
1083          * write all sectors, we should decrement
1084          * last to ensure we don't write to a register bit that
1085          * doesn't exist*/
1086         if ((bank->num_sectors == 12) && (last == 12))
1087                 last--;
1088
1089         /*  We need to fill out the procon register representation
1090          *   that we will be writing to the device */
1091         for (unsigned int i = first; i <= last; i++)
1092                 procon |= 1 << i;
1093
1094         /* If read protection is requested, set the appropriate bit
1095          * (we checked that this is allowed above) */
1096         if (read_protect)
1097                 procon |= PROCON_RPRO_MASK;
1098
1099         LOG_DEBUG("Setting flash protection with procon:");
1100         LOG_DEBUG("PROCON: %"PRIx32, procon);
1101
1102         /* First we need to copy in the procon register to the buffer
1103          * we're going to attempt to write.  This is written twice */
1104         target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], procon);
1105         target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], procon);
1106
1107         /* Now we must copy in both flash passwords.  As with the
1108          * procon data, this must be written twice (4 total words
1109          * worth of data) */
1110         target_buffer_set_u32(bank->target, &ucp0_buf[4 * 4], fb->pw1);
1111         target_buffer_set_u32(bank->target, &ucp0_buf[5 * 4], fb->pw2);
1112         target_buffer_set_u32(bank->target, &ucp0_buf[6 * 4], fb->pw1);
1113         target_buffer_set_u32(bank->target, &ucp0_buf[7 * 4], fb->pw2);
1114
1115         /* Finally, (if requested) we copy in the confirmation
1116          * code so that the protection is permanent and will
1117          * require a password to undo. */
1118         target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
1119         target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
1120
1121         /* Now that the data is copied into place, we must write
1122          * these pages into flash */
1123
1124         /* The user configuration block base depends on what level of
1125          * protection we're trying to install, select the proper one */
1126         switch (level) {
1127         case 0:
1128                 ucb_base = UCB0_BASE;
1129                 break;
1130         case 1:
1131                 ucb_base = UCB1_BASE;
1132                 break;
1133         case 2:
1134                 ucb_base = UCB2_BASE;
1135                 break;
1136         }
1137
1138         /* Write the user config pages */
1139         res = xmc4xxx_write_page(bank, ucp0_buf, ucb_base, true);
1140         if (res != ERROR_OK) {
1141                 LOG_ERROR("Error writing user configuration block 0");
1142                 return res;
1143         }
1144
1145         return ERROR_OK;
1146 }
1147
1148 static int xmc4xxx_protect(struct flash_bank *bank, int set, unsigned int first,
1149                 unsigned int last)
1150 {
1151         int ret;
1152         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1153
1154         /* Check for flash passwords */
1155         if (!fb->pw_set) {
1156                 LOG_ERROR("Flash passwords not set, use xmc4xxx flash_password to set them");
1157                 return ERROR_FAIL;
1158         }
1159
1160         /* We want to clear flash protection temporarily*/
1161         if (set == 0) {
1162                 LOG_WARNING("Flash protection will be temporarily disabled"
1163                             " for all pages (User 0 only)!");
1164                 ret = xmc4xxx_temp_unprotect(bank, 0);
1165                 return ret;
1166         }
1167
1168         /* Install write protection for user 0 on the specified pages */
1169         ret = xmc4xxx_flash_protect(bank, 0, false, first, last);
1170
1171         return ret;
1172 }
1173
1174 static int xmc4xxx_protect_check(struct flash_bank *bank)
1175 {
1176         int ret;
1177         uint32_t protection[3] = {0};
1178         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1179
1180         ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON0, &protection[0]);
1181         if (ret != ERROR_OK) {
1182                 LOG_ERROR("Unable to read flash User0 protection register");
1183                 return ret;
1184         }
1185
1186         ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON1, &protection[1]);
1187         if (ret != ERROR_OK) {
1188                 LOG_ERROR("Unable to read flash User1 protection register");
1189                 return ret;
1190         }
1191
1192         ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON2, &protection[2]);
1193         if (ret != ERROR_OK) {
1194                 LOG_ERROR("Unable to read flash User2 protection register");
1195                 return ret;
1196         }
1197
1198         unsigned int sectors = bank->num_sectors;
1199
1200         /* On devices with 12 sectors, sectors 10 & 11 are ptected
1201          * together instead of individually */
1202         if (sectors == 12)
1203                 sectors--;
1204
1205         /* Clear the protection status */
1206         for (unsigned int i = 0; i < bank->num_sectors; i++) {
1207                 bank->sectors[i].is_protected = 0;
1208                 fb->write_prot_otp[i] = false;
1209         }
1210         fb->read_protected = false;
1211
1212         /* The xmc4xxx series supports 3 levels of user protection
1213          * (User0, User1 (low priority), and User 2(OTP), we need to
1214          * check all 3 */
1215         for (unsigned int i = 0; i < ARRAY_SIZE(protection); i++) {
1216
1217                 /* Check for write protection on every available
1218                 *  sector */
1219                 for (unsigned int j = 0; j < sectors; j++) {
1220                         int set = (protection[i] & (1 << j)) ? 1 : 0;
1221                         bank->sectors[j].is_protected |= set;
1222
1223                         /* Handle sector 11 */
1224                         if (j == 10)
1225                                 bank->sectors[j + 1].is_protected |= set;
1226
1227                         /* User 2 indicates this protection is
1228                          * permanent, make note in the private driver structure */
1229                         if (i == 2 && set) {
1230                                 fb->write_prot_otp[j] = true;
1231
1232                                 /* Handle sector 11 */
1233                                 if (j == 10)
1234                                         fb->write_prot_otp[j + 1] = true;
1235                         }
1236
1237                 }
1238         }
1239
1240         /* XMC4xxx also supports read proptection, make a note
1241          * in the private driver structure */
1242         if (protection[0] & PROCON_RPRO_MASK)
1243                 fb->read_protected = true;
1244
1245         return ERROR_OK;
1246 }
1247
1248 FLASH_BANK_COMMAND_HANDLER(xmc4xxx_flash_bank_command)
1249 {
1250         bank->driver_priv = malloc(sizeof(struct xmc4xxx_flash_bank));
1251
1252         if (!bank->driver_priv)
1253                 return ERROR_FLASH_OPERATION_FAILED;
1254
1255         (void)memset(bank->driver_priv, 0, sizeof(struct xmc4xxx_flash_bank));
1256
1257         return ERROR_OK;
1258 }
1259
1260 COMMAND_HANDLER(xmc4xxx_handle_flash_password_command)
1261 {
1262         int res;
1263         struct flash_bank *bank;
1264
1265         if (CMD_ARGC < 3)
1266                 return ERROR_COMMAND_SYNTAX_ERROR;
1267
1268         res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1269         if (res != ERROR_OK)
1270                 return res;
1271
1272         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1273
1274         errno = 0;
1275
1276         /* We skip over the flash bank */
1277         fb->pw1 = strtol(CMD_ARGV[1], NULL, 16);
1278
1279         if (errno)
1280                 return ERROR_COMMAND_SYNTAX_ERROR;
1281
1282         fb->pw2 = strtol(CMD_ARGV[2], NULL, 16);
1283
1284         if (errno)
1285                 return ERROR_COMMAND_SYNTAX_ERROR;
1286
1287         fb->pw_set = true;
1288
1289         command_print(CMD, "XMC4xxx flash passwords set to:\n");
1290         command_print(CMD, "-0x%08"PRIx32"\n", fb->pw1);
1291         command_print(CMD, "-0x%08"PRIx32"\n", fb->pw2);
1292         return ERROR_OK;
1293 }
1294
1295 COMMAND_HANDLER(xmc4xxx_handle_flash_unprotect_command)
1296 {
1297         struct flash_bank *bank;
1298         int res;
1299         int32_t level;
1300
1301         if (CMD_ARGC < 2)
1302                 return ERROR_COMMAND_SYNTAX_ERROR;
1303
1304         res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1305         if (res != ERROR_OK)
1306                 return res;
1307
1308         COMMAND_PARSE_NUMBER(s32, CMD_ARGV[1], level);
1309
1310         res = xmc4xxx_flash_unprotect(bank, level);
1311
1312         return res;
1313 }
1314
1315 static const struct command_registration xmc4xxx_exec_command_handlers[] = {
1316         {
1317                 .name = "flash_password",
1318                 .handler = xmc4xxx_handle_flash_password_command,
1319                 .mode = COMMAND_EXEC,
1320                 .usage = "bank_id password1 password2",
1321                 .help = "Set the flash passwords used for protect operations. "
1322                 "Passwords should be in standard hex form (0x00000000). "
1323                 "(You must call this before any other protect commands) "
1324                 "NOTE: The xmc4xxx's UCB area only allows for FOUR cycles. "
1325                 "Please use protection carefully!",
1326         },
1327         {
1328                 .name = "flash_unprotect",
1329                 .handler = xmc4xxx_handle_flash_unprotect_command,
1330                 .mode = COMMAND_EXEC,
1331                 .usage = "bank_id user_level[0-1]",
1332                 .help = "Permanently Removes flash protection (read and write) "
1333                 "for the specified user level",
1334         },
1335         COMMAND_REGISTRATION_DONE
1336 };
1337
1338 static const struct command_registration xmc4xxx_command_handlers[] = {
1339         {
1340                 .name = "xmc4xxx",
1341                 .mode = COMMAND_ANY,
1342                 .help = "xmc4xxx flash command group",
1343                 .usage = "",
1344                 .chain = xmc4xxx_exec_command_handlers,
1345         },
1346         COMMAND_REGISTRATION_DONE
1347 };
1348
1349 const struct flash_driver xmc4xxx_flash = {
1350         .name = "xmc4xxx",
1351         .commands = xmc4xxx_command_handlers,
1352         .flash_bank_command = xmc4xxx_flash_bank_command,
1353         .erase = xmc4xxx_erase,
1354         .write = xmc4xxx_write,
1355         .read = default_flash_read,
1356         .probe = xmc4xxx_probe,
1357         .auto_probe = xmc4xxx_probe,
1358         .erase_check = default_flash_blank_check,
1359         .info = xmc4xxx_get_info_command,
1360         .protect_check = xmc4xxx_protect_check,
1361         .protect = xmc4xxx_protect,
1362         .free_driver_priv = default_flash_free_driver_priv,
1363 };