1 /***************************************************************************
2 * Copyright (C) 2007,2008 by Christopher Kilgour *
3 * techie |_at_| whiterocker |_dot_| com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
25 /* ----------------------------------------------------------------------
26 * Internal Support, Helpers
27 * ---------------------------------------------------------------------- */
29 struct tms470_flash_bank {
32 /* device identification register */
33 uint32_t device_ident_reg;
34 uint32_t silicon_version;
35 uint32_t technology_family;
38 const char *part_name;
42 static const struct flash_sector TMS470R1A256_SECTORS[] = {
43 {0x00000000, 0x00002000, -1, -1},
44 {0x00002000, 0x00002000, -1, -1},
45 {0x00004000, 0x00002000, -1, -1},
46 {0x00006000, 0x00002000, -1, -1},
47 {0x00008000, 0x00008000, -1, -1},
48 {0x00010000, 0x00008000, -1, -1},
49 {0x00018000, 0x00008000, -1, -1},
50 {0x00020000, 0x00008000, -1, -1},
51 {0x00028000, 0x00008000, -1, -1},
52 {0x00030000, 0x00008000, -1, -1},
53 {0x00038000, 0x00002000, -1, -1},
54 {0x0003A000, 0x00002000, -1, -1},
55 {0x0003C000, 0x00002000, -1, -1},
56 {0x0003E000, 0x00002000, -1, -1},
59 #define TMS470R1A256_NUM_SECTORS \
60 ARRAY_SIZE(TMS470R1A256_SECTORS)
62 static const struct flash_sector TMS470R1A288_BANK0_SECTORS[] = {
63 {0x00000000, 0x00002000, -1, -1},
64 {0x00002000, 0x00002000, -1, -1},
65 {0x00004000, 0x00002000, -1, -1},
66 {0x00006000, 0x00002000, -1, -1},
69 #define TMS470R1A288_BANK0_NUM_SECTORS \
70 ARRAY_SIZE(TMS470R1A288_BANK0_SECTORS)
72 static const struct flash_sector TMS470R1A288_BANK1_SECTORS[] = {
73 {0x00040000, 0x00010000, -1, -1},
74 {0x00050000, 0x00010000, -1, -1},
75 {0x00060000, 0x00010000, -1, -1},
76 {0x00070000, 0x00010000, -1, -1},
79 #define TMS470R1A288_BANK1_NUM_SECTORS \
80 ARRAY_SIZE(TMS470R1A288_BANK1_SECTORS)
82 static const struct flash_sector TMS470R1A384_BANK0_SECTORS[] = {
83 {0x00000000, 0x00002000, -1, -1},
84 {0x00002000, 0x00002000, -1, -1},
85 {0x00004000, 0x00004000, -1, -1},
86 {0x00008000, 0x00004000, -1, -1},
87 {0x0000C000, 0x00004000, -1, -1},
88 {0x00010000, 0x00004000, -1, -1},
89 {0x00014000, 0x00004000, -1, -1},
90 {0x00018000, 0x00002000, -1, -1},
91 {0x0001C000, 0x00002000, -1, -1},
92 {0x0001E000, 0x00002000, -1, -1},
95 #define TMS470R1A384_BANK0_NUM_SECTORS \
96 ARRAY_SIZE(TMS470R1A384_BANK0_SECTORS)
98 static const struct flash_sector TMS470R1A384_BANK1_SECTORS[] = {
99 {0x00020000, 0x00008000, -1, -1},
100 {0x00028000, 0x00008000, -1, -1},
101 {0x00030000, 0x00008000, -1, -1},
102 {0x00038000, 0x00008000, -1, -1},
105 #define TMS470R1A384_BANK1_NUM_SECTORS \
106 ARRAY_SIZE(TMS470R1A384_BANK1_SECTORS)
108 static const struct flash_sector TMS470R1A384_BANK2_SECTORS[] = {
109 {0x00040000, 0x00008000, -1, -1},
110 {0x00048000, 0x00008000, -1, -1},
111 {0x00050000, 0x00008000, -1, -1},
112 {0x00058000, 0x00008000, -1, -1},
115 #define TMS470R1A384_BANK2_NUM_SECTORS \
116 ARRAY_SIZE(TMS470R1A384_BANK2_SECTORS)
118 /* ---------------------------------------------------------------------- */
120 static int tms470_read_part_info(struct flash_bank *bank)
122 struct tms470_flash_bank *tms470_info = bank->driver_priv;
123 struct target *target = bank->target;
124 uint32_t device_ident_reg;
125 uint32_t silicon_version;
126 uint32_t technology_family;
128 uint32_t part_number;
129 const char *part_name;
131 /* we shall not rely on the caller in this test, this function allocates memory,
132 thus and executing the code more than once may cause memory leak */
133 if (tms470_info->device_ident_reg)
136 /* read and parse the device identification register */
137 target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
139 LOG_INFO("device_ident_reg = 0x%08" PRIx32 "", device_ident_reg);
141 if ((device_ident_reg & 7) == 0) {
142 LOG_WARNING("Cannot identify target as a TMS470 family.");
143 return ERROR_FLASH_OPERATION_FAILED;
146 silicon_version = (device_ident_reg >> 12) & 0xF;
147 technology_family = (device_ident_reg >> 11) & 1;
148 rom_flash = (device_ident_reg >> 10) & 1;
149 part_number = (device_ident_reg >> 3) & 0x7f;
153 bank->sectors = NULL;
154 bank->num_sectors = 0;
158 * If the part number is known, determine if the flash bank is valid
159 * based on the base address being within the known flash bank
160 * ranges. Then fixup/complete the remaining fields of the flash
163 switch (part_number) {
165 part_name = "TMS470R1A256";
167 if (bank->base >= 0x00040000) {
168 LOG_ERROR("No %s flash bank contains base address "
172 return ERROR_FLASH_OPERATION_FAILED;
174 tms470_info->ordinal = 0;
175 bank->base = 0x00000000;
176 bank->size = 256 * 1024;
177 bank->num_sectors = TMS470R1A256_NUM_SECTORS;
178 bank->sectors = malloc(sizeof(TMS470R1A256_SECTORS));
180 return ERROR_FLASH_OPERATION_FAILED;
181 (void)memcpy(bank->sectors, TMS470R1A256_SECTORS, sizeof(TMS470R1A256_SECTORS));
185 part_name = "TMS470R1A288";
187 if (bank->base < 0x00008000) {
188 tms470_info->ordinal = 0;
189 bank->base = 0x00000000;
190 bank->size = 32 * 1024;
191 bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS;
192 bank->sectors = malloc(sizeof(TMS470R1A288_BANK0_SECTORS));
194 return ERROR_FLASH_OPERATION_FAILED;
195 (void)memcpy(bank->sectors, TMS470R1A288_BANK0_SECTORS,
196 sizeof(TMS470R1A288_BANK0_SECTORS));
197 } else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000)) {
198 tms470_info->ordinal = 1;
199 bank->base = 0x00040000;
200 bank->size = 256 * 1024;
201 bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS;
202 bank->sectors = malloc(sizeof(TMS470R1A288_BANK1_SECTORS));
204 return ERROR_FLASH_OPERATION_FAILED;
205 (void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS,
206 sizeof(TMS470R1A288_BANK1_SECTORS));
208 LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
209 part_name, bank->base);
210 return ERROR_FLASH_OPERATION_FAILED;
215 part_name = "TMS470R1A384";
217 if (bank->base < 0x00020000) {
218 tms470_info->ordinal = 0;
219 bank->base = 0x00000000;
220 bank->size = 128 * 1024;
221 bank->num_sectors = TMS470R1A384_BANK0_NUM_SECTORS;
222 bank->sectors = malloc(sizeof(TMS470R1A384_BANK0_SECTORS));
224 return ERROR_FLASH_OPERATION_FAILED;
225 (void)memcpy(bank->sectors, TMS470R1A384_BANK0_SECTORS,
226 sizeof(TMS470R1A384_BANK0_SECTORS));
227 } else if ((bank->base >= 0x00020000) && (bank->base < 0x00040000)) {
228 tms470_info->ordinal = 1;
229 bank->base = 0x00020000;
230 bank->size = 128 * 1024;
231 bank->num_sectors = TMS470R1A384_BANK1_NUM_SECTORS;
232 bank->sectors = malloc(sizeof(TMS470R1A384_BANK1_SECTORS));
234 return ERROR_FLASH_OPERATION_FAILED;
235 (void)memcpy(bank->sectors, TMS470R1A384_BANK1_SECTORS,
236 sizeof(TMS470R1A384_BANK1_SECTORS));
237 } else if ((bank->base >= 0x00040000) && (bank->base < 0x00060000)) {
238 tms470_info->ordinal = 2;
239 bank->base = 0x00040000;
240 bank->size = 128 * 1024;
241 bank->num_sectors = TMS470R1A384_BANK2_NUM_SECTORS;
242 bank->sectors = malloc(sizeof(TMS470R1A384_BANK2_SECTORS));
244 return ERROR_FLASH_OPERATION_FAILED;
245 (void)memcpy(bank->sectors, TMS470R1A384_BANK2_SECTORS,
246 sizeof(TMS470R1A384_BANK2_SECTORS));
248 LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
249 part_name, bank->base);
250 return ERROR_FLASH_OPERATION_FAILED;
255 LOG_WARNING("Could not identify part 0x%02x as a member of the TMS470 family.",
256 (unsigned)part_number);
257 return ERROR_FLASH_OPERATION_FAILED;
260 /* turn off memory selects */
261 target_write_u32(target, 0xFFFFFFE4, 0x00000000);
262 target_write_u32(target, 0xFFFFFFE0, 0x00000000);
264 bank->chip_width = 32;
265 bank->bus_width = 32;
267 LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.",
269 (int)(silicon_version),
270 (technology_family ? "1.8v" : "3.3v"),
271 (rom_flash ? "rom" : "flash"));
273 tms470_info->device_ident_reg = device_ident_reg;
274 tms470_info->silicon_version = silicon_version;
275 tms470_info->technology_family = technology_family;
276 tms470_info->rom_flash = rom_flash;
277 tms470_info->part_number = part_number;
278 tms470_info->part_name = part_name;
281 * Disable reset on address access violation.
283 target_write_u32(target, 0xFFFFFFE0, 0x00004007);
288 /* ---------------------------------------------------------------------- */
290 static uint32_t keysSet;
291 static uint32_t flashKeys[4];
293 COMMAND_HANDLER(tms470_handle_flash_keyset_command)
296 return ERROR_COMMAND_SYNTAX_ERROR;
297 else if (CMD_ARGC == 4) {
300 for (i = 0; i < 4; i++) {
301 int start = (0 == strncmp(CMD_ARGV[i], "0x", 2)) ? 2 : 0;
303 if (1 != sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flashKeys[i])) {
304 command_print(CMD, "could not process flash key %s",
306 LOG_ERROR("could not process flash key %s", CMD_ARGV[i]);
307 return ERROR_COMMAND_SYNTAX_ERROR;
312 } else if (CMD_ARGC != 0) {
313 command_print(CMD, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
314 return ERROR_COMMAND_SYNTAX_ERROR;
319 "using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
325 command_print(CMD, "flash keys not set");
330 static const uint32_t FLASH_KEYS_ALL_ONES[] = { 0xFFFFFFFF, 0xFFFFFFFF,
331 0xFFFFFFFF, 0xFFFFFFFF,};
333 static const uint32_t FLASH_KEYS_ALL_ZEROS[] = { 0x00000000, 0x00000000,
334 0x00000000, 0x00000000,};
336 static const uint32_t FLASH_KEYS_MIX1[] = { 0xf0fff0ff, 0xf0fff0ff,
337 0xf0fff0ff, 0xf0fff0ff};
339 static const uint32_t FLASH_KEYS_MIX2[] = { 0x0000ffff, 0x0000ffff,
340 0x0000ffff, 0x0000ffff};
342 /* ---------------------------------------------------------------------- */
344 static int oscMHz = 12;
346 COMMAND_HANDLER(tms470_handle_osc_megahertz_command)
349 return ERROR_COMMAND_SYNTAX_ERROR;
350 else if (CMD_ARGC == 1)
351 sscanf(CMD_ARGV[0], "%d", &oscMHz);
354 LOG_ERROR("osc_megahertz must be positive and non-zero!");
355 command_print(CMD, "osc_megahertz must be positive and non-zero!");
357 return ERROR_COMMAND_SYNTAX_ERROR;
360 command_print(CMD, "osc_megahertz=%d", oscMHz);
365 /* ---------------------------------------------------------------------- */
369 COMMAND_HANDLER(tms470_handle_plldis_command)
372 return ERROR_COMMAND_SYNTAX_ERROR;
373 else if (CMD_ARGC == 1) {
374 sscanf(CMD_ARGV[0], "%d", &plldis);
375 plldis = plldis ? 1 : 0;
378 command_print(CMD, "plldis=%d", plldis);
383 /* ---------------------------------------------------------------------- */
385 static int tms470_check_flash_unlocked(struct target *target)
389 target_read_u32(target, 0xFFE89C08, &fmbbusy);
390 LOG_INFO("tms470 fmbbusy = 0x%08" PRIx32 " -> %s",
392 fmbbusy & 0x8000 ? "unlocked" : "LOCKED");
393 return fmbbusy & 0x8000 ? ERROR_OK : ERROR_FLASH_OPERATION_FAILED;
396 /* ---------------------------------------------------------------------- */
398 static int tms470_try_flash_keys(struct target *target, const uint32_t *key_set)
400 uint32_t glbctrl, fmmstat;
401 int retval = ERROR_FLASH_OPERATION_FAILED;
404 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
405 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
407 /* only perform the key match when 3VSTAT is clear */
408 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
409 if (!(fmmstat & 0x08)) {
411 uint32_t fmbptr, fmbac2, orig_fmregopt;
413 target_write_u32(target, 0xFFE8BC04, fmmstat & ~0x07);
415 /* wait for pump ready */
417 target_read_u32(target, 0xFFE8A814, &fmbptr);
419 } while (!(fmbptr & 0x0200));
421 /* force max wait states */
422 target_read_u32(target, 0xFFE88004, &fmbac2);
423 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
425 /* save current access mode, force normal read mode */
426 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
427 target_write_u32(target, 0xFFE89C00, 0x00);
429 for (i = 0; i < 4; i++) {
432 /* There is no point displaying the value of tmp, it is
433 * filtered by the chip. The purpose of this read is to
434 * prime the unlocking logic rather than read out the value.
436 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
438 LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32 "", key_set[i]);
439 target_write_u32(target, 0xFFE89C0C, key_set[i]);
442 if (ERROR_OK == tms470_check_flash_unlocked(target)) {
444 * There seems to be a side-effect of reading the FMPKEY
445 * register in that it re-enables the protection. So we
448 for (i = 0; i < 4; i++) {
451 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
452 target_write_u32(target, 0xFFE89C0C, key_set[i]);
457 /* restore settings */
458 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
459 target_write_u32(target, 0xFFE88004, fmbac2);
462 /* clear config bit */
463 target_write_u32(target, 0xFFFFFFDC, glbctrl);
468 /* ---------------------------------------------------------------------- */
470 static int tms470_unlock_flash(struct flash_bank *bank)
472 struct target *target = bank->target;
473 const uint32_t *p_key_sets[5];
474 unsigned i, key_set_count;
478 p_key_sets[0] = flashKeys;
479 p_key_sets[1] = FLASH_KEYS_ALL_ONES;
480 p_key_sets[2] = FLASH_KEYS_ALL_ZEROS;
481 p_key_sets[3] = FLASH_KEYS_MIX1;
482 p_key_sets[4] = FLASH_KEYS_MIX2;
485 p_key_sets[0] = FLASH_KEYS_ALL_ONES;
486 p_key_sets[1] = FLASH_KEYS_ALL_ZEROS;
487 p_key_sets[2] = FLASH_KEYS_MIX1;
488 p_key_sets[3] = FLASH_KEYS_MIX2;
491 for (i = 0; i < key_set_count; i++) {
492 if (tms470_try_flash_keys(target, p_key_sets[i]) == ERROR_OK) {
493 LOG_INFO("tms470 flash is unlocked");
498 LOG_WARNING("tms470 could not unlock flash memory protection level 2");
499 return ERROR_FLASH_OPERATION_FAILED;
502 /* ---------------------------------------------------------------------- */
504 static int tms470_flash_initialize_internal_state_machine(struct flash_bank *bank)
506 uint32_t fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
507 struct target *target = bank->target;
508 struct tms470_flash_bank *tms470_info = bank->driver_priv;
509 int result = ERROR_OK;
512 * Select the desired bank to be programmed by writing BANK[2:0] of
515 target_read_u32(target, 0xFFE8BC04, &fmmac2);
517 fmmac2 |= (tms470_info->ordinal & 7);
518 target_write_u32(target, 0xFFE8BC04, fmmac2);
519 LOG_DEBUG("set fmmac2 = 0x%04" PRIx32 "", fmmac2);
522 * Disable level 1 sector protection by setting bit 15 of FMMAC1.
524 target_read_u32(target, 0xFFE8BC00, &fmmac1);
526 target_write_u32(target, 0xFFE8BC00, fmmac1);
527 LOG_DEBUG("set fmmac1 = 0x%04" PRIx32 "", fmmac1);
532 target_write_u32(target, 0xFFE8BC10, 0x2fc0);
533 LOG_DEBUG("set fmtcreg = 0x2fc0");
538 target_write_u32(target, 0xFFE8A07C, 50);
539 LOG_DEBUG("set fmmaxpp = 50");
542 * MAXCP = 0xf000 + 2000
544 target_write_u32(target, 0xFFE8A084, 0xf000 + 2000);
545 LOG_DEBUG("set fmmaxcp = 0x%04x", 0xf000 + 2000);
550 target_read_u32(target, 0xFFE8A080, &fmmaxep);
551 if (fmmaxep == 0xf000) {
552 fmmaxep = 0xf000 + 4095;
553 target_write_u32(target, 0xFFE8A80C, 0x9964);
554 LOG_DEBUG("set fmptr3 = 0x9964");
556 fmmaxep = 0xa000 + 4095;
557 target_write_u32(target, 0xFFE8A80C, 0x9b64);
558 LOG_DEBUG("set fmptr3 = 0x9b64");
560 target_write_u32(target, 0xFFE8A080, fmmaxep);
561 LOG_DEBUG("set fmmaxep = 0x%04" PRIx32 "", fmmaxep);
566 target_write_u32(target, 0xFFE8A810, 0xa000);
567 LOG_DEBUG("set fmptr4 = 0xa000");
570 * FMPESETUP, delay parameter selected based on clock frequency.
572 * According to the TI App Note SPNU257 and flashing code, delay is
573 * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
574 * clock is usually derived from the ZPLL module, and selected by
577 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
578 sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * oscMHz / (1 + (glbctrl & 7));
579 delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
580 target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
581 LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) | (delay << 8));
584 * FMPVEVACCESS, based on delay.
586 k = delay | (delay << 8);
587 target_write_u32(target, 0xFFE8A05C, k);
588 LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32 "", k);
591 * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
594 target_write_u32(target, 0xFFE8A034, k);
595 LOG_DEBUG("set fmpchold = 0x%04" PRIx32 "", k);
596 target_write_u32(target, 0xFFE8A040, k);
597 LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32 "", k);
598 target_write_u32(target, 0xFFE8A024, k);
599 LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32 "", k);
602 * FMCVACCESS, based on delay.
605 target_write_u32(target, 0xFFE8A060, k);
606 LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32 "", k);
609 * FMCSETUP, based on delay.
611 k = 0x3000 | delay * 20;
612 target_write_u32(target, 0xFFE8A020, k);
613 LOG_DEBUG("set fmcsetup = 0x%04" PRIx32 "", k);
616 * FMEHOLD, based on delay.
618 k = (delay * 20) << 2;
619 target_write_u32(target, 0xFFE8A038, k);
620 LOG_DEBUG("set fmehold = 0x%04" PRIx32 "", k);
623 * PWIDTH, CWIDTH, EWIDTH, based on delay.
625 target_write_u32(target, 0xFFE8A050, delay * 8);
626 LOG_DEBUG("set fmpwidth = 0x%04" PRIx32 "", delay * 8);
627 target_write_u32(target, 0xFFE8A058, delay * 1000);
628 LOG_DEBUG("set fmcwidth = 0x%04" PRIx32 "", delay * 1000);
629 target_write_u32(target, 0xFFE8A054, delay * 5400);
630 LOG_DEBUG("set fmewidth = 0x%04" PRIx32 "", delay * 5400);
635 /* ---------------------------------------------------------------------- */
637 static int tms470_flash_status(struct flash_bank *bank)
639 struct target *target = bank->target;
640 int result = ERROR_OK;
643 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
644 LOG_DEBUG("set fmmstat = 0x%04" PRIx32 "", fmmstat);
646 if (fmmstat & 0x0080) {
647 LOG_WARNING("tms470 flash command: erase still active after busy clear.");
648 result = ERROR_FLASH_OPERATION_FAILED;
651 if (fmmstat & 0x0040) {
652 LOG_WARNING("tms470 flash command: program still active after busy clear.");
653 result = ERROR_FLASH_OPERATION_FAILED;
656 if (fmmstat & 0x0020) {
657 LOG_WARNING("tms470 flash command: invalid data command.");
658 result = ERROR_FLASH_OPERATION_FAILED;
661 if (fmmstat & 0x0010) {
662 LOG_WARNING("tms470 flash command: program, erase or validate sector failed.");
663 result = ERROR_FLASH_OPERATION_FAILED;
666 if (fmmstat & 0x0008) {
667 LOG_WARNING("tms470 flash command: voltage instability detected.");
668 result = ERROR_FLASH_OPERATION_FAILED;
671 if (fmmstat & 0x0006) {
672 LOG_WARNING("tms470 flash command: command suspend detected.");
673 result = ERROR_FLASH_OPERATION_FAILED;
676 if (fmmstat & 0x0001) {
677 LOG_WARNING("tms470 flash command: sector was locked.");
678 result = ERROR_FLASH_OPERATION_FAILED;
684 /* ---------------------------------------------------------------------- */
686 static int tms470_erase_sector(struct flash_bank *bank, int sector)
688 uint32_t glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
689 struct target *target = bank->target;
690 uint32_t flashAddr = bank->base + bank->sectors[sector].offset;
691 int result = ERROR_OK;
694 * Set the bit GLBCTRL4 of the GLBCTRL register (in the System
695 * module) to enable writing to the flash registers }.
697 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
698 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
699 LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl | 0x10);
701 /* Force normal read mode. */
702 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
703 target_write_u32(target, 0xFFE89C00, 0);
704 LOG_DEBUG("set fmregopt = 0x%08x", 0);
706 (void)tms470_flash_initialize_internal_state_machine(bank);
709 * Select one or more bits in FMBSEA or FMBSEB to disable Level 1
710 * protection for the particular sector to be erased/written.
713 target_read_u32(target, 0xFFE88008, &fmbsea);
714 target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
715 LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea | (1 << sector));
717 target_read_u32(target, 0xFFE8800C, &fmbseb);
718 target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
719 LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb | (1 << (sector - 16)));
721 bank->sectors[sector].is_protected = 0;
724 * clear status regiser, sent erase command, kickoff erase
726 target_write_u16(target, flashAddr, 0x0040);
727 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flashAddr);
728 target_write_u16(target, flashAddr, 0x0020);
729 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0020", flashAddr);
730 target_write_u16(target, flashAddr, 0xffff);
731 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0xffff", flashAddr);
734 * Monitor FMMSTAT, busy until clear, then check and other flags for
735 * ultimate result of the operation.
738 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
739 if (fmmstat & 0x0100)
741 } while (fmmstat & 0x0100);
743 result = tms470_flash_status(bank);
746 target_write_u32(target, 0xFFE88008, fmbsea);
747 LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea);
748 bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
750 target_write_u32(target, 0xFFE8800C, fmbseb);
751 LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb);
752 bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
754 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
755 LOG_DEBUG("set fmregopt = 0x%08" PRIx32 "", orig_fmregopt);
756 target_write_u32(target, 0xFFFFFFDC, glbctrl);
757 LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl);
762 /*----------------------------------------------------------------------
763 * Implementation of Flash Driver Interfaces
764 *---------------------------------------------------------------------- */
766 static const struct command_registration tms470_any_command_handlers[] = {
768 .name = "flash_keyset",
769 .usage = "<key0> <key1> <key2> <key3>",
770 .handler = tms470_handle_flash_keyset_command,
772 .help = "tms470 flash_keyset <key0> <key1> <key2> <key3>",
775 .name = "osc_megahertz",
777 .handler = tms470_handle_osc_megahertz_command,
779 .help = "tms470 osc_megahertz <MHz>",
784 .handler = tms470_handle_plldis_command,
786 .help = "tms470 plldis <0/1>",
788 COMMAND_REGISTRATION_DONE
790 static const struct command_registration tms470_command_handlers[] = {
794 .help = "TI tms470 flash command group",
796 .chain = tms470_any_command_handlers,
798 COMMAND_REGISTRATION_DONE
801 /* ---------------------------------------------------------------------- */
803 static int tms470_erase(struct flash_bank *bank, int first, int last)
805 struct tms470_flash_bank *tms470_info = bank->driver_priv;
806 int sector, result = ERROR_OK;
808 if (bank->target->state != TARGET_HALTED) {
809 LOG_ERROR("Target not halted");
810 return ERROR_TARGET_NOT_HALTED;
813 tms470_read_part_info(bank);
815 if ((first < 0) || (first >= bank->num_sectors) || (last < 0) ||
816 (last >= bank->num_sectors) || (first > last)) {
817 LOG_ERROR("Sector range %d to %d invalid.", first, last);
818 return ERROR_FLASH_SECTOR_INVALID;
821 result = tms470_unlock_flash(bank);
822 if (result != ERROR_OK)
825 for (sector = first; sector <= last; sector++) {
826 LOG_INFO("Erasing tms470 bank %d sector %d...", tms470_info->ordinal, sector);
828 result = tms470_erase_sector(bank, sector);
830 if (result != ERROR_OK) {
831 LOG_ERROR("tms470 could not erase flash sector.");
834 LOG_INFO("sector erased successfully.");
840 /* ---------------------------------------------------------------------- */
842 static int tms470_protect(struct flash_bank *bank, int set, int first, int last)
844 struct tms470_flash_bank *tms470_info = bank->driver_priv;
845 struct target *target = bank->target;
846 uint32_t fmmac2, fmbsea, fmbseb;
849 if (target->state != TARGET_HALTED) {
850 LOG_ERROR("Target not halted");
851 return ERROR_TARGET_NOT_HALTED;
854 tms470_read_part_info(bank);
856 if ((first < 0) || (first >= bank->num_sectors) || (last < 0) ||
857 (last >= bank->num_sectors) || (first > last)) {
858 LOG_ERROR("Sector range %d to %d invalid.", first, last);
859 return ERROR_FLASH_SECTOR_INVALID;
862 /* enable the appropriate bank */
863 target_read_u32(target, 0xFFE8BC04, &fmmac2);
864 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
866 /* get the original sector proection flags for this bank */
867 target_read_u32(target, 0xFFE88008, &fmbsea);
868 target_read_u32(target, 0xFFE8800C, &fmbseb);
870 for (sector = 0; sector < bank->num_sectors; sector++) {
872 fmbsea = set ? fmbsea & ~(1 << sector) : fmbsea | (1 << sector);
873 bank->sectors[sector].is_protected = set ? 1 : 0;
875 fmbseb = set ? fmbseb &
876 ~(1 << (sector - 16)) : fmbseb | (1 << (sector - 16));
877 bank->sectors[sector].is_protected = set ? 1 : 0;
881 /* update the protection bits */
882 target_write_u32(target, 0xFFE88008, fmbsea);
883 target_write_u32(target, 0xFFE8800C, fmbseb);
888 /* ---------------------------------------------------------------------- */
890 static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
892 struct target *target = bank->target;
893 uint32_t glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
894 int result = ERROR_OK;
897 if (target->state != TARGET_HALTED) {
898 LOG_ERROR("Target not halted");
899 return ERROR_TARGET_NOT_HALTED;
902 tms470_read_part_info(bank);
904 LOG_INFO("Writing %" PRId32 " bytes starting at " TARGET_ADDR_FMT,
905 count, bank->base + offset);
908 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
909 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
911 (void)tms470_flash_initialize_internal_state_machine(bank);
913 /* force max wait states */
914 target_read_u32(target, 0xFFE88004, &fmbac2);
915 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
917 /* save current access mode, force normal read mode */
918 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
919 target_write_u32(target, 0xFFE89C00, 0x00);
922 * Disable Level 1 protection for all sectors to be erased/written.
924 target_read_u32(target, 0xFFE88008, &fmbsea);
925 target_write_u32(target, 0xFFE88008, 0xffff);
926 target_read_u32(target, 0xFFE8800C, &fmbseb);
927 target_write_u32(target, 0xFFE8800C, 0xffff);
930 target_read_u32(target, 0xFFE8A07C, &fmmaxpp);
932 for (i = 0; i < count; i += 2) {
933 uint32_t addr = bank->base + offset + i;
934 uint16_t word = (((uint16_t) buffer[i]) << 8) | (uint16_t) buffer[i + 1];
936 if (word != 0xffff) {
937 LOG_INFO("writing 0x%04x at 0x%08" PRIx32 "", word, addr);
939 /* clear status register */
940 target_write_u16(target, addr, 0x0040);
941 /* program flash command */
942 target_write_u16(target, addr, 0x0010);
943 /* burn the 16-bit word (big-endian) */
944 target_write_u16(target, addr, word);
947 * Monitor FMMSTAT, busy until clear, then check and other flags
948 * for ultimate result of the operation.
951 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
952 if (fmmstat & 0x0100)
954 } while (fmmstat & 0x0100);
956 if (fmmstat & 0x3ff) {
957 LOG_ERROR("fmstat = 0x%04" PRIx32 "", fmmstat);
959 "Could not program word 0x%04x at address 0x%08" PRIx32 ".",
962 result = ERROR_FLASH_OPERATION_FAILED;
966 LOG_INFO("skipping 0xffff at 0x%08" PRIx32 "", addr);
970 target_write_u32(target, 0xFFE88008, fmbsea);
971 target_write_u32(target, 0xFFE8800C, fmbseb);
972 target_write_u32(target, 0xFFE88004, fmbac2);
973 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
974 target_write_u32(target, 0xFFFFFFDC, glbctrl);
979 /* ---------------------------------------------------------------------- */
981 static int tms470_probe(struct flash_bank *bank)
983 if (bank->target->state != TARGET_HALTED) {
984 LOG_WARNING("Cannot communicate... target not halted.");
985 return ERROR_TARGET_NOT_HALTED;
988 return tms470_read_part_info(bank);
991 static int tms470_auto_probe(struct flash_bank *bank)
993 struct tms470_flash_bank *tms470_info = bank->driver_priv;
995 if (tms470_info->device_ident_reg)
997 return tms470_probe(bank);
1000 /* ---------------------------------------------------------------------- */
1002 static int tms470_erase_check(struct flash_bank *bank)
1004 struct target *target = bank->target;
1005 struct tms470_flash_bank *tms470_info = bank->driver_priv;
1006 int sector, result = ERROR_OK;
1007 uint32_t fmmac2, fmbac2, glbctrl, orig_fmregopt;
1008 static uint8_t buffer[64 * 1024];
1010 if (target->state != TARGET_HALTED) {
1011 LOG_ERROR("Target not halted");
1012 return ERROR_TARGET_NOT_HALTED;
1015 if (!tms470_info->device_ident_reg)
1016 tms470_read_part_info(bank);
1019 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
1020 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
1022 /* save current access mode, force normal read mode */
1023 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
1024 target_write_u32(target, 0xFFE89C00, 0x00);
1026 /* enable the appropriate bank */
1027 target_read_u32(target, 0xFFE8BC04, &fmmac2);
1028 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1031 target_write_u32(target, 0xFFE8BC10, 0x2fc0);
1033 /* clear TEZ in fmbrdy */
1034 target_write_u32(target, 0xFFE88010, 0x0b);
1036 /* save current wait states, force max */
1037 target_read_u32(target, 0xFFE88004, &fmbac2);
1038 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
1041 * The TI primitives inspect the flash memory by reading one 32-bit
1042 * word at a time. Here we read an entire sector and inspect it in
1043 * an attempt to reduce the JTAG overhead.
1045 for (sector = 0; sector < bank->num_sectors; sector++) {
1046 uint32_t i, addr = bank->base + bank->sectors[sector].offset;
1048 LOG_INFO("checking flash bank %d sector %d", tms470_info->ordinal, sector);
1050 target_read_buffer(target, addr, bank->sectors[sector].size, buffer);
1052 bank->sectors[sector].is_erased = 1;
1053 for (i = 0; i < bank->sectors[sector].size; i++) {
1054 if (buffer[i] != 0xff) {
1055 bank->sectors[sector].is_erased = 0;
1059 if (bank->sectors[sector].is_erased != 1) {
1060 result = ERROR_FLASH_SECTOR_NOT_ERASED;
1063 LOG_INFO("sector erased");
1066 /* reset TEZ, wait states, read mode, GLBCTRL.4 */
1067 target_write_u32(target, 0xFFE88010, 0x0f);
1068 target_write_u32(target, 0xFFE88004, fmbac2);
1069 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
1070 target_write_u32(target, 0xFFFFFFDC, glbctrl);
1075 /* ---------------------------------------------------------------------- */
1077 static int tms470_protect_check(struct flash_bank *bank)
1079 struct target *target = bank->target;
1080 struct tms470_flash_bank *tms470_info = bank->driver_priv;
1081 int sector, result = ERROR_OK;
1082 uint32_t fmmac2, fmbsea, fmbseb;
1084 if (target->state != TARGET_HALTED) {
1085 LOG_ERROR("Target not halted");
1086 return ERROR_TARGET_NOT_HALTED;
1089 if (!tms470_info->device_ident_reg)
1090 tms470_read_part_info(bank);
1092 /* enable the appropriate bank */
1093 target_read_u32(target, 0xFFE8BC04, &fmmac2);
1094 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1096 target_read_u32(target, 0xFFE88008, &fmbsea);
1097 target_read_u32(target, 0xFFE8800C, &fmbseb);
1099 for (sector = 0; sector < bank->num_sectors; sector++) {
1103 protected = fmbsea & (1 << sector) ? 0 : 1;
1104 bank->sectors[sector].is_protected = protected;
1106 protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
1107 bank->sectors[sector].is_protected = protected;
1110 LOG_DEBUG("bank %d sector %d is %s",
1111 tms470_info->ordinal,
1113 protected ? "protected" : "not protected");
1119 /* ---------------------------------------------------------------------- */
1121 static int get_tms470_info(struct flash_bank *bank, char *buf, int buf_size)
1124 struct tms470_flash_bank *tms470_info = bank->driver_priv;
1126 if (!tms470_info->device_ident_reg)
1127 tms470_read_part_info(bank);
1129 if (!tms470_info->device_ident_reg) {
1130 (void)snprintf(buf, buf_size, "Cannot identify target as a TMS470\n");
1131 return ERROR_FLASH_OPERATION_FAILED;
1135 snprintf(buf, buf_size, "\ntms470 information: Chip is %s\n",
1136 tms470_info->part_name);
1140 snprintf(buf, buf_size, "Flash protection level 2 is %s\n",
1141 tms470_check_flash_unlocked(bank->target) == ERROR_OK ? "disabled" : "enabled");
1146 /* ---------------------------------------------------------------------- */
1149 * flash bank tms470 <base> <size> <chip_width> <bus_width> <target>
1153 FLASH_BANK_COMMAND_HANDLER(tms470_flash_bank_command)
1155 bank->driver_priv = malloc(sizeof(struct tms470_flash_bank));
1157 if (!bank->driver_priv)
1158 return ERROR_FLASH_OPERATION_FAILED;
1160 (void)memset(bank->driver_priv, 0, sizeof(struct tms470_flash_bank));
1165 const struct flash_driver tms470_flash = {
1167 .commands = tms470_command_handlers,
1168 .flash_bank_command = tms470_flash_bank_command,
1169 .erase = tms470_erase,
1170 .protect = tms470_protect,
1171 .write = tms470_write,
1172 .read = default_flash_read,
1173 .probe = tms470_probe,
1174 .auto_probe = tms470_auto_probe,
1175 .erase_check = tms470_erase_check,
1176 .protect_check = tms470_protect_check,
1177 .info = get_tms470_info,
1178 .free_driver_priv = default_flash_free_driver_priv,