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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2010 Øyvind Harboe                                      *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "imp.h"
  31 #include <target/arm.h>
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34
  35
  36 /*  Flash registers */
  37
  38 #define FLASH_CR0               0x00000000
  39 #define FLASH_CR1               0x00000004
  40 #define FLASH_DR0               0x00000008
  41 #define FLASH_DR1               0x0000000C
  42 #define FLASH_AR                0x00000010
  43 #define FLASH_ER                0x00000014
  44 #define FLASH_NVWPAR    0x0000DFB0
  45 #define FLASH_NVAPR0    0x0000DFB8
  46 #define FLASH_NVAPR1    0x0000DFBC
  47
  48 /* FLASH_CR0 register bits */
  49
  50 #define FLASH_WMS               0x80000000
  51 #define FLASH_SUSP              0x40000000
  52 #define FLASH_WPG               0x20000000
  53 #define FLASH_DWPG              0x10000000
  54 #define FLASH_SER               0x08000000
  55 #define FLASH_SPR               0x01000000
  56 #define FLASH_BER               0x04000000
  57 #define FLASH_MER               0x02000000
  58 #define FLASH_LOCK              0x00000010
  59 #define FLASH_BSYA1             0x00000004
  60 #define FLASH_BSYA0             0x00000002
  61
  62 /* FLASH_CR1 register bits */
  63
  64 #define FLASH_B1S               0x02000000
  65 #define FLASH_B0S               0x01000000
  66 #define FLASH_B1F1              0x00020000
  67 #define FLASH_B1F0              0x00010000
  68 #define FLASH_B0F7              0x00000080
  69 #define FLASH_B0F6              0x00000040
  70 #define FLASH_B0F5              0x00000020
  71 #define FLASH_B0F4              0x00000010
  72 #define FLASH_B0F3              0x00000008
  73 #define FLASH_B0F2              0x00000004
  74 #define FLASH_B0F1              0x00000002
  75 #define FLASH_B0F0              0x00000001
  76
  77 /* FLASH_ER register bits */
  78
  79 #define FLASH_WPF               0x00000100
  80 #define FLASH_RESER             0x00000080
  81 #define FLASH_SEQER             0x00000040
  82 #define FLASH_10ER              0x00000008
  83 #define FLASH_PGER              0x00000004
  84 #define FLASH_ERER              0x00000002
  85 #define FLASH_ERR               0x00000001
  86
  87
  88 struct str7x_flash_bank
  89 {
  90         uint32_t *sector_bits;
  91         uint32_t disable_bit;
  92         uint32_t busy_bits;
  93         uint32_t register_base;
  94         struct working_area *write_algorithm;
  95 };
  96
  97 struct str7x_mem_layout {
  98         uint32_t sector_start;
  99         uint32_t sector_size;
 100         uint32_t sector_bit;
 101 };
 102
 103 enum str7x_status_codes
 104 {
 105         STR7X_CMD_SUCCESS = 0,
 106         STR7X_INVALID_COMMAND = 1,
 107         STR7X_SRC_ADDR_ERROR = 2,
 108         STR7X_DST_ADDR_ERROR = 3,
 109         STR7X_SRC_ADDR_NOT_MAPPED = 4,
 110         STR7X_DST_ADDR_NOT_MAPPED = 5,
 111         STR7X_COUNT_ERROR = 6,
 112         STR7X_INVALID_SECTOR = 7,
 113         STR7X_SECTOR_NOT_BLANK = 8,
 114         STR7X_SECTOR_NOT_PREPARED = 9,
 115         STR7X_COMPARE_ERROR = 10,
 116         STR7X_BUSY = 11
 117 };
 118
 119 static struct str7x_mem_layout mem_layout_str7bank0[] = {
 120         {0x00000000, 0x02000, 0x01},
 121         {0x00002000, 0x02000, 0x02},
 122         {0x00004000, 0x02000, 0x04},
 123         {0x00006000, 0x02000, 0x08},
 124         {0x00008000, 0x08000, 0x10},
 125         {0x00010000, 0x10000, 0x20},
 126         {0x00020000, 0x10000, 0x40},
 127         {0x00030000, 0x10000, 0x80}
 128 };
 129
 130 static struct str7x_mem_layout mem_layout_str7bank1[] = {
 131         {0x00000000, 0x02000, 0x10000},
 132         {0x00002000, 0x02000, 0x20000}
 133 };
 134
 135 static int str7x_get_flash_adr(struct flash_bank *bank, uint32_t reg)
 136 {
 137         struct str7x_flash_bank *str7x_info = bank->driver_priv;
 138         return (str7x_info->register_base | reg);
 139 }
 140
 141 static int str7x_build_block_list(struct flash_bank *bank)
 142 {
 143         struct str7x_flash_bank *str7x_info = bank->driver_priv;
 144
 145         int i;
 146         int num_sectors;
 147         int b0_sectors = 0, b1_sectors = 0;
 148
 149         switch (bank->size)
 150         {
 151                 case 16 * 1024:
 152                         b1_sectors = 2;
 153                         break;
 154                 case 64 * 1024:
 155                         b0_sectors = 5;
 156                         break;
 157                 case 128 * 1024:
 158                         b0_sectors = 6;
 159                         break;
 160                 case 256 * 1024:
 161                         b0_sectors = 8;
 162                         break;
 163                 default:
 164                         LOG_ERROR("BUG: unknown bank->size encountered");
 165                         exit(-1);
 166         }
 167
 168         num_sectors = b0_sectors + b1_sectors;
 169
 170         bank->num_sectors = num_sectors;
 171         bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
 172         str7x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
 173
 174         num_sectors = 0;
 175
 176         for (i = 0; i < b0_sectors; i++)
 177         {
 178                 bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
 179                 bank->sectors[num_sectors].size = mem_layout_str7bank0[i].sector_size;
 180                 bank->sectors[num_sectors].is_erased = -1;
 181                 /* the reset_init handler marks all the sectors unprotected,
 182                  * matching hardware after reset; keep the driver in sync
 183                  */
 184                 bank->sectors[num_sectors].is_protected = 0;
 185                 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
 186         }
 187
 188         for (i = 0; i < b1_sectors; i++)
 189         {
 190                 bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
 191                 bank->sectors[num_sectors].size = mem_layout_str7bank1[i].sector_size;
 192                 bank->sectors[num_sectors].is_erased = -1;
 193                 /* the reset_init handler marks all the sectors unprotected,
 194                  * matching hardware after reset; keep the driver in sync
 195                  */
 196                 bank->sectors[num_sectors].is_protected = 0;
 197                 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank1[i].sector_bit;
 198         }
 199
 200         return ERROR_OK;
 201 }
 202
 203 /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
 204  */
 205 FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command)
 206 {
 207         struct str7x_flash_bank *str7x_info;
 208
 209         if (CMD_ARGC < 7)
 210         {
 211                 return ERROR_COMMAND_SYNTAX_ERROR;
 212         }
 213
 214         str7x_info = malloc(sizeof(struct str7x_flash_bank));
 215         bank->driver_priv = str7x_info;
 216
 217         /* set default bits for str71x flash */
 218         str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA1 | FLASH_BSYA0);
 219         str7x_info->disable_bit = (1 << 1);
 220
 221         if (strcmp(CMD_ARGV[6], "STR71x") == 0)
 222         {
 223                 str7x_info->register_base = 0x40100000;
 224         }
 225         else if (strcmp(CMD_ARGV[6], "STR73x") == 0)
 226         {
 227                 str7x_info->register_base = 0x80100000;
 228                 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA0);
 229         }
 230         else if (strcmp(CMD_ARGV[6], "STR75x") == 0)
 231         {
 232                 str7x_info->register_base = 0x20100000;
 233                 str7x_info->disable_bit = (1 << 0);
 234         }
 235         else
 236         {
 237                 LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV[6]);
 238                 free(str7x_info);
 239                 return ERROR_FLASH_BANK_INVALID;
 240         }
 241
 242         str7x_build_block_list(bank);
 243
 244         str7x_info->write_algorithm = NULL;
 245
 246         return ERROR_OK;
 247 }
 248
 249 /* wait for flash to become idle or report errors.
 250
 251    FIX!!! what's the maximum timeout??? The documentation doesn't
 252    state any maximum time.... by inspection it seems > 1000ms is to be
 253    expected.
 254
 255    10000ms is long enough that it should cover anything, yet not
 256    quite be equivalent to an infinite loop.
 257
 258  */
 259 static int str7x_waitbusy(struct flash_bank *bank)
 260 {
 261         int err;
 262         int i;
 263         struct target *target = bank->target;
 264         struct str7x_flash_bank *str7x_info = bank->driver_priv;
 265
 266         for (i = 0 ; i < 10000; i++)
 267         {
 268                 uint32_t retval;
 269                 err = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
 270                 if (err != ERROR_OK)
 271                         return err;
 272
 273                 if ((retval & str7x_info->busy_bits) == 0)
 274                         return ERROR_OK;
 275
 276                 alive_sleep(1);
 277         }
 278         LOG_ERROR("Timed out waiting for str7x flash");
 279         return ERROR_FAIL;
 280 }
 281
 282
 283 static int str7x_result(struct flash_bank *bank)
 284 {
 285         struct target *target = bank->target;
 286         uint32_t flash_flags;
 287
 288         int retval;
 289         retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &flash_flags);
 290         if (retval != ERROR_OK)
 291                 return retval;
 292
 293         if (flash_flags & FLASH_WPF)
 294         {
 295                 LOG_ERROR("str7x hw write protection set");
 296                 retval = ERROR_FAIL;
 297         }
 298         if (flash_flags & FLASH_RESER)
 299         {
 300                 LOG_ERROR("str7x suspended program erase not resumed");
 301                 retval = ERROR_FAIL;
 302         }
 303         if (flash_flags & FLASH_10ER)
 304         {
 305                 LOG_ERROR("str7x trying to set bit to 1 when it is already 0");
 306                 retval = ERROR_FAIL;
 307         }
 308         if (flash_flags & FLASH_PGER)
 309         {
 310                 LOG_ERROR("str7x program error");
 311                 retval = ERROR_FAIL;
 312         }
 313         if (flash_flags & FLASH_ERER)
 314         {
 315                 LOG_ERROR("str7x erase error");
 316                 retval = ERROR_FAIL;
 317         }
 318         if (retval == ERROR_OK)
 319         {
 320                 if (flash_flags & FLASH_ERR)
 321                 {
 322                         /* this should always be set if one of the others are set... */
 323                         LOG_ERROR("str7x write operation failed / bad setup");
 324                         retval = ERROR_FAIL;
 325                 }
 326         }
 327
 328         return retval;
 329 }
 330
 331 static int str7x_protect_check(struct flash_bank *bank)
 332 {
 333         struct str7x_flash_bank *str7x_info = bank->driver_priv;
 334         struct target *target = bank->target;
 335
 336         int i;
 337         uint32_t flash_flags;
 338
 339         if (bank->target->state != TARGET_HALTED)
 340         {
 341                 LOG_ERROR("Target not halted");
 342                 return ERROR_TARGET_NOT_HALTED;
 343         }
 344
 345         int retval;
 346         retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &flash_flags);
 347         if (retval != ERROR_OK)
 348                 return retval;
 349
 350         for (i = 0; i < bank->num_sectors; i++)
 351         {
 352                 if (flash_flags & str7x_info->sector_bits[i])
 353                         bank->sectors[i].is_protected = 0;
 354                 else
 355                         bank->sectors[i].is_protected = 1;
 356         }
 357
 358         return ERROR_OK;
 359 }
 360
 361 static int str7x_erase(struct flash_bank *bank, int first, int last)
 362 {
 363         struct str7x_flash_bank *str7x_info = bank->driver_priv;
 364         struct target *target = bank->target;
 365
 366         int i;
 367         uint32_t cmd;
 368         uint32_t sectors = 0;
 369         int err;
 370
 371         if (bank->target->state != TARGET_HALTED)
 372         {
 373                 LOG_ERROR("Target not halted");
 374                 return ERROR_TARGET_NOT_HALTED;
 375         }
 376
 377         for (i = first; i <= last; i++)
 378         {
 379                 sectors |= str7x_info->sector_bits[i];
 380         }
 381
 382         LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
 383
 384         /* clear FLASH_ER register */
 385         err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
 386         if (err != ERROR_OK)
 387                 return err;
 388
 389         cmd = FLASH_SER;
 390         err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 391         if (err != ERROR_OK)
 392                 return err;
 393
 394         cmd = sectors;
 395         err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
 396         if (err != ERROR_OK)
 397                 return err;
 398
 399         cmd = FLASH_SER | FLASH_WMS;
 400         err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 401         if (err != ERROR_OK)
 402                 return err;
 403
 404         err = str7x_waitbusy(bank);
 405         if (err != ERROR_OK)
 406                 return err;
 407
 408         err = str7x_result(bank);
 409         if (err != ERROR_OK)
 410                 return err;
 411
 412         for (i = first; i <= last; i++)
 413                 bank->sectors[i].is_erased = 1;
 414
 415         return ERROR_OK;
 416 }
 417
 418 static int str7x_protect(struct flash_bank *bank, int set, int first, int last)
 419 {
 420         struct str7x_flash_bank *str7x_info = bank->driver_priv;
 421         struct target *target = bank->target;
 422         int i;
 423         uint32_t cmd;
 424         uint32_t protect_blocks;
 425
 426         if (bank->target->state != TARGET_HALTED)
 427         {
 428                 LOG_ERROR("Target not halted");
 429                 return ERROR_TARGET_NOT_HALTED;
 430         }
 431
 432         protect_blocks = 0xFFFFFFFF;
 433
 434         if (set)
 435         {
 436                 for (i = first; i <= last; i++)
 437                         protect_blocks &= ~(str7x_info->sector_bits[i]);
 438         }
 439
 440         /* clear FLASH_ER register */
 441         int err;
 442         err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
 443         if (err != ERROR_OK)
 444                 return err;
 445
 446         cmd = FLASH_SPR;
 447         err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 448         if (err != ERROR_OK)
 449                 return err;
 450
 451         cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
 452         err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
 453         if (err != ERROR_OK)
 454                 return err;
 455
 456         cmd = protect_blocks;
 457         err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
 458         if (err != ERROR_OK)
 459                 return err;
 460
 461         cmd = FLASH_SPR | FLASH_WMS;
 462         err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 463         if (err != ERROR_OK)
 464                 return err;
 465
 466         err = str7x_waitbusy(bank);
 467         if (err != ERROR_OK)
 468                 return err;
 469
 470         err = str7x_result(bank);
 471         if (err != ERROR_OK)
 472                 return err;
 473
 474         return ERROR_OK;
 475 }
 476
 477 static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer,
 478                 uint32_t offset, uint32_t count)
 479 {
 480         struct str7x_flash_bank *str7x_info = bank->driver_priv;
 481         struct target *target = bank->target;
 482         uint32_t buffer_size = 32768;
 483         struct working_area *source;
 484         uint32_t address = bank->base + offset;
 485         struct reg_param reg_params[6];
 486         struct arm_algorithm armv4_5_info;
 487         int retval = ERROR_OK;
 488
 489         /* see contib/loaders/flash/str7x.s for src */
 490
 491         static const uint32_t str7x_flash_write_code[] = {
 492                                         /* write:                               */
 493                 0xe3a04201, /*  mov r4, #0x10000000     */
 494                 0xe5824000, /*  str r4, [r2, #0x0]      */
 495                 0xe5821010, /*  str r1, [r2, #0x10]     */
 496                 0xe4904004, /*  ldr r4, [r0], #4        */
 497                 0xe5824008, /*  str r4, [r2, #0x8]      */
 498                 0xe4904004, /*  ldr r4, [r0], #4        */
 499                 0xe582400c, /*  str r4, [r2, #0xc]      */
 500                 0xe3a04209, /*  mov r4, #0x90000000     */
 501                 0xe5824000, /*  str r4, [r2, #0x0]      */
 502                             /* busy:                            */
 503                 0xe5924000, /*  ldr r4, [r2, #0x0]      */
 504                 0xe1140005,     /*      tst r4, r5                      */
 505                 0x1afffffc, /*  bne busy                        */
 506                 0xe5924014, /*  ldr r4, [r2, #0x14]     */
 507                 0xe31400ff, /*  tst r4, #0xff           */
 508                 0x03140c01, /*  tsteq r4, #0x100        */
 509                 0x1a000002, /*  bne exit                        */
 510                 0xe2811008, /*  add r1, r1, #0x8        */
 511                 0xe2533001, /*  subs r3, r3, #1         */
 512                 0x1affffec, /*  bne write                       */
 513                                         /* exit:                                */
 514                 0xeafffffe, /*  b exit                          */
 515         };
 516
 517         /* flash write code */
 518         if (target_alloc_working_area_try(target, sizeof(str7x_flash_write_code),
 519                         &str7x_info->write_algorithm) != ERROR_OK)
 520         {
 521                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 522         };
 523
 524         target_write_buffer(target, str7x_info->write_algorithm->address,
 525                         sizeof(str7x_flash_write_code),
 526                         (uint8_t*)str7x_flash_write_code);
 527
 528         /* memory buffer */
 529         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
 530         {
 531                 buffer_size /= 2;
 532                 if (buffer_size <= 256)
 533                 {
 534                         /* if we already allocated the writing code, but failed to get a
 535                          * buffer, free the algorithm */
 536                         if (str7x_info->write_algorithm)
 537                                 target_free_working_area(target, str7x_info->write_algorithm);
 538
 539                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 540                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 541                 }
 542         }
 543
 544         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 545         armv4_5_info.core_mode = ARM_MODE_SVC;
 546         armv4_5_info.core_state = ARM_STATE_ARM;
 547
 548         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 549         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 550         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 551         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
 552         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
 553         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
 554
 555         while (count > 0)
 556         {
 557                 uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
 558
 559                 target_write_buffer(target, source->address, thisrun_count * 8, buffer);
 560
 561                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 562                 buf_set_u32(reg_params[1].value, 0, 32, address);
 563                 buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
 564                 buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
 565                 buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
 566
 567                 if ((retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
 568                                 str7x_info->write_algorithm->address,
 569                                 str7x_info->write_algorithm->address + (sizeof(str7x_flash_write_code) - 4),
 570                                 10000, &armv4_5_info)) != ERROR_OK)
 571                 {
 572                         break;
 573                 }
 574
 575                 if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
 576                 {
 577                         retval = str7x_result(bank);
 578                         break;
 579                 }
 580
 581                 buffer += thisrun_count * 8;
 582                 address += thisrun_count * 8;
 583                 count -= thisrun_count;
 584         }
 585
 586         target_free_working_area(target, source);
 587         target_free_working_area(target, str7x_info->write_algorithm);
 588
 589         destroy_reg_param(&reg_params[0]);
 590         destroy_reg_param(&reg_params[1]);
 591         destroy_reg_param(&reg_params[2]);
 592         destroy_reg_param(&reg_params[3]);
 593         destroy_reg_param(&reg_params[4]);
 594         destroy_reg_param(&reg_params[5]);
 595
 596         return retval;
 597 }
 598
 599 static int str7x_write(struct flash_bank *bank, uint8_t *buffer,
 600                 uint32_t offset, uint32_t count)
 601 {
 602         struct target *target = bank->target;
 603         uint32_t dwords_remaining = (count / 8);
 604         uint32_t bytes_remaining = (count & 0x00000007);
 605         uint32_t address = bank->base + offset;
 606         uint32_t bytes_written = 0;
 607         uint32_t cmd;
 608         int retval;
 609         uint32_t check_address = offset;
 610         int i;
 611
 612         if (bank->target->state != TARGET_HALTED)
 613         {
 614                 LOG_ERROR("Target not halted");
 615                 return ERROR_TARGET_NOT_HALTED;
 616         }
 617
 618         if (offset & 0x7)
 619         {
 620                 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset);
 621                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 622         }
 623
 624         for (i = 0; i < bank->num_sectors; i++)
 625         {
 626                 uint32_t sec_start = bank->sectors[i].offset;
 627                 uint32_t sec_end = sec_start + bank->sectors[i].size;
 628
 629                 /* check if destination falls within the current sector */
 630                 if ((check_address >= sec_start) && (check_address < sec_end))
 631                 {
 632                         /* check if destination ends in the current sector */
 633                         if (offset + count < sec_end)
 634                                 check_address = offset + count;
 635                         else
 636                                 check_address = sec_end;
 637                 }
 638         }
 639
 640         if (check_address != offset + count)
 641                 return ERROR_FLASH_DST_OUT_OF_BANK;
 642
 643         /* clear FLASH_ER register */
 644         target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
 645
 646         /* multiple dwords (8-byte) to be programmed? */
 647         if (dwords_remaining > 0)
 648         {
 649                 /* try using a block write */
 650                 if ((retval = str7x_write_block(bank, buffer, offset,
 651                                 dwords_remaining)) != ERROR_OK)
 652                 {
 653                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 654                         {
 655                                 /* if block write failed (no sufficient working area),
 656                                  * we use normal (slow) single dword accesses */
 657                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 658                         } else
 659                         {
 660                                 return retval;
 661                         }
 662                 }
 663                 else
 664                 {
 665                         buffer += dwords_remaining * 8;
 666                         address += dwords_remaining * 8;
 667                         dwords_remaining = 0;
 668                 }
 669         }
 670
 671         while (dwords_remaining > 0)
 672         {
 673                 /* command */
 674                 cmd = FLASH_DWPG;
 675                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 676
 677                 /* address */
 678                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
 679
 680                 /* data word 1 */
 681                 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
 682                                 4, 1, buffer + bytes_written);
 683                 bytes_written += 4;
 684
 685                 /* data word 2 */
 686                 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
 687                                 4, 1, buffer + bytes_written);
 688                 bytes_written += 4;
 689
 690                 /* start programming cycle */
 691                 cmd = FLASH_DWPG | FLASH_WMS;
 692                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 693
 694                 int err;
 695                 err = str7x_waitbusy(bank);
 696                 if (err != ERROR_OK)
 697                         return err;
 698
 699                 err = str7x_result(bank);
 700                 if (err != ERROR_OK)
 701                         return err;
 702
 703                 dwords_remaining--;
 704                 address += 8;
 705         }
 706
 707         if (bytes_remaining)
 708         {
 709                 uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
 710                 i = 0;
 711
 712                 while (bytes_remaining > 0)
 713                 {
 714                         last_dword[i++] = *(buffer + bytes_written);
 715                         bytes_remaining--;
 716                         bytes_written++;
 717                 }
 718
 719                 /* command */
 720                 cmd = FLASH_DWPG;
 721                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 722
 723                 /* address */
 724                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
 725
 726                 /* data word 1 */
 727                 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
 728                                 4, 1, last_dword);
 729                 bytes_written += 4;
 730
 731                 /* data word 2 */
 732                 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
 733                                 4, 1, last_dword + 4);
 734                 bytes_written += 4;
 735
 736                 /* start programming cycle */
 737                 cmd = FLASH_DWPG | FLASH_WMS;
 738                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
 739
 740                 int err;
 741                 err = str7x_waitbusy(bank);
 742                 if (err != ERROR_OK)
 743                         return err;
 744
 745                 err = str7x_result(bank);
 746                 if (err != ERROR_OK)
 747                         return err;
 748         }
 749
 750         return ERROR_OK;
 751 }
 752
 753 static int str7x_probe(struct flash_bank *bank)
 754 {
 755         return ERROR_OK;
 756 }
 757
 758 #if 0
 759 COMMAND_HANDLER(str7x_handle_part_id_command)
 760 {
 761         return ERROR_OK;
 762 }
 763 #endif
 764
 765 static int get_str7x_info(struct flash_bank *bank, char *buf, int buf_size)
 766 {
 767         snprintf(buf, buf_size, "str7x flash driver info");
 768         /* STR7x flash doesn't support sector protection interrogation.
 769          * FLASH_NVWPAR acts as a write only register; its read value
 770          * doesn't reflect the actual protection state of the sectors.
 771          */
 772         LOG_WARNING("STR7x flash lock information might not be correct "
 773                         "due to hardware limitations.");
 774         return ERROR_OK;
 775 }
 776
 777 COMMAND_HANDLER(str7x_handle_disable_jtag_command)
 778 {
 779         struct target *target = NULL;
 780         struct str7x_flash_bank *str7x_info = NULL;
 781
 782         uint32_t flash_cmd;
 783         uint16_t ProtectionLevel = 0;
 784         uint16_t ProtectionRegs;
 785
 786         if (CMD_ARGC < 1)
 787         {
 788                 return ERROR_COMMAND_SYNTAX_ERROR;
 789         }
 790
 791         struct flash_bank *bank;
 792         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 793         if (ERROR_OK != retval)
 794                 return retval;
 795
 796         str7x_info = bank->driver_priv;
 797
 798         target = bank->target;
 799
 800         if (target->state != TARGET_HALTED)
 801         {
 802                 LOG_ERROR("Target not halted");
 803                 return ERROR_TARGET_NOT_HALTED;
 804         }
 805
 806         /* first we get protection status */
 807         uint32_t reg;
 808         target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &reg);
 809
 810         if (!(reg & str7x_info->disable_bit))
 811         {
 812                 ProtectionLevel = 1;
 813         }
 814
 815         target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &reg);
 816         ProtectionRegs = ~(reg >> 16);
 817
 818         while (((ProtectionRegs) != 0) && (ProtectionLevel < 16))
 819         {
 820                 ProtectionRegs >>= 1;
 821                 ProtectionLevel++;
 822         }
 823
 824         if (ProtectionLevel == 0)
 825         {
 826                 flash_cmd = FLASH_SPR;
 827                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
 828                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
 829                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), 0xFFFFFFFD);
 830                 flash_cmd = FLASH_SPR | FLASH_WMS;
 831                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
 832         }
 833         else
 834         {
 835                 flash_cmd = FLASH_SPR;
 836                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
 837                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
 838                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0),
 839                                 ~(1 << (15 + ProtectionLevel)));
 840                 flash_cmd = FLASH_SPR | FLASH_WMS;
 841                 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
 842         }
 843
 844         return ERROR_OK;
 845 }
 846
 847 static const struct command_registration str7x_exec_command_handlers[] = {
 848         {
 849                 .name = "disable_jtag",
 850                 .usage = "<bank>",
 851                 .handler = str7x_handle_disable_jtag_command,
 852                 .mode = COMMAND_EXEC,
 853                 .help = "disable jtag access",
 854         },
 855         COMMAND_REGISTRATION_DONE
 856 };
 857
 858 static const struct command_registration str7x_command_handlers[] = {
 859         {
 860                 .name = "str7x",
 861                 .mode = COMMAND_ANY,
 862                 .help = "str7x flash command group",
 863                 .chain = str7x_exec_command_handlers,
 864         },
 865         COMMAND_REGISTRATION_DONE
 866 };
 867
 868 struct flash_driver str7x_flash = {
 869         .name = "str7x",
 870         .commands = str7x_command_handlers,
 871         .flash_bank_command = str7x_flash_bank_command,
 872         .erase = str7x_erase,
 873         .protect = str7x_protect,
 874         .write = str7x_write,
 875         .read = default_flash_read,
 876         .probe = str7x_probe,
 877         .auto_probe = str7x_probe,
 878         .erase_check = default_flash_blank_check,
 879         .protect_check = str7x_protect_check,
 880         .info = get_str7x_info,
 881 };