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   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com>       *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19
  20 /* STM Serial Memory Interface (SMI) controller is a SPI bus controller
  21  * specifically designed for SPI memories.
  22  * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
  23  * Two working modes are available:
  24  * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
  25  *   on the bus.
  26  * - HW mode: the SPI but is under SMI control. Memory content is directly
  27  *   accessible in CPU memory space. CPU can read, write and execute memory
  28  *   content. */
  29
  30 /* ATTENTION:
  31  * To have flash memory mapped in CPU memory space, the SMI controller
  32  * have to be in "HW mode". This requires following constraints:
  33  * 1) The command "reset init" have to initialize SMI controller and put
  34  *    it in HW mode;
  35  * 2) every command in this file have to return to prompt in HW mode. */
  36
  37 #ifdef HAVE_CONFIG_H
  38 #include "config.h"
  39 #endif
  40
  41 #include "imp.h"
  42 #include <jtag/jtag.h>
  43 #include <helper/time_support.h>
  44
  45 #define SMI_READ_REG(a) (_SMI_READ_REG(a))
  46 #define _SMI_READ_REG(a)                        \
  47 {                                                                       \
  48         int __a;                                                \
  49         uint32_t __v;                                   \
  50                                                                         \
  51         __a = target_read_u32(target, io_base + (a), &__v); \
  52         if (__a != ERROR_OK)                    \
  53                 return __a;                                     \
  54         __v;                                                    \
  55 }
  56
  57 #define SMI_WRITE_REG(a, v)                     \
  58 {                                                                       \
  59         int __r;                                                \
  60                                                                         \
  61         __r = target_write_u32(target, io_base + (a), (v)); \
  62         if (__r != ERROR_OK)                    \
  63                 return __r;                                     \
  64 }
  65
  66 #define SMI_POLL_TFF(timeout)           \
  67 {                                                                       \
  68         int __r;                                                \
  69                                                                         \
  70         __r = poll_tff(target, io_base, timeout); \
  71         if (__r != ERROR_OK)                    \
  72                 return __r;                                     \
  73 }
  74
  75 #define SMI_SET_SW_MODE()       SMI_WRITE_REG(SMI_CR1, \
  76         SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
  77 #define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
  78         (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
  79 #define SMI_SET_HW_MODE()       SMI_WRITE_REG(SMI_CR1, \
  80         SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
  81 #define SMI_CLEAR_TFF()         SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
  82
  83 #define SMI_BANK_SIZE      (0x01000000)
  84
  85 #define SMI_CR1 (0x00) /* Control register 1 */
  86 #define SMI_CR2 (0x04) /* Control register 2 */
  87 #define SMI_SR  (0x08) /* Status register */
  88 #define SMI_TR  (0x0c) /* TX */
  89 #define SMI_RR  (0x10) /* RX */
  90
  91 /* fields in SMI_CR1 */
  92 #define SMI_SW_MODE       0x10000000 /* set to enable SW Mode */
  93 #define SMI_WB_MODE       0x20000000 /* Write Burst Mode */
  94
  95 /* fields in SMI_CR2 */
  96 #define SMI_TX_LEN_1      0x00000001 /* data length = 1 byte */
  97 #define SMI_TX_LEN_4      0x00000004 /* data length = 4 byte */
  98 #define SMI_RX_LEN_3      0x00000030 /* data length = 3 byte */
  99 #define SMI_SEND          0x00000080 /* Send data */
 100 #define SMI_RSR           0x00000400 /* reads status reg */
 101 #define SMI_WE            0x00000800 /* Write Enable */
 102 #define SMI_SEL_BANK0     0x00000000 /* Select Bank0 */
 103 #define SMI_SEL_BANK1     0x00001000 /* Select Bank1 */
 104 #define SMI_SEL_BANK2     0x00002000 /* Select Bank2 */
 105 #define SMI_SEL_BANK3     0x00003000 /* Select Bank3 */
 106
 107 /* fields in SMI_SR */
 108 #define SMI_WIP_BIT       0x00000001 /* WIP Bit of SPI SR on SMI SR */
 109 #define SMI_WEL_BIT       0x00000002 /* WEL Bit of SPI SR on SMI SR */
 110 #define SMI_TFF           0x00000100 /* Transfer Finished Flag */
 111
 112 /* Commands */
 113 #define SMI_READ_ID       0x0000009F /* Read Flash Identification */
 114
 115 /* Timeout in ms */
 116 #define SMI_CMD_TIMEOUT   (100)
 117 #define SMI_PROBE_TIMEOUT (100)
 118 #define SMI_MAX_TIMEOUT  (3000)
 119
 120 struct stmsmi_flash_bank {
 121         int probed;
 122         uint32_t io_base;
 123         uint32_t bank_num;
 124         struct flash_device *dev;
 125 };
 126
 127 /* data structure to maintain flash ids from different vendors */
 128 struct flash_device {
 129         char *name;
 130         uint8_t erase_cmd;
 131         uint32_t device_id;
 132         uint32_t pagesize;
 133         unsigned long sectorsize;
 134         unsigned long size_in_bytes;
 135 };
 136
 137 #define FLASH_ID(n, es, id, psize, ssize, size) \
 138 {                               \
 139         .name = n,              \
 140         .erase_cmd = es,        \
 141         .device_id = id,        \
 142         .pagesize = psize,      \
 143         .sectorsize = ssize,    \
 144         .size_in_bytes = size   \
 145 }
 146
 147 /* List below is taken from Linux driver. It is not exhaustive of all the
 148  * possible SPI memories, nor exclusive for SMI. Could be shared with
 149  * other SPI drivers. */
 150 static struct flash_device flash_devices[] = {
 151         /* name, erase_cmd, device_id, pagesize, sectorsize, size_in_bytes */
 152         FLASH_ID("st m25p05",      0xd8, 0x00102020, 0x80,  0x8000,  0x10000),
 153         FLASH_ID("st m25p10",      0xd8, 0x00112020, 0x80,  0x8000,  0x20000),
 154         FLASH_ID("st m25p20",      0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
 155         FLASH_ID("st m25p40",      0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
 156         FLASH_ID("st m25p80",      0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
 157         FLASH_ID("st m25p16",      0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
 158         FLASH_ID("st m25p32",      0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
 159         FLASH_ID("st m25p64",      0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
 160         FLASH_ID("st m25p128",     0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
 161         FLASH_ID("st m45pe10",     0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
 162         FLASH_ID("st m45pe20",     0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
 163         FLASH_ID("st m45pe40",     0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
 164         FLASH_ID("st m45pe80",     0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
 165         FLASH_ID("sp s25fl004",    0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
 166         FLASH_ID("sp s25fl008",    0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
 167         FLASH_ID("sp s25fl016",    0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
 168         FLASH_ID("sp s25fl032",    0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
 169         FLASH_ID("sp s25fl064",    0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
 170         FLASH_ID("atmel 25f512",   0x52, 0x0065001f, 0x80,  0x8000,  0x10000),
 171         FLASH_ID("atmel 25f1024",  0x52, 0x0060001f, 0x100, 0x8000,  0x20000),
 172         FLASH_ID("atmel 25f2048",  0x52, 0x0063001f, 0x100, 0x10000, 0x40000),
 173         FLASH_ID("atmel 25f4096",  0x52, 0x0064001f, 0x100, 0x10000, 0x80000),
 174         FLASH_ID("atmel 25fs040",  0xd7, 0x0004661f, 0x100, 0x10000, 0x80000),
 175         FLASH_ID("mac 25l512",     0xd8, 0x001020c2, 0x010, 0x10000, 0x10000),
 176         FLASH_ID("mac 25l1005",    0xd8, 0x001120c2, 0x010, 0x10000, 0x20000),
 177         FLASH_ID("mac 25l2005",    0xd8, 0x001220c2, 0x010, 0x10000, 0x40000),
 178         FLASH_ID("mac 25l4005",    0xd8, 0x001320c2, 0x010, 0x10000, 0x80000),
 179         FLASH_ID("mac 25l8005",    0xd8, 0x001420c2, 0x010, 0x10000, 0x100000),
 180         FLASH_ID("mac 25l1605",    0xd8, 0x001520c2, 0x100, 0x10000, 0x200000),
 181         FLASH_ID("mac 25l3205",    0xd8, 0x001620c2, 0x100, 0x10000, 0x400000),
 182         FLASH_ID("mac 25l6405",    0xd8, 0x001720c2, 0x100, 0x10000, 0x800000),
 183         FLASH_ID(NULL,             0,    0,          0,     0,       0)
 184 };
 185
 186 struct stmsmi_target {
 187         char *name;
 188         uint32_t tap_idcode;
 189         uint32_t smi_base;
 190         uint32_t io_base;
 191 };
 192
 193 static struct stmsmi_target target_devices[] = {
 194         /* name,          tap_idcode, smi_base,   io_base */
 195         { "SPEAr3xx/6xx", 0x07926041, 0xf8000000, 0xfc000000 },
 196         { "STR75x",       0x4f1f0041, 0x80000000, 0x90000000 },
 197         { NULL,           0,          0,          0 }
 198 };
 199
 200 FLASH_BANK_COMMAND_HANDLER(stmsmi_flash_bank_command)
 201 {
 202         struct stmsmi_flash_bank *stmsmi_info;
 203
 204         LOG_DEBUG("%s", __func__);
 205
 206         if (CMD_ARGC < 6)
 207                 return ERROR_COMMAND_SYNTAX_ERROR;
 208
 209         stmsmi_info = malloc(sizeof(struct stmsmi_flash_bank));
 210         if (stmsmi_info == NULL) {
 211                 LOG_ERROR("not enough memory");
 212                 return ERROR_FAIL;
 213         }
 214
 215         bank->driver_priv = stmsmi_info;
 216         stmsmi_info->probed = 0;
 217
 218         return ERROR_OK;
 219 }
 220
 221 /* Poll transmit finished flag */
 222 /* timeout in ms */
 223 static int poll_tff(struct target *target, uint32_t io_base, int timeout)
 224 {
 225         long long endtime;
 226
 227         if (SMI_READ_REG(SMI_SR) & SMI_TFF)
 228                 return ERROR_OK;
 229
 230         endtime = timeval_ms() + timeout;
 231         do {
 232                 alive_sleep(1);
 233                 if (SMI_READ_REG(SMI_SR) & SMI_TFF)
 234                         return ERROR_OK;
 235         } while (timeval_ms() < endtime);
 236
 237         LOG_ERROR("Timeout while polling TFF");
 238         return ERROR_FLASH_OPERATION_FAILED;
 239 }
 240
 241 /* Read the status register of the external SPI flash chip.
 242  * The operation is triggered by setting SMI_RSR bit.
 243  * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
 244 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
 245 {
 246         struct target *target = bank->target;
 247         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 248         uint32_t io_base = stmsmi_info->io_base;
 249
 250         /* clear transmit finished flag */
 251         SMI_CLEAR_TFF();
 252
 253         /* Read status */
 254         SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_RSR);
 255
 256         /* Poll transmit finished flag */
 257         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 258
 259         /* clear transmit finished flag */
 260         SMI_CLEAR_TFF();
 261
 262         *status = SMI_READ_REG(SMI_SR) & 0x0000ffff;
 263
 264         /* clean-up SMI_CR2 */
 265         SMI_WRITE_REG(SMI_CR2, 0); /* AB: Required ? */
 266
 267         return ERROR_OK;
 268 }
 269
 270 /* check for WIP (write in progress) bit in status register */
 271 /* timeout in ms */
 272 static int wait_till_ready(struct flash_bank *bank, int timeout)
 273 {
 274         uint32_t status;
 275         int retval;
 276         long long endtime;
 277
 278         endtime = timeval_ms() + timeout;
 279         do {
 280                 /* read flash status register */
 281                 retval = read_status_reg(bank, &status);
 282                 if (retval != ERROR_OK)
 283                         return retval;
 284
 285                 if ((status & SMI_WIP_BIT) == 0)
 286                         return ERROR_OK;
 287                 alive_sleep(1);
 288         } while (timeval_ms() < endtime);
 289
 290         LOG_ERROR("timeout");
 291         return ERROR_FAIL;
 292 }
 293
 294 /* Send "write enable" command to SPI flash chip.
 295  * The operation is triggered by setting SMI_WE bit, and SMI sends
 296  * the proper SPI command (0x06) */
 297 static int smi_write_enable(struct flash_bank *bank)
 298 {
 299         struct target *target = bank->target;
 300         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 301         uint32_t io_base = stmsmi_info->io_base;
 302         uint32_t status;
 303         int retval;
 304
 305         /* Enter in HW mode */
 306         SMI_SET_HW_MODE(); /* AB: is this correct ?*/
 307
 308         /* clear transmit finished flag */
 309         SMI_CLEAR_TFF();
 310
 311         /* Send write enable command */
 312         SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_WE);
 313
 314         /* Poll transmit finished flag */
 315         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 316
 317         /* read flash status register */
 318         retval = read_status_reg(bank, &status);
 319         if (retval != ERROR_OK)
 320                 return retval;
 321
 322         /* Check write enabled */
 323         if ((status & SMI_WEL_BIT) == 0) {
 324                 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
 325                 return ERROR_FAIL;
 326         }
 327
 328         return ERROR_OK;
 329 }
 330
 331 static uint32_t erase_command(struct stmsmi_flash_bank *stmsmi_info,
 332         uint32_t offset)
 333 {
 334         union {
 335                 uint32_t command;
 336                 uint8_t x[4];
 337         } cmd;
 338
 339         cmd.x[0] = stmsmi_info->dev->erase_cmd;
 340         cmd.x[1] = offset >> 16;
 341         cmd.x[2] = offset >> 8;
 342         cmd.x[3] = offset;
 343
 344         return cmd.command;
 345 }
 346
 347 static int smi_erase_sector(struct flash_bank *bank, int sector)
 348 {
 349         struct target *target = bank->target;
 350         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 351         uint32_t io_base = stmsmi_info->io_base;
 352         uint32_t cmd;
 353         int retval;
 354
 355         retval = smi_write_enable(bank);
 356         if (retval != ERROR_OK)
 357                 return retval;
 358
 359         /* Switch to SW mode to send sector erase command */
 360         SMI_SET_SW_MODE();
 361
 362         /* clear transmit finished flag */
 363         SMI_CLEAR_TFF();
 364
 365         /* send SPI command "block erase" */
 366         cmd = erase_command(stmsmi_info, bank->sectors[sector].offset);
 367         SMI_WRITE_REG(SMI_TR, cmd);
 368         SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_SEND | SMI_TX_LEN_4);
 369
 370         /* Poll transmit finished flag */
 371         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 372
 373         /* poll WIP for end of self timed Sector Erase cycle */
 374         retval = wait_till_ready(bank, SMI_MAX_TIMEOUT);
 375         if (retval != ERROR_OK)
 376                 return retval;
 377
 378         return ERROR_OK;
 379 }
 380
 381 static int stmsmi_erase(struct flash_bank *bank, int first, int last)
 382 {
 383         struct target *target = bank->target;
 384         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 385         uint32_t io_base = stmsmi_info->io_base;
 386         int retval = ERROR_OK;
 387         int sector;
 388
 389         LOG_DEBUG("%s: from sector %d to sector %d", __func__, first, last);
 390
 391         if (target->state != TARGET_HALTED) {
 392                 LOG_ERROR("Target not halted");
 393                 return ERROR_TARGET_NOT_HALTED;
 394         }
 395
 396         if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
 397                 LOG_ERROR("Flash sector invalid");
 398                 return ERROR_FLASH_SECTOR_INVALID;
 399         }
 400
 401         if (!(stmsmi_info->probed)) {
 402                 LOG_ERROR("Flash bank not probed");
 403                 return ERROR_FLASH_BANK_NOT_PROBED;
 404         }
 405
 406         for (sector = first; sector <= last; sector++) {
 407                 if (bank->sectors[sector].is_protected) {
 408                         LOG_ERROR("Flash sector %d protected", sector);
 409                         return ERROR_FAIL;
 410                 }
 411         }
 412
 413         for (sector = first; sector <= last; sector++) {
 414                 retval = smi_erase_sector(bank, sector);
 415                 if (retval != ERROR_OK)
 416                         break;
 417                 keep_alive();
 418         }
 419
 420         /* Switch to HW mode before return to prompt */
 421         SMI_SET_HW_MODE();
 422         return retval;
 423 }
 424
 425 static int stmsmi_protect(struct flash_bank *bank, int set,
 426         int first, int last)
 427 {
 428         int sector;
 429
 430         for (sector = first; sector <= last; sector++)
 431                 bank->sectors[sector].is_protected = set;
 432         return ERROR_OK;
 433 }
 434
 435 static int smi_write_buffer(struct flash_bank *bank, uint8_t *buffer,
 436         uint32_t address, uint32_t len)
 437 {
 438         struct target *target = bank->target;
 439         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 440         uint32_t io_base = stmsmi_info->io_base;
 441         int retval;
 442
 443         LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
 444                         __func__, address, len);
 445
 446         retval = smi_write_enable(bank);
 447         if (retval != ERROR_OK)
 448                 return retval;
 449
 450         /* HW mode, write burst mode */
 451         SMI_SET_HWWB_MODE();
 452
 453         retval = target_write_buffer(target, address, len, buffer);
 454         if (retval != ERROR_OK)
 455                 return retval;
 456
 457         return ERROR_OK;
 458 }
 459
 460 static int stmsmi_write(struct flash_bank *bank, uint8_t *buffer,
 461         uint32_t offset, uint32_t count)
 462 {
 463         struct target *target = bank->target;
 464         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 465         uint32_t io_base = stmsmi_info->io_base;
 466         uint32_t cur_count, page_size, page_offset;
 467         int sector;
 468         int retval = ERROR_OK;
 469
 470         LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
 471                 __func__, offset, count);
 472
 473         if (target->state != TARGET_HALTED) {
 474                 LOG_ERROR("Target not halted");
 475                 return ERROR_TARGET_NOT_HALTED;
 476         }
 477
 478         if (offset + count > stmsmi_info->dev->size_in_bytes) {
 479                 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
 480                 count = stmsmi_info->dev->size_in_bytes - offset;
 481         }
 482
 483         /* Check sector protection */
 484         for (sector = 0; sector < bank->num_sectors; sector++) {
 485                 /* Start offset in or before this sector? */
 486                 /* End offset in or behind this sector? */
 487                 if ((offset <
 488                                 (bank->sectors[sector].offset + bank->sectors[sector].size))
 489                         && ((offset + count - 1) >= bank->sectors[sector].offset)
 490                         && bank->sectors[sector].is_protected) {
 491                         LOG_ERROR("Flash sector %d protected", sector);
 492                         return ERROR_FAIL;
 493                 }
 494         }
 495
 496         page_size = stmsmi_info->dev->pagesize;
 497
 498         /* unaligned buffer head */
 499         if (count > 0 && (offset & 3) != 0) {
 500                 cur_count = 4 - (offset & 3);
 501                 if (cur_count > count)
 502                         cur_count = count;
 503                 retval = smi_write_buffer(bank, buffer, bank->base + offset,
 504                         cur_count);
 505                 if (retval != ERROR_OK)
 506                         goto err;
 507                 offset += cur_count;
 508                 buffer += cur_count;
 509                 count -= cur_count;
 510         }
 511
 512         page_offset = offset % page_size;
 513         /* central part, aligned words */
 514         while (count >= 4) {
 515                 /* clip block at page boundary */
 516                 if (page_offset + count > page_size)
 517                         cur_count = page_size - page_offset;
 518                 else
 519                         cur_count = count & ~3;
 520
 521                 retval = smi_write_buffer(bank, buffer, bank->base + offset,
 522                         cur_count);
 523                 if (retval != ERROR_OK)
 524                         goto err;
 525
 526                 page_offset = 0;
 527                 buffer += cur_count;
 528                 offset += cur_count;
 529                 count -= cur_count;
 530
 531                 keep_alive();
 532         }
 533
 534         /* buffer tail */
 535         if (count > 0)
 536                 retval = smi_write_buffer(bank, buffer, bank->base + offset, count);
 537
 538 err:
 539         /* Switch to HW mode before return to prompt */
 540         SMI_SET_HW_MODE();
 541         return retval;
 542 }
 543
 544 /* Return ID of flash device */
 545 /* On exit, SW mode is kept */
 546 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
 547 {
 548         struct target *target = bank->target;
 549         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 550         uint32_t io_base = stmsmi_info->io_base;
 551         int retval;
 552
 553         if (target->state != TARGET_HALTED) {
 554                 LOG_ERROR("Target not halted");
 555                 return ERROR_TARGET_NOT_HALTED;
 556         }
 557
 558         /* poll WIP */
 559         retval = wait_till_ready(bank, SMI_PROBE_TIMEOUT);
 560         if (retval != ERROR_OK)
 561                 return retval;
 562
 563         /* enter in SW mode */
 564         SMI_SET_SW_MODE();
 565
 566         /* clear transmit finished flag */
 567         SMI_CLEAR_TFF();
 568
 569         /* Send SPI command "read ID" */
 570         SMI_WRITE_REG(SMI_TR, SMI_READ_ID);
 571         SMI_WRITE_REG(SMI_CR2,
 572                 stmsmi_info->bank_num | SMI_SEND | SMI_RX_LEN_3 | SMI_TX_LEN_1);
 573
 574         /* Poll transmit finished flag */
 575         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 576
 577         /* clear transmit finished flag */
 578         SMI_CLEAR_TFF();
 579
 580         /* read ID from Receive Register */
 581         *id = SMI_READ_REG(SMI_RR) & 0x00ffffff;
 582         return ERROR_OK;
 583 }
 584
 585 static int stmsmi_probe(struct flash_bank *bank)
 586 {
 587         struct target *target = bank->target;
 588         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 589         uint32_t io_base;
 590         struct flash_sector *sectors;
 591         uint32_t id = 0; /* silence uninitialized warning */
 592         struct stmsmi_target *target_device;
 593         int retval;
 594
 595         if (stmsmi_info->probed)
 596                 free(bank->sectors);
 597         stmsmi_info->probed = 0;
 598
 599         for (target_device = target_devices ; target_device->name ; ++target_device)
 600                 if (target_device->tap_idcode == target->tap->idcode)
 601                         break;
 602         if (!target_device->name) {
 603                 LOG_ERROR("Device ID 0x%" PRIx32 " is not known as SMI capable",
 604                                 target->tap->idcode);
 605                 return ERROR_FAIL;
 606         }
 607
 608         switch (bank->base - target_device->smi_base) {
 609                 case 0:
 610                         stmsmi_info->bank_num = SMI_SEL_BANK0;
 611                         break;
 612                 case SMI_BANK_SIZE:
 613                         stmsmi_info->bank_num = SMI_SEL_BANK1;
 614                         break;
 615                 case 2*SMI_BANK_SIZE:
 616                         stmsmi_info->bank_num = SMI_SEL_BANK2;
 617                         break;
 618                 case 3*SMI_BANK_SIZE:
 619                         stmsmi_info->bank_num = SMI_SEL_BANK3;
 620                         break;
 621                 default:
 622                         LOG_ERROR("Invalid SMI base address 0x%" PRIx32, bank->base);
 623                         return ERROR_FAIL;
 624         }
 625         io_base = target_device->io_base;
 626         stmsmi_info->io_base = io_base;
 627
 628         LOG_DEBUG("Valid SMI on device %s at address 0x%" PRIx32,
 629                 target_device->name, bank->base);
 630
 631         /* read and decode flash ID; returns in SW mode */
 632         retval = read_flash_id(bank, &id);
 633         SMI_SET_HW_MODE();
 634         if (retval != ERROR_OK)
 635                 return retval;
 636
 637         stmsmi_info->dev = NULL;
 638         for (struct flash_device *p = flash_devices; p->name ; p++)
 639                 if (p->device_id == id) {
 640                         stmsmi_info->dev = p;
 641                         break;
 642                 }
 643
 644         if (!stmsmi_info->dev) {
 645                 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
 646                 return ERROR_FAIL;
 647         }
 648
 649         LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
 650                 stmsmi_info->dev->name, stmsmi_info->dev->device_id);
 651
 652         /* Set correct size value */
 653         bank->size = stmsmi_info->dev->size_in_bytes;
 654
 655         /* create and fill sectors array */
 656         bank->num_sectors =
 657                 stmsmi_info->dev->size_in_bytes / stmsmi_info->dev->sectorsize;
 658         sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 659         if (sectors == NULL) {
 660                 LOG_ERROR("not enough memory");
 661                 return ERROR_FAIL;
 662         }
 663
 664         for (int sector = 0; sector < bank->num_sectors; sector++) {
 665                 sectors[sector].offset = sector * stmsmi_info->dev->sectorsize;
 666                 sectors[sector].size = stmsmi_info->dev->sectorsize;
 667                 sectors[sector].is_erased = -1;
 668                 sectors[sector].is_protected = 1;
 669         }
 670
 671         bank->sectors = sectors;
 672         stmsmi_info->probed = 1;
 673         return ERROR_OK;
 674 }
 675
 676 static int stmsmi_auto_probe(struct flash_bank *bank)
 677 {
 678         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 679         if (stmsmi_info->probed)
 680                 return ERROR_OK;
 681         return stmsmi_probe(bank);
 682 }
 683
 684 static int stmsmi_protect_check(struct flash_bank *bank)
 685 {
 686         /* Nothing to do. Protection is only handled in SW. */
 687         return ERROR_OK;
 688 }
 689
 690 static int get_stmsmi_info(struct flash_bank *bank, char *buf, int buf_size)
 691 {
 692         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 693
 694         if (!(stmsmi_info->probed)) {
 695                 snprintf(buf, buf_size,
 696                         "\nSMI flash bank not probed yet\n");
 697                 return ERROR_OK;
 698         }
 699
 700         snprintf(buf, buf_size, "\nSMI flash information:\n"
 701                 "  Device \'%s\' (ID 0x%08x)\n",
 702                 stmsmi_info->dev->name, stmsmi_info->dev->device_id);
 703
 704         return ERROR_OK;
 705 }
 706
 707 struct flash_driver stmsmi_flash = {
 708         .name = "stmsmi",
 709         .flash_bank_command = stmsmi_flash_bank_command,
 710         .erase = stmsmi_erase,
 711         .protect = stmsmi_protect,
 712         .write = stmsmi_write,
 713         .read = default_flash_read,
 714         .probe = stmsmi_probe,
 715         .auto_probe = stmsmi_auto_probe,
 716         .erase_check = default_flash_blank_check,
 717         .protect_check = stmsmi_protect_check,
 718         .info = get_stmsmi_info,
 719 };