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   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com>       *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  16  ***************************************************************************/
  17
  18 /* STM Serial Memory Interface (SMI) controller is a SPI bus controller
  19  * specifically designed for SPI memories.
  20  * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
  21  * Two working modes are available:
  22  * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
  23  *   on the bus.
  24  * - HW mode: the SPI but is under SMI control. Memory content is directly
  25  *   accessible in CPU memory space. CPU can read, write and execute memory
  26  *   content. */
  27
  28 /* ATTENTION:
  29  * To have flash memory mapped in CPU memory space, the SMI controller
  30  * have to be in "HW mode". This requires following constraints:
  31  * 1) The command "reset init" have to initialize SMI controller and put
  32  *    it in HW mode;
  33  * 2) every command in this file have to return to prompt in HW mode. */
  34
  35 #ifdef HAVE_CONFIG_H
  36 #include "config.h"
  37 #endif
  38
  39 #include "imp.h"
  40 #include "spi.h"
  41 #include <jtag/jtag.h>
  42 #include <helper/time_support.h>
  43
  44 #define SMI_READ_REG(a) (_SMI_READ_REG(a))
  45 #define _SMI_READ_REG(a)                        \
  46 {                                                                       \
  47         int __a;                                                \
  48         uint32_t __v;                                   \
  49                                                                         \
  50         __a = target_read_u32(target, io_base + (a), &__v); \
  51         if (__a != ERROR_OK)                    \
  52                 return __a;                                     \
  53         __v;                                                    \
  54 }
  55
  56 #define SMI_WRITE_REG(a, v)                     \
  57 {                                                                       \
  58         int __r;                                                \
  59                                                                         \
  60         __r = target_write_u32(target, io_base + (a), (v)); \
  61         if (__r != ERROR_OK)                    \
  62                 return __r;                                     \
  63 }
  64
  65 #define SMI_POLL_TFF(timeout)           \
  66 {                                                                       \
  67         int __r;                                                \
  68                                                                         \
  69         __r = poll_tff(target, io_base, timeout); \
  70         if (__r != ERROR_OK)                    \
  71                 return __r;                                     \
  72 }
  73
  74 #define SMI_SET_SW_MODE()       SMI_WRITE_REG(SMI_CR1, \
  75         SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
  76 #define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
  77         (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
  78 #define SMI_SET_HW_MODE()       SMI_WRITE_REG(SMI_CR1, \
  79         SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
  80 #define SMI_CLEAR_TFF()         SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
  81
  82 #define SMI_BANK_SIZE      (0x01000000)
  83
  84 #define SMI_CR1 (0x00) /* Control register 1 */
  85 #define SMI_CR2 (0x04) /* Control register 2 */
  86 #define SMI_SR  (0x08) /* Status register */
  87 #define SMI_TR  (0x0c) /* TX */
  88 #define SMI_RR  (0x10) /* RX */
  89
  90 /* fields in SMI_CR1 */
  91 #define SMI_SW_MODE       0x10000000 /* set to enable SW Mode */
  92 #define SMI_WB_MODE       0x20000000 /* Write Burst Mode */
  93
  94 /* fields in SMI_CR2 */
  95 #define SMI_TX_LEN_1      0x00000001 /* data length = 1 byte */
  96 #define SMI_TX_LEN_4      0x00000004 /* data length = 4 byte */
  97 #define SMI_RX_LEN_3      0x00000030 /* data length = 3 byte */
  98 #define SMI_SEND          0x00000080 /* Send data */
  99 #define SMI_RSR           0x00000400 /* reads status reg */
 100 #define SMI_WE            0x00000800 /* Write Enable */
 101 #define SMI_SEL_BANK0     0x00000000 /* Select Bank0 */
 102 #define SMI_SEL_BANK1     0x00001000 /* Select Bank1 */
 103 #define SMI_SEL_BANK2     0x00002000 /* Select Bank2 */
 104 #define SMI_SEL_BANK3     0x00003000 /* Select Bank3 */
 105
 106 /* fields in SMI_SR */
 107 #define SMI_TFF           0x00000100 /* Transfer Finished Flag */
 108
 109 /* Commands */
 110 #define SMI_READ_ID       0x0000009F /* Read Flash Identification */
 111
 112 /* Timeout in ms */
 113 #define SMI_CMD_TIMEOUT   (100)
 114 #define SMI_PROBE_TIMEOUT (100)
 115 #define SMI_MAX_TIMEOUT  (3000)
 116
 117 struct stmsmi_flash_bank {
 118         bool probed;
 119         uint32_t io_base;
 120         uint32_t bank_num;
 121         const struct flash_device *dev;
 122 };
 123
 124 struct stmsmi_target {
 125         char *name;
 126         uint32_t tap_idcode;
 127         uint32_t smi_base;
 128         uint32_t io_base;
 129 };
 130
 131 static const struct stmsmi_target target_devices[] = {
 132         /* name,          tap_idcode, smi_base,   io_base */
 133         { "SPEAr3xx/6xx", 0x07926041, 0xf8000000, 0xfc000000 },
 134         { "STR75x",       0x4f1f0041, 0x80000000, 0x90000000 },
 135         { NULL,           0,          0,          0 }
 136 };
 137
 138 FLASH_BANK_COMMAND_HANDLER(stmsmi_flash_bank_command)
 139 {
 140         struct stmsmi_flash_bank *stmsmi_info;
 141
 142         LOG_DEBUG("%s", __func__);
 143
 144         if (CMD_ARGC < 6)
 145                 return ERROR_COMMAND_SYNTAX_ERROR;
 146
 147         stmsmi_info = malloc(sizeof(struct stmsmi_flash_bank));
 148         if (stmsmi_info == NULL) {
 149                 LOG_ERROR("not enough memory");
 150                 return ERROR_FAIL;
 151         }
 152
 153         bank->driver_priv = stmsmi_info;
 154         stmsmi_info->probed = false;
 155
 156         return ERROR_OK;
 157 }
 158
 159 /* Poll transmit finished flag */
 160 /* timeout in ms */
 161 static int poll_tff(struct target *target, uint32_t io_base, int timeout)
 162 {
 163         int64_t endtime;
 164
 165         if (SMI_READ_REG(SMI_SR) & SMI_TFF)
 166                 return ERROR_OK;
 167
 168         endtime = timeval_ms() + timeout;
 169         do {
 170                 alive_sleep(1);
 171                 if (SMI_READ_REG(SMI_SR) & SMI_TFF)
 172                         return ERROR_OK;
 173         } while (timeval_ms() < endtime);
 174
 175         LOG_ERROR("Timeout while polling TFF");
 176         return ERROR_FLASH_OPERATION_FAILED;
 177 }
 178
 179 /* Read the status register of the external SPI flash chip.
 180  * The operation is triggered by setting SMI_RSR bit.
 181  * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
 182 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
 183 {
 184         struct target *target = bank->target;
 185         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 186         uint32_t io_base = stmsmi_info->io_base;
 187
 188         /* clear transmit finished flag */
 189         SMI_CLEAR_TFF();
 190
 191         /* Read status */
 192         SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_RSR);
 193
 194         /* Poll transmit finished flag */
 195         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 196
 197         /* clear transmit finished flag */
 198         SMI_CLEAR_TFF();
 199
 200         *status = SMI_READ_REG(SMI_SR) & 0x0000ffff;
 201
 202         /* clean-up SMI_CR2 */
 203         SMI_WRITE_REG(SMI_CR2, 0); /* AB: Required ? */
 204
 205         return ERROR_OK;
 206 }
 207
 208 /* check for WIP (write in progress) bit in status register */
 209 /* timeout in ms */
 210 static int wait_till_ready(struct flash_bank *bank, int timeout)
 211 {
 212         uint32_t status;
 213         int retval;
 214         int64_t endtime;
 215
 216         endtime = timeval_ms() + timeout;
 217         do {
 218                 /* read flash status register */
 219                 retval = read_status_reg(bank, &status);
 220                 if (retval != ERROR_OK)
 221                         return retval;
 222
 223                 if ((status & SPIFLASH_BSY_BIT) == 0)
 224                         return ERROR_OK;
 225                 alive_sleep(1);
 226         } while (timeval_ms() < endtime);
 227
 228         LOG_ERROR("timeout");
 229         return ERROR_FAIL;
 230 }
 231
 232 /* Send "write enable" command to SPI flash chip.
 233  * The operation is triggered by setting SMI_WE bit, and SMI sends
 234  * the proper SPI command (0x06) */
 235 static int smi_write_enable(struct flash_bank *bank)
 236 {
 237         struct target *target = bank->target;
 238         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 239         uint32_t io_base = stmsmi_info->io_base;
 240         uint32_t status;
 241         int retval;
 242
 243         /* Enter in HW mode */
 244         SMI_SET_HW_MODE(); /* AB: is this correct ?*/
 245
 246         /* clear transmit finished flag */
 247         SMI_CLEAR_TFF();
 248
 249         /* Send write enable command */
 250         SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_WE);
 251
 252         /* Poll transmit finished flag */
 253         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 254
 255         /* read flash status register */
 256         retval = read_status_reg(bank, &status);
 257         if (retval != ERROR_OK)
 258                 return retval;
 259
 260         /* Check write enabled */
 261         if ((status & SPIFLASH_WE_BIT) == 0) {
 262                 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
 263                 return ERROR_FAIL;
 264         }
 265
 266         return ERROR_OK;
 267 }
 268
 269 static uint32_t erase_command(struct stmsmi_flash_bank *stmsmi_info,
 270         uint32_t offset)
 271 {
 272         uint8_t cmd_bytes[] = {
 273                 stmsmi_info->dev->erase_cmd,
 274                 offset >> 16,
 275                 offset >> 8,
 276                 offset
 277         };
 278
 279         return le_to_h_u32(cmd_bytes);
 280 }
 281
 282 static int smi_erase_sector(struct flash_bank *bank, int sector)
 283 {
 284         struct target *target = bank->target;
 285         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 286         uint32_t io_base = stmsmi_info->io_base;
 287         uint32_t cmd;
 288         int retval;
 289
 290         retval = smi_write_enable(bank);
 291         if (retval != ERROR_OK)
 292                 return retval;
 293
 294         /* Switch to SW mode to send sector erase command */
 295         SMI_SET_SW_MODE();
 296
 297         /* clear transmit finished flag */
 298         SMI_CLEAR_TFF();
 299
 300         /* send SPI command "block erase" */
 301         cmd = erase_command(stmsmi_info, bank->sectors[sector].offset);
 302         SMI_WRITE_REG(SMI_TR, cmd);
 303         SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_SEND | SMI_TX_LEN_4);
 304
 305         /* Poll transmit finished flag */
 306         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 307
 308         /* poll WIP for end of self timed Sector Erase cycle */
 309         retval = wait_till_ready(bank, SMI_MAX_TIMEOUT);
 310         if (retval != ERROR_OK)
 311                 return retval;
 312
 313         return ERROR_OK;
 314 }
 315
 316 static int stmsmi_erase(struct flash_bank *bank, unsigned int first,
 317                 unsigned int last)
 318 {
 319         struct target *target = bank->target;
 320         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 321         uint32_t io_base = stmsmi_info->io_base;
 322         int retval = ERROR_OK;
 323
 324         LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
 325
 326         if (target->state != TARGET_HALTED) {
 327                 LOG_ERROR("Target not halted");
 328                 return ERROR_TARGET_NOT_HALTED;
 329         }
 330
 331         if ((last < first) || (last >= bank->num_sectors)) {
 332                 LOG_ERROR("Flash sector invalid");
 333                 return ERROR_FLASH_SECTOR_INVALID;
 334         }
 335
 336         if (!(stmsmi_info->probed)) {
 337                 LOG_ERROR("Flash bank not probed");
 338                 return ERROR_FLASH_BANK_NOT_PROBED;
 339         }
 340
 341         for (unsigned int sector = first; sector <= last; sector++) {
 342                 if (bank->sectors[sector].is_protected) {
 343                         LOG_ERROR("Flash sector %u protected", sector);
 344                         return ERROR_FAIL;
 345                 }
 346         }
 347
 348         if (stmsmi_info->dev->erase_cmd == 0x00)
 349                 return ERROR_FLASH_OPER_UNSUPPORTED;
 350
 351         for (unsigned int sector = first; sector <= last; sector++) {
 352                 retval = smi_erase_sector(bank, sector);
 353                 if (retval != ERROR_OK)
 354                         break;
 355                 keep_alive();
 356         }
 357
 358         /* Switch to HW mode before return to prompt */
 359         SMI_SET_HW_MODE();
 360         return retval;
 361 }
 362
 363 static int stmsmi_protect(struct flash_bank *bank, int set,
 364                 unsigned int first, unsigned int last)
 365 {
 366         for (unsigned int sector = first; sector <= last; sector++)
 367                 bank->sectors[sector].is_protected = set;
 368         return ERROR_OK;
 369 }
 370
 371 static int smi_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
 372         uint32_t address, uint32_t len)
 373 {
 374         struct target *target = bank->target;
 375         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 376         uint32_t io_base = stmsmi_info->io_base;
 377         int retval;
 378
 379         LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
 380                         __func__, address, len);
 381
 382         retval = smi_write_enable(bank);
 383         if (retval != ERROR_OK)
 384                 return retval;
 385
 386         /* HW mode, write burst mode */
 387         SMI_SET_HWWB_MODE();
 388
 389         retval = target_write_buffer(target, address, len, buffer);
 390         if (retval != ERROR_OK)
 391                 return retval;
 392
 393         return ERROR_OK;
 394 }
 395
 396 static int stmsmi_write(struct flash_bank *bank, const uint8_t *buffer,
 397         uint32_t offset, uint32_t count)
 398 {
 399         struct target *target = bank->target;
 400         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 401         uint32_t io_base = stmsmi_info->io_base;
 402         uint32_t cur_count, page_size, page_offset;
 403         int retval = ERROR_OK;
 404
 405         LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
 406                 __func__, offset, count);
 407
 408         if (target->state != TARGET_HALTED) {
 409                 LOG_ERROR("Target not halted");
 410                 return ERROR_TARGET_NOT_HALTED;
 411         }
 412
 413         if (offset + count > stmsmi_info->dev->size_in_bytes) {
 414                 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
 415                 count = stmsmi_info->dev->size_in_bytes - offset;
 416         }
 417
 418         /* Check sector protection */
 419         for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
 420                 /* Start offset in or before this sector? */
 421                 /* End offset in or behind this sector? */
 422                 if ((offset <
 423                                 (bank->sectors[sector].offset + bank->sectors[sector].size))
 424                         && ((offset + count - 1) >= bank->sectors[sector].offset)
 425                         && bank->sectors[sector].is_protected) {
 426                         LOG_ERROR("Flash sector %u protected", sector);
 427                         return ERROR_FAIL;
 428                 }
 429         }
 430
 431         /* if no valid page_size, use reasonable default */
 432         page_size = stmsmi_info->dev->pagesize ?
 433                 stmsmi_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
 434
 435         /* unaligned buffer head */
 436         if (count > 0 && (offset & 3) != 0) {
 437                 cur_count = 4 - (offset & 3);
 438                 if (cur_count > count)
 439                         cur_count = count;
 440                 retval = smi_write_buffer(bank, buffer, bank->base + offset,
 441                         cur_count);
 442                 if (retval != ERROR_OK)
 443                         goto err;
 444                 offset += cur_count;
 445                 buffer += cur_count;
 446                 count -= cur_count;
 447         }
 448
 449         page_offset = offset % page_size;
 450         /* central part, aligned words */
 451         while (count >= 4) {
 452                 /* clip block at page boundary */
 453                 if (page_offset + count > page_size)
 454                         cur_count = page_size - page_offset;
 455                 else
 456                         cur_count = count & ~3;
 457
 458                 retval = smi_write_buffer(bank, buffer, bank->base + offset,
 459                         cur_count);
 460                 if (retval != ERROR_OK)
 461                         goto err;
 462
 463                 page_offset = 0;
 464                 buffer += cur_count;
 465                 offset += cur_count;
 466                 count -= cur_count;
 467
 468                 keep_alive();
 469         }
 470
 471         /* buffer tail */
 472         if (count > 0)
 473                 retval = smi_write_buffer(bank, buffer, bank->base + offset, count);
 474
 475 err:
 476         /* Switch to HW mode before return to prompt */
 477         SMI_SET_HW_MODE();
 478         return retval;
 479 }
 480
 481 /* Return ID of flash device */
 482 /* On exit, SW mode is kept */
 483 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
 484 {
 485         struct target *target = bank->target;
 486         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 487         uint32_t io_base = stmsmi_info->io_base;
 488         int retval;
 489
 490         if (target->state != TARGET_HALTED) {
 491                 LOG_ERROR("Target not halted");
 492                 return ERROR_TARGET_NOT_HALTED;
 493         }
 494
 495         /* poll WIP */
 496         retval = wait_till_ready(bank, SMI_PROBE_TIMEOUT);
 497         if (retval != ERROR_OK)
 498                 return retval;
 499
 500         /* enter in SW mode */
 501         SMI_SET_SW_MODE();
 502
 503         /* clear transmit finished flag */
 504         SMI_CLEAR_TFF();
 505
 506         /* Send SPI command "read ID" */
 507         SMI_WRITE_REG(SMI_TR, SMI_READ_ID);
 508         SMI_WRITE_REG(SMI_CR2,
 509                 stmsmi_info->bank_num | SMI_SEND | SMI_RX_LEN_3 | SMI_TX_LEN_1);
 510
 511         /* Poll transmit finished flag */
 512         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 513
 514         /* clear transmit finished flag */
 515         SMI_CLEAR_TFF();
 516
 517         /* read ID from Receive Register */
 518         *id = SMI_READ_REG(SMI_RR) & 0x00ffffff;
 519         return ERROR_OK;
 520 }
 521
 522 static int stmsmi_probe(struct flash_bank *bank)
 523 {
 524         struct target *target = bank->target;
 525         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 526         uint32_t io_base, sectorsize;
 527         struct flash_sector *sectors;
 528         uint32_t id = 0; /* silence uninitialized warning */
 529         const struct stmsmi_target *target_device;
 530         int retval;
 531
 532         if (stmsmi_info->probed)
 533                 free(bank->sectors);
 534         stmsmi_info->probed = false;
 535
 536         for (target_device = target_devices ; target_device->name ; ++target_device)
 537                 if (target_device->tap_idcode == target->tap->idcode)
 538                         break;
 539         if (!target_device->name) {
 540                 LOG_ERROR("Device ID 0x%" PRIx32 " is not known as SMI capable",
 541                                 target->tap->idcode);
 542                 return ERROR_FAIL;
 543         }
 544
 545         switch (bank->base - target_device->smi_base) {
 546                 case 0:
 547                         stmsmi_info->bank_num = SMI_SEL_BANK0;
 548                         break;
 549                 case SMI_BANK_SIZE:
 550                         stmsmi_info->bank_num = SMI_SEL_BANK1;
 551                         break;
 552                 case 2*SMI_BANK_SIZE:
 553                         stmsmi_info->bank_num = SMI_SEL_BANK2;
 554                         break;
 555                 case 3*SMI_BANK_SIZE:
 556                         stmsmi_info->bank_num = SMI_SEL_BANK3;
 557                         break;
 558                 default:
 559                         LOG_ERROR("Invalid SMI base address " TARGET_ADDR_FMT, bank->base);
 560                         return ERROR_FAIL;
 561         }
 562         io_base = target_device->io_base;
 563         stmsmi_info->io_base = io_base;
 564
 565         LOG_DEBUG("Valid SMI on device %s at address " TARGET_ADDR_FMT,
 566                 target_device->name, bank->base);
 567
 568         /* read and decode flash ID; returns in SW mode */
 569         retval = read_flash_id(bank, &id);
 570         SMI_SET_HW_MODE();
 571         if (retval != ERROR_OK)
 572                 return retval;
 573
 574         stmsmi_info->dev = NULL;
 575         for (const struct flash_device *p = flash_devices; p->name ; p++)
 576                 if (p->device_id == id) {
 577                         stmsmi_info->dev = p;
 578                         break;
 579                 }
 580
 581         if (!stmsmi_info->dev) {
 582                 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
 583                 return ERROR_FAIL;
 584         }
 585
 586         LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
 587                 stmsmi_info->dev->name, stmsmi_info->dev->device_id);
 588
 589         /* Set correct size value */
 590         bank->size = stmsmi_info->dev->size_in_bytes;
 591         if (bank->size <= (1UL << 16))
 592                 LOG_WARNING("device needs 2-byte addresses - not implemented");
 593         if (bank->size > (1UL << 24))
 594                 LOG_WARNING("device needs paging or 4-byte addresses - not implemented");
 595
 596         /* if no sectors, treat whole bank as single sector */
 597         sectorsize = stmsmi_info->dev->sectorsize ?
 598                 stmsmi_info->dev->sectorsize : stmsmi_info->dev->size_in_bytes;
 599
 600         /* create and fill sectors array */
 601         bank->num_sectors =
 602                 stmsmi_info->dev->size_in_bytes / sectorsize;
 603         sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 604         if (sectors == NULL) {
 605                 LOG_ERROR("not enough memory");
 606                 return ERROR_FAIL;
 607         }
 608
 609         for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
 610                 sectors[sector].offset = sector * sectorsize;
 611                 sectors[sector].size = sectorsize;
 612                 sectors[sector].is_erased = -1;
 613                 sectors[sector].is_protected = 1;
 614         }
 615
 616         bank->sectors = sectors;
 617         stmsmi_info->probed = true;
 618         return ERROR_OK;
 619 }
 620
 621 static int stmsmi_auto_probe(struct flash_bank *bank)
 622 {
 623         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 624         if (stmsmi_info->probed)
 625                 return ERROR_OK;
 626         return stmsmi_probe(bank);
 627 }
 628
 629 static int stmsmi_protect_check(struct flash_bank *bank)
 630 {
 631         /* Nothing to do. Protection is only handled in SW. */
 632         return ERROR_OK;
 633 }
 634
 635 static int get_stmsmi_info(struct flash_bank *bank, char *buf, int buf_size)
 636 {
 637         struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
 638
 639         if (!(stmsmi_info->probed)) {
 640                 snprintf(buf, buf_size,
 641                         "\nSMI flash bank not probed yet\n");
 642                 return ERROR_OK;
 643         }
 644
 645         snprintf(buf, buf_size, "\nSMI flash information:\n"
 646                 "  Device \'%s\' (ID 0x%08" PRIx32 ")\n",
 647                 stmsmi_info->dev->name, stmsmi_info->dev->device_id);
 648
 649         return ERROR_OK;
 650 }
 651
 652 const struct flash_driver stmsmi_flash = {
 653         .name = "stmsmi",
 654         .flash_bank_command = stmsmi_flash_bank_command,
 655         .erase = stmsmi_erase,
 656         .protect = stmsmi_protect,
 657         .write = stmsmi_write,
 658         .read = default_flash_read,
 659         .probe = stmsmi_probe,
 660         .auto_probe = stmsmi_auto_probe,
 661         .erase_check = default_flash_blank_check,
 662         .protect_check = stmsmi_protect_check,
 663         .info = get_stmsmi_info,
 664         .free_driver_priv = default_flash_free_driver_priv,
 665 };