1 /***************************************************************************
2 * Copyright (C) 2016 - 2018 by Andreas Bolsch *
3 * andreas.bolsch@mni.thm.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
19 #ifndef OPENOCD_FLASH_NOR_STMQSPI_H
20 #define OPENOCD_FLASH_NOR_STMQSPI_H
24 /* QSPI register offsets */
25 #define QSPI_CR (0x00) /* Control register */
26 #define QSPI_DCR (0x04) /* Device configuration register */
27 #define QSPI_SR (0x08) /* Status register */
28 #define QSPI_FCR (0x0C) /* Flag clear register */
29 #define QSPI_DLR (0x10) /* Data length register */
30 #define QSPI_CCR (0x14) /* Communication configuration register */
31 #define QSPI_AR (0x18) /* Address register */
32 #define QSPI_ABR (0x1C) /* Alternate bytes register */
33 #define QSPI_DR (0x20) /* Data register */
35 /* common bits in QSPI_CR and OCTOSPI_CR */
36 #define SPI_FSEL_FLASH 7 /* Select flash 2 */
37 #define SPI_DUAL_FLASH 6 /* Dual flash mode */
38 #define SPI_ABORT 1 /* Abort bit */
40 /* common bits in QSPI_DCR and OCTOSPI_DCR1 */
41 #define SPI_FSIZE_POS 16 /* bit position of FSIZE */
42 #define SPI_FSIZE_LEN 5 /* width of FSIZE field */
44 /* common bits in QSPI_SR/FCR and OCTOSPI_SR/FCR */
45 #define SPI_BUSY 5 /* Busy flag */
46 #define SPI_FTF 2 /* FIFO threshold flag */
47 #define SPI_TCF 1 /* Transfer complete flag */
49 /* fields in QSPI_CCR */
50 #define QSPI_DDRM 31 /* position of DDRM bit */
51 #define SPI_DMODE_POS 24 /* bit position of DMODE */
52 #define QSPI_DCYC_POS 18 /* bit position of DCYC */
53 #define QSPI_DCYC_LEN 5 /* width of DCYC field */
54 #define QSPI_DCYC_MASK ((BIT(QSPI_DCYC_LEN) - 1) << QSPI_DCYC_POS)
55 #define SPI_ADSIZE_POS 12 /* bit position of ADSIZE */
57 #define QSPI_WRITE_MODE 0x00000000U /* indirect write mode */
58 #define QSPI_READ_MODE 0x04000000U /* indirect read mode */
59 #define QSPI_MM_MODE 0x0C000000U /* memory mapped mode */
60 #define QSPI_ALTB_MODE 0x0003C000U /* alternate byte mode */
61 #define QSPI_4LINE_MODE 0x03000F00U /* 4 lines for data, addr, instr */
62 #define QSPI_NO_DATA (~0x03000000U) /* no data */
63 #define QSPI_NO_ALTB (~QSPI_ALTB_MODE) /* no alternate */
64 #define QSPI_NO_ADDR (~0x00000C00U) /* no address */
65 #define QSPI_ADDR3 (0x2U << SPI_ADSIZE_POS) /* 3 byte address */
66 #define QSPI_ADDR4 (0x3U << SPI_ADSIZE_POS) /* 4 byte address */
68 /* OCTOSPI register offsets */
69 #define OCTOSPI_CR (0x000) /* Control register */
70 #define OCTOSPI_DCR1 (0x008) /* Device configuration register 1 */
71 #define OCTOSPI_DCR2 (0x00C) /* Device configuration register 2 */
72 #define OCTOSPI_DCR3 (0x010) /* Device configuration register 3 */
73 #define OCTOSPI_SR (0x020) /* Status register */
74 #define OCTOSPI_FCR (0x024) /* Flag clear register */
75 #define OCTOSPI_DLR (0x040) /* Data length register */
76 #define OCTOSPI_AR (0x048) /* Address register */
77 #define OCTOSPI_DR (0x050) /* Data register */
78 #define OCTOSPI_CCR (0x100) /* Communication configuration register */
79 #define OCTOSPI_TCR (0x108) /* Timing configuration register */
80 #define OCTOSPI_IR (0x110) /* Instruction register */
81 #define OCTOSPI_WCCR (0x180) /* Write communication configuration register */
82 #define OCTOSPI_WIR (0x190) /* Write instruction register */
83 #define OCTOSPI_MAGIC (0x3FC) /* Magic ID register, deleted from RM, why? */
85 #define OCTO_MAGIC_ID 0xA3C5DD01 /* Magic ID, deleted from RM, why? */
87 /* additional bits in OCTOSPI_CR */
88 #define OCTOSPI_WRITE_MODE 0x00000000U /* indirect write mode */
89 #define OCTOSPI_READ_MODE 0x10000000U /* indirect read mode */
90 #define OCTOSPI_MM_MODE 0x30000000U /* memory mapped mode */
92 /* additional fields in OCTOSPI_DCR1 */
93 #define OCTOSPI_MTYP_POS (24) /* bit position of MTYP */
94 #define OCTOSPI_MTYP_LEN (3) /* width of MTYP field */
95 #define OCTOSPI_MTYP_MASK ((BIT(OCTOSPI_MTYP_LEN) - 1) << OCTOSPI_MTYP_POS)
97 /* fields in OCTOSPI_CCR */
98 #define OCTOSPI_ALTB_MODE 0x001F0000U /* alternate byte mode */
99 #define OCTOSPI_8LINE_MODE 0x0F003F3FU /* 8 lines DTR for data, addr, instr */
100 #define OCTOSPI_NO_DATA (~0x0F000000U) /* no data */
101 #define OCTOSPI_NO_ALTB (~OCTOSPI_ALTB_MODE) /* no alternate */
102 #define OCTOSPI_NO_ADDR (~0x00000F00U) /* no address */
103 #define OCTOSPI_ADDR3 (0x2U << SPI_ADSIZE_POS) /* 3 byte address */
104 #define OCTOSPI_ADDR4 (0x3U << SPI_ADSIZE_POS) /* 4 byte address */
105 #define OCTOSPI_DQSEN 29 /* DQS enable */
106 #define OCTOSPI_DDTR 27 /* DTR for data */
107 #define OCTOSPI_NO_DDTR (~BIT(OCTOSPI_DDTR)) /* no DTR for data, but maybe still DQS */
108 #define OCTOSPI_ISIZE_MASK (0x30) /* ISIZE field */
110 /* fields in OCTOSPI_TCR */
111 #define OCTOSPI_DCYC_POS 0 /* bit position of DCYC */
112 #define OCTOSPI_DCYC_LEN 5 /* width of DCYC field */
113 #define OCTOSPI_DCYC_MASK ((BIT(OCTOSPI_DCYC_LEN) - 1) << OCTOSPI_DCYC_POS)
115 #define IS_OCTOSPI (stmqspi_info->octo)
116 #define SPI_CR (IS_OCTOSPI ? OCTOSPI_CR : QSPI_CR)
117 #define SPI_DCR (IS_OCTOSPI ? OCTOSPI_DCR1 : QSPI_DCR)
118 #define SPI_SR (IS_OCTOSPI ? OCTOSPI_SR : QSPI_SR)
119 #define SPI_FCR (IS_OCTOSPI ? OCTOSPI_FCR : QSPI_FCR)
120 #define SPI_DLR (IS_OCTOSPI ? OCTOSPI_DLR : QSPI_DLR)
121 #define SPI_AR (IS_OCTOSPI ? OCTOSPI_AR : QSPI_AR)
122 #define SPI_DR (IS_OCTOSPI ? OCTOSPI_DR : QSPI_DR)
123 #define SPI_CCR (IS_OCTOSPI ? OCTOSPI_CCR : QSPI_CCR)
125 #endif /* OPENOCD_FLASH_NOR_STMQSPI_H */