1 /***************************************************************************
2 * Copyright (C) 2016 - 2019 by Andreas Bolsch *
3 * andreas.bolsch@mni.thm.de *
5 * Copyright (C) 2010 by Antonio Borneo *
6 * borneo.antonio@gmail.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
22 /* STM QuadSPI (QSPI) and OctoSPI (OCTOSPI) controller are SPI bus controllers
23 * specifically designed for SPI memories.
24 * Two working modes are available:
25 * - indirect mode: the SPI is controlled by SW. Any custom commands can be sent
27 * - memory mapped mode: the SPI is under QSPI/OCTOSPI control. Memory content
28 * is directly accessible in CPU memory space. CPU can read and execute from
29 * memory (but not write to) */
32 * To have flash mapped in CPU memory space, the QSPI/OCTOSPI controller
33 * has to be in "memory mapped mode". This requires following constraints:
34 * 1) The command "reset init" has to initialize QSPI/OCTOSPI controller and put
35 * it in memory mapped mode;
36 * 2) every command in this file has to return to prompt in memory mapped mode. */
43 #include <helper/bits.h>
44 #include <helper/time_support.h>
45 #include <target/algorithm.h>
46 #include <target/armv7m.h>
47 #include <target/image.h>
53 #undef SPIFLASH_PAGE_PROGRAM
55 /* saved mode settings */
56 #define QSPI_MODE (stmqspi_info->saved_ccr & \
57 (0xF0000000U | QSPI_DCYC_MASK | QSPI_4LINE_MODE | QSPI_ALTB_MODE | QSPI_ADDR4))
59 /* saved read mode settings but indirect read instead of memory mapped
60 * in particular, use the dummy cycle setting from this saved setting */
61 #define QSPI_CCR_READ (QSPI_READ_MODE | (stmqspi_info->saved_ccr & \
62 (0xF0000000U | QSPI_DCYC_MASK | QSPI_4LINE_MODE | QSPI_ALTB_MODE | QSPI_ADDR4 | 0xFF)))
64 /* QSPI_CCR for various other commands, these never use dummy cycles nor alternate bytes */
65 #define QSPI_CCR_READ_STATUS \
66 ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ADDR & QSPI_NO_ALTB) | \
67 (QSPI_READ_MODE | SPIFLASH_READ_STATUS))
69 #define QSPI_CCR_READ_ID \
70 ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ADDR & QSPI_NO_ALTB) | \
71 (QSPI_READ_MODE | SPIFLASH_READ_ID))
73 #define QSPI_CCR_READ_MID \
74 ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ADDR & QSPI_NO_ALTB) | \
75 (QSPI_READ_MODE | SPIFLASH_READ_MID))
77 /* always use 3-byte addresses for read SFDP */
78 #define QSPI_CCR_READ_SFDP \
79 ((QSPI_MODE & ~QSPI_DCYC_MASK & ~QSPI_ADDR4 & QSPI_NO_ALTB) | \
80 (QSPI_READ_MODE | QSPI_ADDR3 | SPIFLASH_READ_SFDP))
82 #define QSPI_CCR_WRITE_ENABLE \
83 ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ADDR & QSPI_NO_ALTB & QSPI_NO_DATA) | \
84 (QSPI_WRITE_MODE | SPIFLASH_WRITE_ENABLE))
86 #define QSPI_CCR_SECTOR_ERASE \
87 ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ALTB & QSPI_NO_DATA) | \
88 (QSPI_WRITE_MODE | stmqspi_info->dev.erase_cmd))
90 #define QSPI_CCR_MASS_ERASE \
91 ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ADDR & QSPI_NO_ALTB & QSPI_NO_DATA) | \
92 (QSPI_WRITE_MODE | stmqspi_info->dev.chip_erase_cmd))
94 #define QSPI_CCR_PAGE_PROG \
95 ((QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ALTB) | \
96 (QSPI_WRITE_MODE | stmqspi_info->dev.pprog_cmd))
98 /* saved mode settings */
99 #define OCTOSPI_MODE (stmqspi_info->saved_cr & 0xCFFFFFFF)
101 #define OPI_MODE ((stmqspi_info->saved_ccr & OCTOSPI_ISIZE_MASK) != 0)
103 #define OCTOSPI_MODE_CCR (stmqspi_info->saved_ccr & \
104 (0xF0000000U | OCTOSPI_8LINE_MODE | OCTOSPI_ALTB_MODE | OCTOSPI_ADDR4))
106 /* use saved ccr for read */
107 #define OCTOSPI_CCR_READ OCTOSPI_MODE_CCR
109 /* OCTOSPI_CCR for various other commands, these never use alternate bytes *
110 * for READ_STATUS and READ_ID, 4-byte address 0 *
111 * 4 dummy cycles must sent in OPI mode when DQS is disabled. However, when *
112 * DQS is enabled, some STM32 devices need at least 6 dummy cycles for *
113 * proper operation, but otherwise the actual number has no effect! *
114 * E.g. RM0432 Rev. 7 is incorrect regarding this: L4R9 works well with 4 *
115 * dummy clocks whereas L4P5 not at all. *
118 ((stmqspi_info->saved_ccr & OCTOSPI_DQSEN) ? 6U : 4U)
120 #define OCTOSPI_CCR_READ_STATUS \
121 ((OCTOSPI_MODE_CCR & OCTOSPI_NO_DDTR & \
122 (OPI_MODE ? ~0U : OCTOSPI_NO_ADDR) & OCTOSPI_NO_ALTB))
124 #define OCTOSPI_CCR_READ_ID \
125 ((OCTOSPI_MODE_CCR & OCTOSPI_NO_DDTR & \
126 (OPI_MODE ? ~0U : OCTOSPI_NO_ADDR) & OCTOSPI_NO_ALTB))
128 #define OCTOSPI_CCR_READ_MID OCTOSPI_CCR_READ_ID
130 /* 4-byte address in octo mode, else 3-byte address for read SFDP */
131 #define OCTOSPI_CCR_READ_SFDP(len) \
132 ((OCTOSPI_MODE_CCR & OCTOSPI_NO_DDTR & ~OCTOSPI_ADDR4 & OCTOSPI_NO_ALTB) | \
133 (((len) < 4) ? OCTOSPI_ADDR3 : OCTOSPI_ADDR4))
135 #define OCTOSPI_CCR_WRITE_ENABLE \
136 ((OCTOSPI_MODE_CCR & OCTOSPI_NO_ADDR & OCTOSPI_NO_ALTB & OCTOSPI_NO_DATA))
138 #define OCTOSPI_CCR_SECTOR_ERASE \
139 ((OCTOSPI_MODE_CCR & OCTOSPI_NO_ALTB & OCTOSPI_NO_DATA))
141 #define OCTOSPI_CCR_MASS_ERASE \
142 ((OCTOSPI_MODE_CCR & OCTOSPI_NO_ADDR & OCTOSPI_NO_ALTB & OCTOSPI_NO_DATA))
144 #define OCTOSPI_CCR_PAGE_PROG \
145 ((OCTOSPI_MODE_CCR & QSPI_NO_ALTB))
147 #define SPI_ADSIZE (((stmqspi_info->saved_ccr >> SPI_ADSIZE_POS) & 0x3) + 1)
149 #define OPI_CMD(cmd) ((OPI_MODE ? ((((uint16_t)(cmd)) << 8) | (~(cmd) & 0xFFU)) : (cmd)))
151 /* convert uint32_t into 4 uint8_t in little endian byte order */
152 static inline uint32_t h_to_le_32(uint32_t val)
156 h_u32_to_le((uint8_t *)&result, val);
161 #define SPI_CMD_TIMEOUT (100)
162 #define SPI_PROBE_TIMEOUT (100)
163 #define SPI_MAX_TIMEOUT (2000)
164 #define SPI_MASS_ERASE_TIMEOUT (400000)
172 struct stmqspi_flash_bank {
176 struct flash_device dev;
178 uint32_t saved_cr; /* in particalar FSEL, DFM bit mask in QUADSPI_CR *AND* OCTOSPI_CR */
179 uint32_t saved_ccr; /* different meaning for QUADSPI and OCTOSPI */
180 uint32_t saved_tcr; /* only for OCTOSPI */
181 uint32_t saved_ir; /* only for OCTOSPI */
182 unsigned int sfdp_dummy1; /* number of dummy bytes for SFDP read for flash1 and octo */
183 unsigned int sfdp_dummy2; /* number of dummy bytes for SFDP read for flash2 */
186 static inline int octospi_cmd(struct flash_bank *bank, uint32_t mode,
187 uint32_t ccr, uint32_t ir)
189 struct target *target = bank->target;
190 const struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
191 const uint32_t io_base = stmqspi_info->io_base;
193 int retval = target_write_u32(target, io_base + OCTOSPI_CR,
194 OCTOSPI_MODE | mode);
196 if (retval != ERROR_OK)
199 retval = target_write_u32(target, io_base + OCTOSPI_TCR,
200 (stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) |
201 ((OPI_MODE && (mode == OCTOSPI_READ_MODE)) ?
202 (OPI_DUMMY << OCTOSPI_DCYC_POS) : 0));
204 if (retval != ERROR_OK)
207 retval = target_write_u32(target, io_base + OCTOSPI_CCR, ccr);
209 if (retval != ERROR_OK)
212 return target_write_u32(target, io_base + OCTOSPI_IR, OPI_CMD(ir));
215 FLASH_BANK_COMMAND_HANDLER(stmqspi_flash_bank_command)
217 struct stmqspi_flash_bank *stmqspi_info;
220 LOG_DEBUG("%s", __func__);
223 return ERROR_COMMAND_SYNTAX_ERROR;
225 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], io_base);
227 stmqspi_info = malloc(sizeof(struct stmqspi_flash_bank));
228 if (stmqspi_info == NULL) {
229 LOG_ERROR("not enough memory");
233 bank->driver_priv = stmqspi_info;
234 stmqspi_info->sfdp_dummy1 = 0;
235 stmqspi_info->sfdp_dummy2 = 0;
236 stmqspi_info->probed = false;
237 stmqspi_info->io_base = io_base;
244 static int poll_busy(struct flash_bank *bank, int timeout)
246 struct target *target = bank->target;
247 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
248 uint32_t io_base = stmqspi_info->io_base;
251 endtime = timeval_ms() + timeout;
254 int retval = target_read_u32(target, io_base + SPI_SR, &spi_sr);
256 if (retval != ERROR_OK)
259 if ((spi_sr & BIT(SPI_BUSY)) == 0) {
260 /* Clear transmit finished flag */
261 return target_write_u32(target, io_base + SPI_FCR, BIT(SPI_TCF));
263 LOG_DEBUG("busy: 0x%08X", spi_sr);
265 } while (timeval_ms() < endtime);
267 LOG_ERROR("Timeout while polling BUSY");
268 return ERROR_FLASH_OPERATION_FAILED;
271 static int stmqspi_abort(struct flash_bank *bank)
273 struct target *target = bank->target;
274 const struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
275 const uint32_t io_base = stmqspi_info->io_base;
278 int retval = target_read_u32(target, io_base + SPI_CR, &cr);
280 if (retval != ERROR_OK)
283 return target_write_u32(target, io_base + SPI_CR, cr | BIT(SPI_ABORT));
286 /* Set to memory-mapped mode, e.g. after an error */
287 static int set_mm_mode(struct flash_bank *bank)
289 struct target *target = bank->target;
290 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
291 uint32_t io_base = stmqspi_info->io_base;
294 /* Reset Address register bits 0 and 1, see various errata sheets */
295 retval = target_write_u32(target, io_base + SPI_AR, 0x0);
296 if (retval != ERROR_OK)
299 /* Abort any previous operation */
300 retval = stmqspi_abort(bank);
301 if (retval != ERROR_OK)
304 /* Wait for busy to be cleared */
305 retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
306 if (retval != ERROR_OK)
309 /* Finally switch to memory mapped mode */
311 retval = target_write_u32(target, io_base + OCTOSPI_CR,
312 OCTOSPI_MODE | OCTOSPI_MM_MODE);
313 if (retval == ERROR_OK)
314 retval = target_write_u32(target, io_base + OCTOSPI_CCR,
315 stmqspi_info->saved_ccr);
316 if (retval == ERROR_OK)
317 retval = target_write_u32(target, io_base + OCTOSPI_TCR,
318 stmqspi_info->saved_tcr);
319 if (retval == ERROR_OK)
320 retval = target_write_u32(target, io_base + OCTOSPI_IR,
321 stmqspi_info->saved_ir);
323 retval = target_write_u32(target, io_base + QSPI_CR,
324 stmqspi_info->saved_cr);
325 if (retval == ERROR_OK)
326 retval = target_write_u32(target, io_base + QSPI_CCR,
327 stmqspi_info->saved_ccr);
332 /* Read the status register of the external SPI flash chip(s). */
333 static int read_status_reg(struct flash_bank *bank, uint16_t *status)
335 struct target *target = bank->target;
336 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
337 uint32_t io_base = stmqspi_info->io_base;
341 /* Abort any previous operation */
342 retval = stmqspi_abort(bank);
343 if (retval != ERROR_OK)
346 /* Wait for busy to be cleared */
347 retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
348 if (retval != ERROR_OK)
351 /* Read always two (for DTR mode) bytes per chip */
353 retval = target_write_u32(target, io_base + SPI_DLR,
354 ((stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 2 * count : count) - 1);
355 if (retval != ERROR_OK)
360 retval = octospi_cmd(bank, OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_STATUS,
361 SPIFLASH_READ_STATUS);
363 /* Dummy address 0, only required for 8-line mode */
364 retval = target_write_u32(target, io_base + SPI_AR, 0);
365 if (retval != ERROR_OK)
369 retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_STATUS);
370 if (retval != ERROR_OK)
375 /* for debugging only */
377 (void)target_read_u32(target, io_base + SPI_SR, &dummy);
379 for ( ; count > 0; --count) {
380 if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
381 != BIT(SPI_FSEL_FLASH)) {
382 /* get status of flash 1 in dual mode or flash 1 only mode */
383 retval = target_read_u8(target, io_base + SPI_DR, &data);
384 if (retval != ERROR_OK)
389 if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) {
390 /* get status of flash 2 in dual mode or flash 2 only mode */
391 retval = target_read_u8(target, io_base + SPI_DR, &data);
392 if (retval != ERROR_OK)
394 *status |= ((uint16_t)data) << 8;
398 LOG_DEBUG("flash status regs: 0x%04" PRIx16, *status);
404 /* check for WIP (write in progress) bit(s) in status register(s) */
406 static int wait_till_ready(struct flash_bank *bank, int timeout)
412 endtime = timeval_ms() + timeout;
414 /* Read flash status register(s) */
415 retval = read_status_reg(bank, &status);
416 if (retval != ERROR_OK)
419 if ((status & ((SPIFLASH_BSY_BIT << 8) | SPIFLASH_BSY_BIT)) == 0)
422 } while (timeval_ms() < endtime);
424 LOG_ERROR("timeout");
425 return ERROR_FLASH_OPERATION_FAILED;
428 /* Send "write enable" command to SPI flash chip(s). */
429 static int qspi_write_enable(struct flash_bank *bank)
431 struct target *target = bank->target;
432 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
433 uint32_t io_base = stmqspi_info->io_base;
437 /* Abort any previous operation */
438 retval = stmqspi_abort(bank);
439 if (retval != ERROR_OK)
442 /* Wait for busy to be cleared */
443 retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
444 if (retval != ERROR_OK)
447 /* Send write enable command */
449 retval = octospi_cmd(bank, OCTOSPI_WRITE_MODE, OCTOSPI_CCR_WRITE_ENABLE,
450 SPIFLASH_WRITE_ENABLE);
452 /* Dummy address 0, only required for 8-line mode */
453 retval = target_write_u32(target, io_base + SPI_AR, 0);
454 if (retval != ERROR_OK)
458 retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_WRITE_ENABLE);
459 if (retval != ERROR_OK)
463 /* Wait for transmit of command completed */
464 poll_busy(bank, SPI_CMD_TIMEOUT);
465 if (retval != ERROR_OK)
468 /* Read flash status register */
469 retval = read_status_reg(bank, &status);
470 if (retval != ERROR_OK)
473 /* Check write enabled for flash 1 */
474 if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
475 != BIT(SPI_FSEL_FLASH))
476 if ((status & (SPIFLASH_WE_BIT | SPIFLASH_BSY_BIT)) != SPIFLASH_WE_BIT) {
477 LOG_ERROR("Cannot write enable flash1. Status=0x%02x",
479 return ERROR_FLASH_OPERATION_FAILED;
482 /* Check write enabled for flash 2 */
484 if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0)
485 if ((status & (SPIFLASH_WE_BIT | SPIFLASH_BSY_BIT)) != SPIFLASH_WE_BIT) {
486 LOG_ERROR("Cannot write enable flash2. Status=0x%02x",
488 return ERROR_FLASH_OPERATION_FAILED;
495 COMMAND_HANDLER(stmqspi_handle_mass_erase_command)
497 struct target *target = NULL;
498 struct flash_bank *bank;
499 struct stmqspi_flash_bank *stmqspi_info;
500 struct duration bench;
506 LOG_DEBUG("%s", __func__);
509 return ERROR_COMMAND_SYNTAX_ERROR;
511 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
512 if (ERROR_OK != retval)
515 stmqspi_info = bank->driver_priv;
516 target = bank->target;
518 if (target->state != TARGET_HALTED) {
519 LOG_ERROR("Target not halted");
520 return ERROR_TARGET_NOT_HALTED;
523 if (!(stmqspi_info->probed)) {
524 LOG_ERROR("Flash bank not probed");
525 return ERROR_FLASH_BANK_NOT_PROBED;
528 if (stmqspi_info->dev.chip_erase_cmd == 0x00) {
529 LOG_ERROR("Mass erase not available for this device");
530 return ERROR_FLASH_OPER_UNSUPPORTED;
533 for (sector = 0; sector < bank->num_sectors; sector++) {
534 if (bank->sectors[sector].is_protected) {
535 LOG_ERROR("Flash sector %u protected", sector);
536 return ERROR_FLASH_PROTECTED;
540 io_base = stmqspi_info->io_base;
541 duration_start(&bench);
543 retval = qspi_write_enable(bank);
544 if (retval != ERROR_OK)
547 /* Send Mass Erase command */
549 retval = octospi_cmd(bank, OCTOSPI_WRITE_MODE, OCTOSPI_CCR_MASS_ERASE,
550 stmqspi_info->dev.chip_erase_cmd);
552 retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_MASS_ERASE);
553 if (retval != ERROR_OK)
556 /* Wait for transmit of command completed */
557 poll_busy(bank, SPI_CMD_TIMEOUT);
558 if (retval != ERROR_OK)
561 /* Read flash status register(s) */
562 retval = read_status_reg(bank, &status);
563 if (retval != ERROR_OK)
566 /* Check for command in progress for flash 1 */
567 if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
568 != BIT(SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
569 ((status & SPIFLASH_WE_BIT) != 0)) {
570 LOG_ERROR("Mass erase command not accepted by flash1. Status=0x%02x",
572 retval = ERROR_FLASH_OPERATION_FAILED;
576 /* Check for command in progress for flash 2 */
578 if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) &&
579 ((status & SPIFLASH_BSY_BIT) == 0) &&
580 ((status & SPIFLASH_WE_BIT) != 0)) {
581 LOG_ERROR("Mass erase command not accepted by flash2. Status=0x%02x",
583 retval = ERROR_FLASH_OPERATION_FAILED;
587 /* Poll WIP for end of self timed Sector Erase cycle */
588 retval = wait_till_ready(bank, SPI_MASS_ERASE_TIMEOUT);
590 duration_measure(&bench);
591 if (retval == ERROR_OK) {
592 /* set all sectors as erased */
593 for (sector = 0; sector < bank->num_sectors; sector++)
594 bank->sectors[sector].is_erased = 1;
596 command_print(CMD, "stmqspi mass erase completed in %fs (%0.3f KiB/s)",
597 duration_elapsed(&bench),
598 duration_kbps(&bench, bank->size));
600 command_print(CMD, "stmqspi mass erase not completed even after %fs",
601 duration_elapsed(&bench));
605 /* Switch to memory mapped mode before return to prompt */
611 static int log2u(uint32_t word)
615 for (result = 0; (unsigned int) result < sizeof(uint32_t) * CHAR_BIT; result++)
616 if (word == BIT(result))
622 COMMAND_HANDLER(stmqspi_handle_set)
624 struct flash_bank *bank = NULL;
625 struct target *target = NULL;
626 struct stmqspi_flash_bank *stmqspi_info = NULL;
627 struct flash_sector *sectors = NULL;
629 unsigned int index = 0, dual, fsize;
632 LOG_DEBUG("%s", __func__);
634 dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
636 /* chip_erase_cmd, sectorsize and erase_cmd are optional */
637 if ((CMD_ARGC < 7) || (CMD_ARGC > 10))
638 return ERROR_COMMAND_SYNTAX_ERROR;
640 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, index++, &bank);
641 if (ERROR_OK != retval)
644 target = bank->target;
645 stmqspi_info = bank->driver_priv;
647 /* invalidate all old info */
648 if (stmqspi_info->probed)
651 bank->num_sectors = 0;
652 bank->sectors = NULL;
653 stmqspi_info->sfdp_dummy1 = 0;
654 stmqspi_info->sfdp_dummy2 = 0;
655 stmqspi_info->probed = false;
656 memset(&stmqspi_info->dev, 0, sizeof(stmqspi_info->dev));
657 stmqspi_info->dev.name = "unknown";
659 strncpy(stmqspi_info->devname, CMD_ARGV[index++], sizeof(stmqspi_info->devname) - 1);
660 stmqspi_info->devname[sizeof(stmqspi_info->devname) - 1] = '\0';
662 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index++], stmqspi_info->dev.size_in_bytes);
663 if (log2u(stmqspi_info->dev.size_in_bytes) < 8) {
664 command_print(CMD, "stmqspi: device size must be 2^n with n >= 8");
665 return ERROR_COMMAND_SYNTAX_ERROR;
668 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index++], stmqspi_info->dev.pagesize);
669 if (stmqspi_info->dev.pagesize > stmqspi_info->dev.size_in_bytes ||
670 (log2u(stmqspi_info->dev.pagesize) < 0)) {
671 command_print(CMD, "stmqspi: page size must be 2^n and <= device size");
672 return ERROR_COMMAND_SYNTAX_ERROR;
675 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.read_cmd);
676 if ((stmqspi_info->dev.read_cmd != 0x03) &&
677 (stmqspi_info->dev.read_cmd != 0x13)) {
678 command_print(CMD, "stmqspi: only 0x03/0x13 READ cmd allowed");
679 return ERROR_COMMAND_SYNTAX_ERROR;
682 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.qread_cmd);
683 if ((stmqspi_info->dev.qread_cmd != 0x00) &&
684 (stmqspi_info->dev.qread_cmd != 0x0B) &&
685 (stmqspi_info->dev.qread_cmd != 0x0C) &&
686 (stmqspi_info->dev.qread_cmd != 0x3B) &&
687 (stmqspi_info->dev.qread_cmd != 0x3C) &&
688 (stmqspi_info->dev.qread_cmd != 0x6B) &&
689 (stmqspi_info->dev.qread_cmd != 0x6C) &&
690 (stmqspi_info->dev.qread_cmd != 0xBB) &&
691 (stmqspi_info->dev.qread_cmd != 0xBC) &&
692 (stmqspi_info->dev.qread_cmd != 0xEB) &&
693 (stmqspi_info->dev.qread_cmd != 0xEC) &&
694 (stmqspi_info->dev.qread_cmd != 0xEE)) {
695 command_print(CMD, "stmqspi: only 0x0B/0x0C/0x3B/0x3C/"
696 "0x6B/0x6C/0xBB/0xBC/0xEB/0xEC/0xEE QREAD allowed");
697 return ERROR_COMMAND_SYNTAX_ERROR;
700 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.pprog_cmd);
701 if ((stmqspi_info->dev.pprog_cmd != 0x02) &&
702 (stmqspi_info->dev.pprog_cmd != 0x12) &&
703 (stmqspi_info->dev.pprog_cmd != 0x32)) {
704 command_print(CMD, "stmqspi: only 0x02/0x12/0x32 PPRG cmd allowed");
705 return ERROR_COMMAND_SYNTAX_ERROR;
708 if (index < CMD_ARGC)
709 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.chip_erase_cmd);
711 stmqspi_info->dev.chip_erase_cmd = 0x00;
713 if (index < CMD_ARGC) {
714 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index++], stmqspi_info->dev.sectorsize);
715 if ((stmqspi_info->dev.sectorsize > stmqspi_info->dev.size_in_bytes) ||
716 (stmqspi_info->dev.sectorsize < stmqspi_info->dev.pagesize) ||
717 (log2u(stmqspi_info->dev.sectorsize) < 0)) {
718 command_print(CMD, "stmqspi: sector size must be 2^n and <= device size");
719 return ERROR_COMMAND_SYNTAX_ERROR;
722 if (index < CMD_ARGC)
723 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], stmqspi_info->dev.erase_cmd);
725 return ERROR_COMMAND_SYNTAX_ERROR;
727 /* no sector size / sector erase cmd given, treat whole bank as a single sector */
728 stmqspi_info->dev.erase_cmd = 0x00;
729 stmqspi_info->dev.sectorsize = stmqspi_info->dev.size_in_bytes;
732 /* set correct size value */
733 bank->size = stmqspi_info->dev.size_in_bytes << dual;
735 io_base = stmqspi_info->io_base;
738 retval = target_read_u32(target, io_base + SPI_DCR, &dcr);
740 if (retval != ERROR_OK)
743 fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
745 LOG_DEBUG("FSIZE = 0x%04x", fsize);
746 if (bank->size == BIT(fsize + 1))
747 LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
748 else if (bank->size == BIT(fsize + 0))
749 LOG_DEBUG("FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?");
751 LOG_ERROR("FSIZE in DCR(1) doesn't match actual capacity.");
753 /* create and fill sectors array */
755 stmqspi_info->dev.size_in_bytes / stmqspi_info->dev.sectorsize;
756 sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
757 if (sectors == NULL) {
758 LOG_ERROR("not enough memory");
762 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
763 sectors[sector].offset = sector * (stmqspi_info->dev.sectorsize << dual);
764 sectors[sector].size = (stmqspi_info->dev.sectorsize << dual);
765 sectors[sector].is_erased = -1;
766 sectors[sector].is_protected = 0;
769 bank->sectors = sectors;
770 stmqspi_info->dev.name = stmqspi_info->devname;
771 if (stmqspi_info->dev.size_in_bytes / 4096)
772 LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 "kbytes,"
773 " bank size = %" PRIu32 "kbytes", stmqspi_info->dev.name,
774 stmqspi_info->dev.size_in_bytes / 1024,
775 (stmqspi_info->dev.size_in_bytes / 1024) << dual);
777 LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 "bytes,"
778 " bank size = %" PRIu32 "bytes", stmqspi_info->dev.name,
779 stmqspi_info->dev.size_in_bytes,
780 stmqspi_info->dev.size_in_bytes << dual);
782 stmqspi_info->probed = true;
787 COMMAND_HANDLER(stmqspi_handle_cmd)
789 struct target *target = NULL;
790 struct flash_bank *bank;
791 struct stmqspi_flash_bank *stmqspi_info = NULL;
792 uint32_t io_base, addr;
793 uint8_t num_write, num_read, cmd_byte, data;
796 char temp[4], output[(2 + max + 256) * 3 + 8];
799 LOG_DEBUG("%s", __func__);
802 return ERROR_COMMAND_SYNTAX_ERROR;
804 num_write = CMD_ARGC - 2;
805 if (num_write > max) {
806 LOG_ERROR("at most %d bytes may be sent", max);
807 return ERROR_COMMAND_SYNTAX_ERROR;
810 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
811 if (ERROR_OK != retval)
814 target = bank->target;
815 stmqspi_info = bank->driver_priv;
816 io_base = stmqspi_info->io_base;
818 if (target->state != TARGET_HALTED) {
819 LOG_ERROR("Target not halted");
820 return ERROR_TARGET_NOT_HALTED;
823 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], num_read);
824 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[2], cmd_byte);
827 /* nothing to read, then one command byte and for dual flash
828 * an *even* number of data bytes to follow */
829 if (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) {
830 if ((num_write & 1) == 0) {
831 LOG_ERROR("number of data bytes to write must be even in dual mode");
832 return ERROR_COMMAND_SYNTAX_ERROR;
836 /* read mode, one command byte and up to four following address bytes */
837 if (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) {
838 if ((num_read & 1) != 0) {
839 LOG_ERROR("number of bytes to read must be even in dual mode");
840 return ERROR_COMMAND_SYNTAX_ERROR;
843 if ((num_write < 1) || (num_write > 5)) {
844 LOG_ERROR("one cmd and up to four addr bytes must be send when reading");
845 return ERROR_COMMAND_SYNTAX_ERROR;
849 /* Abort any previous operation */
850 retval = stmqspi_abort(bank);
851 if (retval != ERROR_OK)
854 /* Wait for busy to be cleared */
855 retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
856 if (retval != ERROR_OK)
859 /* send command byte */
860 snprintf(output, sizeof(output), "spi: %02x ", cmd_byte);
862 /* write, send cmd byte */
863 retval = target_write_u32(target, io_base + SPI_DLR, ((uint32_t)num_write) - 2);
864 if (retval != ERROR_OK)
868 retval = octospi_cmd(bank, OCTOSPI_WRITE_MODE,
869 (OCTOSPI_MODE_CCR & OCTOSPI_NO_ALTB & OCTOSPI_NO_ADDR &
870 ((num_write == 1) ? OCTOSPI_NO_DATA : ~0U)), cmd_byte);
872 retval = target_write_u32(target, io_base + QSPI_CCR,
873 (QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ALTB & QSPI_NO_ADDR &
874 ((num_write == 1) ? QSPI_NO_DATA : ~0U)) |
875 (QSPI_WRITE_MODE | cmd_byte));
876 if (retval != ERROR_OK)
879 /* send additional data bytes */
880 for (count = 3; count < CMD_ARGC; count++) {
881 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[count], data);
882 snprintf(temp, sizeof(temp), "%02" PRIx8 " ", data);
883 retval = target_write_u8(target, io_base + SPI_DR, data);
884 if (retval != ERROR_OK)
886 strncat(output, temp, sizeof(output) - strlen(output) - 1);
888 strncat(output, "-> ", sizeof(output) - strlen(output) - 1);
890 /* read, pack additional bytes into address */
892 for (count = 3; count < CMD_ARGC; count++) {
893 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[count], data);
894 snprintf(temp, sizeof(temp), "%02" PRIx8 " ", data);
895 addr = (addr << 8) | data;
896 strncat(output, temp, sizeof(output) - strlen(output) - 1);
898 strncat(output, "-> ", sizeof(output) - strlen(output) - 1);
900 /* send cmd byte, if ADMODE indicates no address, this already triggers command */
901 retval = target_write_u32(target, io_base + SPI_DLR, ((uint32_t)num_read) - 1);
902 if (retval != ERROR_OK)
905 retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
906 (OCTOSPI_MODE_CCR & OCTOSPI_NO_DDTR & OCTOSPI_NO_ALTB & ~OCTOSPI_ADDR4 &
907 ((num_write == 1) ? OCTOSPI_NO_ADDR : ~0U)) |
908 (((num_write - 2) & 0x3U) << SPI_ADSIZE_POS), cmd_byte);
910 retval = target_write_u32(target, io_base + QSPI_CCR,
911 (QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ALTB & ~QSPI_ADDR4 &
912 ((num_write == 1) ? QSPI_NO_ADDR : ~0U)) |
913 ((QSPI_READ_MODE | (((num_write - 2) & 0x3U) << SPI_ADSIZE_POS) | cmd_byte)));
914 if (retval != ERROR_OK)
918 /* if ADMODE indicates address required, only the write to AR triggers command */
919 retval = target_write_u32(target, io_base + SPI_AR, addr);
920 if (retval != ERROR_OK)
924 /* read response bytes */
925 for ( ; num_read > 0; num_read--) {
926 retval = target_read_u8(target, io_base + SPI_DR, &data);
927 if (retval != ERROR_OK)
929 snprintf(temp, sizeof(temp), "%02" PRIx8 " ", data);
930 strncat(output, temp, sizeof(output) - strlen(output) - 1);
933 command_print(CMD, "%s", output);
936 /* Switch to memory mapped mode before return to prompt */
942 static int qspi_erase_sector(struct flash_bank *bank, unsigned int sector)
944 struct target *target = bank->target;
945 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
946 uint32_t io_base = stmqspi_info->io_base;
950 retval = qspi_write_enable(bank);
951 if (retval != ERROR_OK)
954 /* Send Sector Erase command */
956 retval = octospi_cmd(bank, OCTOSPI_WRITE_MODE, OCTOSPI_CCR_SECTOR_ERASE,
957 stmqspi_info->dev.erase_cmd);
959 retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_SECTOR_ERASE);
960 if (retval != ERROR_OK)
963 /* Address is sector offset, this write initiates command transmission */
964 retval = target_write_u32(target, io_base + SPI_AR, bank->sectors[sector].offset);
965 if (retval != ERROR_OK)
968 /* Wait for transmit of command completed */
969 poll_busy(bank, SPI_CMD_TIMEOUT);
970 if (retval != ERROR_OK)
973 /* Read flash status register(s) */
974 retval = read_status_reg(bank, &status);
975 if (retval != ERROR_OK)
978 LOG_DEBUG("erase status regs: 0x%04" PRIx16, status);
980 /* Check for command in progress for flash 1 */
981 /* If BSY and WE are already cleared the erase did probably complete already */
982 if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
983 != BIT(SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
984 ((status & SPIFLASH_WE_BIT) != 0)) {
985 LOG_ERROR("Sector erase command not accepted by flash1. Status=0x%02x",
987 retval = ERROR_FLASH_OPERATION_FAILED;
991 /* Check for command in progress for flash 2 */
992 /* If BSY and WE are already cleared the erase did probably complete already */
994 if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) &&
995 ((status & SPIFLASH_BSY_BIT) == 0) &&
996 ((status & SPIFLASH_WE_BIT) != 0)) {
997 LOG_ERROR("Sector erase command not accepted by flash2. Status=0x%02x",
999 retval = ERROR_FLASH_OPERATION_FAILED;
1003 /* Erase takes a long time, so some sort of progress message is a good idea */
1004 LOG_DEBUG("erasing sector %4u", sector);
1006 /* Poll WIP for end of self timed Sector Erase cycle */
1007 retval = wait_till_ready(bank, SPI_MAX_TIMEOUT);
1013 static int stmqspi_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
1015 struct target *target = bank->target;
1016 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1017 unsigned int sector;
1018 int retval = ERROR_OK;
1020 LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
1022 if (target->state != TARGET_HALTED) {
1023 LOG_ERROR("Target not halted");
1024 return ERROR_TARGET_NOT_HALTED;
1027 if (!(stmqspi_info->probed)) {
1028 LOG_ERROR("Flash bank not probed");
1029 return ERROR_FLASH_BANK_NOT_PROBED;
1032 if (stmqspi_info->dev.erase_cmd == 0x00) {
1033 LOG_ERROR("Sector erase not available for this device");
1034 return ERROR_FLASH_OPER_UNSUPPORTED;
1037 if ((last < first) || (last >= bank->num_sectors)) {
1038 LOG_ERROR("Flash sector invalid");
1039 return ERROR_FLASH_SECTOR_INVALID;
1042 for (sector = first; sector <= last; sector++) {
1043 if (bank->sectors[sector].is_protected) {
1044 LOG_ERROR("Flash sector %u protected", sector);
1045 return ERROR_FLASH_PROTECTED;
1049 for (sector = first; sector <= last; sector++) {
1050 retval = qspi_erase_sector(bank, sector);
1051 if (retval != ERROR_OK)
1057 if (retval != ERROR_OK)
1058 LOG_ERROR("Flash sector_erase failed on sector %u", sector);
1060 /* Switch to memory mapped mode before return to prompt */
1066 static int stmqspi_protect(struct flash_bank *bank, int set,
1067 unsigned int first, unsigned int last)
1069 unsigned int sector;
1071 for (sector = first; sector <= last; sector++)
1072 bank->sectors[sector].is_protected = set;
1075 LOG_WARNING("setting soft protection only, not related to flash's hardware write protection");
1080 /* Check whether flash is blank */
1081 static int stmqspi_blank_check(struct flash_bank *bank)
1083 struct target *target = bank->target;
1084 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1085 struct duration bench;
1086 struct reg_param reg_params[2];
1087 struct armv7m_algorithm armv7m_info;
1088 struct working_area *algorithm;
1089 const uint8_t *code;
1090 struct sector_info erase_check_info;
1091 uint32_t codesize, maxsize, result, exit_point;
1092 unsigned int count, index, num_sectors, sector;
1094 const uint32_t erased = 0x00FF;
1096 if (target->state != TARGET_HALTED) {
1097 LOG_ERROR("Target not halted");
1098 return ERROR_TARGET_NOT_HALTED;
1101 if (!(stmqspi_info->probed)) {
1102 LOG_ERROR("Flash bank not probed");
1103 return ERROR_FLASH_BANK_NOT_PROBED;
1106 /* Abort any previous operation */
1107 retval = stmqspi_abort(bank);
1108 if (retval != ERROR_OK)
1111 /* Wait for busy to be cleared */
1112 retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1113 if (retval != ERROR_OK)
1116 /* see contrib/loaders/flash/stmqspi/stmqspi_erase_check.S for src */
1117 static const uint8_t stmqspi_erase_check_code[] = {
1118 #include "../../../contrib/loaders/flash/stmqspi/stmqspi_erase_check.inc"
1121 /* see contrib/loaders/flash/stmqspi/stmoctospi_erase_check.S for src */
1122 static const uint8_t stmoctospi_erase_check_code[] = {
1123 #include "../../../contrib/loaders/flash/stmqspi/stmoctospi_erase_check.inc"
1127 code = stmoctospi_erase_check_code;
1128 codesize = sizeof(stmoctospi_erase_check_code);
1130 code = stmqspi_erase_check_code;
1131 codesize = sizeof(stmqspi_erase_check_code);
1134 /* This will overlay the last 4 words of stmqspi/stmoctospi_erase_check_code in target */
1135 /* for read use the saved settings (memory mapped mode) but indirect read mode */
1136 uint32_t ccr_buffer[][4] = {
1137 /* cr (not used for QSPI) *
1138 * ccr (for both QSPI and OCTOSPI) *
1139 * tcr (not used for QSPI) *
1140 * ir (not used for QSPI) */
1142 h_to_le_32(OCTOSPI_MODE | OCTOSPI_READ_MODE),
1143 h_to_le_32(IS_OCTOSPI ? OCTOSPI_CCR_READ : QSPI_CCR_READ),
1144 h_to_le_32(stmqspi_info->saved_tcr),
1145 h_to_le_32(stmqspi_info->saved_ir),
1149 maxsize = target_get_working_area_avail(target);
1150 if (maxsize < codesize + sizeof(erase_check_info)) {
1151 LOG_ERROR("Not enough working area, can't do QSPI blank check");
1152 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1155 num_sectors = (maxsize - codesize) / sizeof(erase_check_info);
1156 num_sectors = (bank->num_sectors < num_sectors) ? bank->num_sectors : num_sectors;
1158 if (target_alloc_working_area_try(target,
1159 codesize + num_sectors * sizeof(erase_check_info), &algorithm) != ERROR_OK) {
1160 LOG_ERROR("allocating working area failed");
1161 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1164 /* prepare blank check code, excluding ccr_buffer */
1165 retval = target_write_buffer(target, algorithm->address,
1166 codesize - sizeof(ccr_buffer), code);
1167 if (retval != ERROR_OK)
1170 /* prepare QSPI/OCTOSPI_CCR register values */
1171 retval = target_write_buffer(target, algorithm->address
1172 + codesize - sizeof(ccr_buffer),
1173 sizeof(ccr_buffer), (uint8_t *)ccr_buffer);
1174 if (retval != ERROR_OK)
1177 duration_start(&bench);
1179 /* after breakpoint instruction (halfword), one nop (halfword) and
1180 * port_buffer till end of code */
1181 exit_point = algorithm->address + codesize - sizeof(uint32_t) - sizeof(ccr_buffer);
1183 init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /* sector count */
1184 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* QSPI/OCTOSPI io_base */
1187 while (sector < bank->num_sectors) {
1188 /* at most num_sectors sectors to handle in one run */
1189 count = bank->num_sectors - sector;
1190 if (count > num_sectors)
1191 count = num_sectors;
1193 for (index = 0; index < count; index++) {
1194 erase_check_info.offset = h_to_le_32(bank->sectors[sector + index].offset);
1195 erase_check_info.size = h_to_le_32(bank->sectors[sector + index].size);
1196 erase_check_info.result = h_to_le_32(erased);
1198 retval = target_write_buffer(target, algorithm->address
1199 + codesize + index * sizeof(erase_check_info),
1200 sizeof(erase_check_info), (uint8_t *)&erase_check_info);
1201 if (retval != ERROR_OK)
1205 buf_set_u32(reg_params[0].value, 0, 32, count);
1206 buf_set_u32(reg_params[1].value, 0, 32, stmqspi_info->io_base);
1208 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1209 armv7m_info.core_mode = ARM_MODE_THREAD;
1211 LOG_DEBUG("checking sectors %u to %u", sector, sector + count - 1);
1212 /* check a block of sectors */
1213 retval = target_run_algorithm(target,
1215 ARRAY_SIZE(reg_params), reg_params,
1216 algorithm->address, exit_point,
1217 count * ((bank->sectors[sector].size >> 6) + 1) + 1000,
1219 if (retval != ERROR_OK)
1222 for (index = 0; index < count; index++) {
1223 retval = target_read_buffer(target, algorithm->address
1224 + codesize + index * sizeof(erase_check_info),
1225 sizeof(erase_check_info), (uint8_t *)&erase_check_info);
1226 if (retval != ERROR_OK)
1229 if ((erase_check_info.offset != h_to_le_32(bank->sectors[sector + index].offset)) ||
1230 (erase_check_info.size != 0)) {
1231 LOG_ERROR("corrupted blank check info");
1235 /* we need le_32_to_h, but that's the same as h_to_le_32 */
1236 result = h_to_le_32(erase_check_info.result);
1237 bank->sectors[sector + index].is_erased = ((result & 0xFF) == 0xFF);
1238 LOG_DEBUG("Flash sector %u checked: 0x%04x", sector + index, result & 0xFFFFU);
1244 destroy_reg_param(®_params[0]);
1245 destroy_reg_param(®_params[1]);
1247 duration_measure(&bench);
1248 LOG_INFO("stmqspi blank checked in %fs (%0.3f KiB/s)", duration_elapsed(&bench),
1249 duration_kbps(&bench, bank->size));
1252 target_free_working_area(target, algorithm);
1254 /* Switch to memory mapped mode before return to prompt */
1260 /* Verify checksum */
1261 static int qspi_verify(struct flash_bank *bank, uint8_t *buffer,
1262 uint32_t offset, uint32_t count)
1264 struct target *target = bank->target;
1265 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1266 struct reg_param reg_params[4];
1267 struct armv7m_algorithm armv7m_info;
1268 struct working_area *algorithm;
1269 const uint8_t *code;
1270 uint32_t pagesize, codesize, crc32, result, exit_point;
1273 /* see contrib/loaders/flash/stmqspi/stmqspi_crc32.S for src */
1274 static const uint8_t stmqspi_crc32_code[] = {
1275 #include "../../../contrib/loaders/flash/stmqspi/stmqspi_crc32.inc"
1278 /* see contrib/loaders/flash/stmqspi/stmoctospi_crc32.S for src */
1279 static const uint8_t stmoctospi_crc32_code[] = {
1280 #include "../../../contrib/loaders/flash/stmqspi/stmoctospi_crc32.inc"
1284 code = stmoctospi_crc32_code;
1285 codesize = sizeof(stmoctospi_crc32_code);
1287 code = stmqspi_crc32_code;
1288 codesize = sizeof(stmqspi_crc32_code);
1291 /* block size doesn't matter that much here */
1292 pagesize = stmqspi_info->dev.sectorsize;
1294 pagesize = stmqspi_info->dev.pagesize;
1296 pagesize = SPIFLASH_DEF_PAGESIZE;
1298 /* adjust size according to dual flash mode */
1299 pagesize = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? pagesize << 1 : pagesize;
1301 /* This will overlay the last 4 words of stmqspi/stmoctospi_crc32_code in target */
1302 /* for read use the saved settings (memory mapped mode) but indirect read mode */
1303 uint32_t ccr_buffer[][4] = {
1304 /* cr (not used for QSPI) *
1305 * ccr (for both QSPI and OCTOSPI) *
1306 * tcr (not used for QSPI) *
1307 * ir (not used for QSPI) */
1309 h_to_le_32(OCTOSPI_MODE | OCTOSPI_READ_MODE),
1310 h_to_le_32(IS_OCTOSPI ? OCTOSPI_CCR_READ : QSPI_CCR_READ),
1311 h_to_le_32(stmqspi_info->saved_tcr),
1312 h_to_le_32(stmqspi_info->saved_ir),
1316 if (target_alloc_working_area_try(target, codesize, &algorithm) != ERROR_OK) {
1317 LOG_ERROR("Not enough working area, can't do QSPI verify");
1318 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1321 /* prepare verify code, excluding ccr_buffer */
1322 retval = target_write_buffer(target, algorithm->address,
1323 codesize - sizeof(ccr_buffer), code);
1324 if (retval != ERROR_OK)
1327 /* prepare QSPI/OCTOSPI_CCR register values */
1328 retval = target_write_buffer(target, algorithm->address
1329 + codesize - sizeof(ccr_buffer),
1330 sizeof(ccr_buffer), (uint8_t *)ccr_buffer);
1331 if (retval != ERROR_OK)
1334 /* after breakpoint instruction (halfword), one nop (halfword) and
1335 * port_buffer till end of code */
1336 exit_point = algorithm->address + codesize - sizeof(uint32_t) - sizeof(ccr_buffer);
1338 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* count (in), crc32 (out) */
1339 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* pagesize */
1340 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* offset into flash address */
1341 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* QSPI/OCTOSPI io_base */
1343 buf_set_u32(reg_params[0].value, 0, 32, count);
1344 buf_set_u32(reg_params[1].value, 0, 32, pagesize);
1345 buf_set_u32(reg_params[2].value, 0, 32, offset);
1346 buf_set_u32(reg_params[3].value, 0, 32, stmqspi_info->io_base);
1349 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1350 armv7m_info.core_mode = ARM_MODE_THREAD;
1352 retval = target_run_algorithm(target,
1354 ARRAY_SIZE(reg_params), reg_params,
1355 algorithm->address, exit_point,
1356 (count >> 5) + 1000,
1360 image_calculate_checksum(buffer, count, &crc32);
1362 if (retval == ERROR_OK) {
1363 result = buf_get_u32(reg_params[0].value, 0, 32);
1364 LOG_DEBUG("addr " TARGET_ADDR_FMT ", len 0x%08" PRIx32 ", crc 0x%08" PRIx32 " 0x%08" PRIx32,
1365 offset + bank->base, count, ~crc32, result);
1366 if (~crc32 != result)
1367 retval = ERROR_FAIL;
1370 destroy_reg_param(®_params[0]);
1371 destroy_reg_param(®_params[1]);
1372 destroy_reg_param(®_params[2]);
1373 destroy_reg_param(®_params[3]);
1376 target_free_working_area(target, algorithm);
1378 /* Switch to memory mapped mode before return to prompt */
1384 static int qspi_read_write_block(struct flash_bank *bank, uint8_t *buffer,
1385 uint32_t offset, uint32_t count, bool write)
1387 struct target *target = bank->target;
1388 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1389 uint32_t io_base = stmqspi_info->io_base;
1390 struct reg_param reg_params[6];
1391 struct armv7m_algorithm armv7m_info;
1392 struct working_area *algorithm;
1393 uint32_t pagesize, fifo_start, fifosize, remaining;
1394 uint32_t maxsize, codesize, exit_point;
1395 const uint8_t *code = NULL;
1399 LOG_DEBUG("%s: offset=0x%08" PRIx32 " len=0x%08" PRIx32,
1400 __func__, offset, count);
1402 dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
1404 /* see contrib/loaders/flash/stmqspi/stmqspi_read.S for src */
1405 static const uint8_t stmqspi_read_code[] = {
1406 #include "../../../contrib/loaders/flash/stmqspi/stmqspi_read.inc"
1409 /* see contrib/loaders/flash/stmqspi/stmoctospi_read.S for src */
1410 static const uint8_t stmoctospi_read_code[] = {
1411 #include "../../../contrib/loaders/flash/stmqspi/stmoctospi_read.inc"
1414 /* see contrib/loaders/flash/stmqspi/stmqspi_write.S for src */
1415 static const uint8_t stmqspi_write_code[] = {
1416 #include "../../../contrib/loaders/flash/stmqspi/stmqspi_write.inc"
1419 /* see contrib/loaders/flash/stmqspi/stmoctospi_write.S for src */
1420 static const uint8_t stmoctospi_write_code[] = {
1421 #include "../../../contrib/loaders/flash/stmqspi/stmoctospi_write.inc"
1424 /* This will overlay the last 12 words of stmqspi/stmoctospi_read/write_code in target */
1425 /* for read use the saved settings (memory mapped mode) but indirect read mode */
1426 uint32_t ccr_buffer[][4] = {
1427 /* cr (not used for QSPI) *
1428 * ccr (for both QSPI and OCTOSPI) *
1429 * tcr (not used for QSPI) *
1430 * ir (not used for QSPI) */
1432 h_to_le_32(OCTOSPI_MODE | OCTOSPI_READ_MODE),
1433 h_to_le_32(IS_OCTOSPI ? OCTOSPI_CCR_READ_STATUS : QSPI_CCR_READ_STATUS),
1434 h_to_le_32((stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) |
1435 (OPI_MODE ? (OPI_DUMMY << OCTOSPI_DCYC_POS) : 0)),
1436 h_to_le_32(OPI_CMD(SPIFLASH_READ_STATUS)),
1439 h_to_le_32(OCTOSPI_MODE | OCTOSPI_WRITE_MODE),
1440 h_to_le_32(IS_OCTOSPI ? OCTOSPI_CCR_WRITE_ENABLE : QSPI_CCR_WRITE_ENABLE),
1441 h_to_le_32(stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK),
1442 h_to_le_32(OPI_CMD(SPIFLASH_WRITE_ENABLE)),
1445 h_to_le_32(OCTOSPI_MODE | (write ? OCTOSPI_WRITE_MODE : OCTOSPI_READ_MODE)),
1446 h_to_le_32(write ? (IS_OCTOSPI ? OCTOSPI_CCR_PAGE_PROG : QSPI_CCR_PAGE_PROG) :
1447 (IS_OCTOSPI ? OCTOSPI_CCR_READ : QSPI_CCR_READ)),
1448 h_to_le_32(write ? (stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) :
1449 stmqspi_info->saved_tcr),
1450 h_to_le_32(write ? OPI_CMD(stmqspi_info->dev.pprog_cmd) : stmqspi_info->saved_ir),
1454 /* force reasonable defaults */
1455 fifosize = stmqspi_info->dev.sectorsize ?
1456 stmqspi_info->dev.sectorsize : stmqspi_info->dev.size_in_bytes;
1460 code = stmoctospi_write_code;
1461 codesize = sizeof(stmoctospi_write_code);
1463 code = stmqspi_write_code;
1464 codesize = sizeof(stmqspi_write_code);
1468 code = stmoctospi_read_code;
1469 codesize = sizeof(stmoctospi_read_code);
1471 code = stmqspi_read_code;
1472 codesize = sizeof(stmqspi_read_code);
1476 /* for write, pagesize must be taken into account */
1477 /* for read, the page size doesn't matter that much */
1478 pagesize = stmqspi_info->dev.pagesize;
1480 pagesize = (fifosize <= SPIFLASH_DEF_PAGESIZE) ?
1481 fifosize : SPIFLASH_DEF_PAGESIZE;
1483 /* adjust sizes according to dual flash mode */
1487 /* memory buffer, we assume sectorsize to be a power of 2 times pagesize */
1488 maxsize = target_get_working_area_avail(target);
1489 if (maxsize < codesize + 2 * sizeof(uint32_t) + pagesize) {
1490 LOG_ERROR("not enough working area, can't do QSPI page reads/writes");
1491 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1494 /* fifo size at most sector size, and multiple of page size */
1495 maxsize -= (codesize + 2 * sizeof(uint32_t));
1496 fifosize = ((maxsize < fifosize) ? maxsize : fifosize) & ~(pagesize - 1);
1498 if (target_alloc_working_area_try(target,
1499 codesize + 2 * sizeof(uint32_t) + fifosize, &algorithm) != ERROR_OK) {
1500 LOG_ERROR("allocating working area failed");
1501 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1504 /* prepare flash write code, excluding ccr_buffer */
1505 retval = target_write_buffer(target, algorithm->address,
1506 codesize - sizeof(ccr_buffer), code);
1507 if (retval != ERROR_OK)
1510 /* prepare QSPI/OCTOSPI_CCR register values */
1511 retval = target_write_buffer(target, algorithm->address
1512 + codesize - sizeof(ccr_buffer),
1513 sizeof(ccr_buffer), (uint8_t *)ccr_buffer);
1514 if (retval != ERROR_OK)
1517 /* target buffer starts right after flash_write_code, i.e.
1518 * wp and rp are implicitly included in buffer!!! */
1519 fifo_start = algorithm->address + codesize + 2 * sizeof(uint32_t);
1521 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* count (in), status (out) */
1522 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* pagesize */
1523 init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT); /* offset into flash address */
1524 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* QSPI/OCTOSPI io_base */
1525 init_reg_param(®_params[4], "r8", 32, PARAM_OUT); /* fifo start */
1526 init_reg_param(®_params[5], "r9", 32, PARAM_OUT); /* fifo end + 1 */
1528 buf_set_u32(reg_params[0].value, 0, 32, count);
1529 buf_set_u32(reg_params[1].value, 0, 32, pagesize);
1530 buf_set_u32(reg_params[2].value, 0, 32, offset);
1531 buf_set_u32(reg_params[3].value, 0, 32, io_base);
1532 buf_set_u32(reg_params[4].value, 0, 32, fifo_start);
1533 buf_set_u32(reg_params[5].value, 0, 32, fifo_start + fifosize);
1535 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1536 armv7m_info.core_mode = ARM_MODE_THREAD;
1538 /* after breakpoint instruction (halfword), one nop (halfword) and
1539 * ccr_buffer follow till end of code */
1540 exit_point = algorithm->address + codesize
1541 - (sizeof(ccr_buffer) + sizeof(uint32_t));
1544 retval = target_run_flash_async_algorithm(target, buffer, count, 1,
1546 ARRAY_SIZE(reg_params), reg_params,
1547 algorithm->address + codesize,
1548 fifosize + 2 * sizeof(uint32_t),
1549 algorithm->address, exit_point,
1552 retval = target_run_read_async_algorithm(target, buffer, count, 1,
1554 ARRAY_SIZE(reg_params), reg_params,
1555 algorithm->address + codesize,
1556 fifosize + 2 * sizeof(uint32_t),
1557 algorithm->address, exit_point,
1561 remaining = buf_get_u32(reg_params[0].value, 0, 32);
1562 if ((retval == ERROR_OK) && remaining)
1563 retval = ERROR_FLASH_OPERATION_FAILED;
1565 if (retval != ERROR_OK) {
1566 offset = buf_get_u32(reg_params[2].value, 0, 32);
1567 LOG_ERROR("flash %s failed at address 0x%" PRIx32 ", remaining 0x%" PRIx32,
1568 write ? "write" : "read", offset, remaining);
1571 destroy_reg_param(®_params[0]);
1572 destroy_reg_param(®_params[1]);
1573 destroy_reg_param(®_params[2]);
1574 destroy_reg_param(®_params[3]);
1575 destroy_reg_param(®_params[4]);
1576 destroy_reg_param(®_params[5]);
1579 target_free_working_area(target, algorithm);
1581 /* Switch to memory mapped mode before return to prompt */
1587 static int stmqspi_read(struct flash_bank *bank, uint8_t *buffer,
1588 uint32_t offset, uint32_t count)
1590 struct target *target = bank->target;
1591 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1594 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
1595 __func__, offset, count);
1597 if (target->state != TARGET_HALTED) {
1598 LOG_ERROR("Target not halted");
1599 return ERROR_TARGET_NOT_HALTED;
1602 if (!(stmqspi_info->probed)) {
1603 LOG_ERROR("Flash bank not probed");
1604 return ERROR_FLASH_BANK_NOT_PROBED;
1607 if (offset + count > bank->size) {
1608 LOG_WARNING("Read beyond end of flash. Extra data to be ignored.");
1609 count = bank->size - offset;
1612 /* Abort any previous operation */
1613 retval = stmqspi_abort(bank);
1614 if (retval != ERROR_OK)
1617 /* Wait for busy to be cleared */
1618 retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1619 if (retval != ERROR_OK)
1622 return qspi_read_write_block(bank, buffer, offset, count, false);
1625 static int stmqspi_write(struct flash_bank *bank, const uint8_t *buffer,
1626 uint32_t offset, uint32_t count)
1628 struct target *target = bank->target;
1629 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1630 unsigned int dual, sector;
1634 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
1635 __func__, offset, count);
1637 dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
1638 octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
1640 if (target->state != TARGET_HALTED) {
1641 LOG_ERROR("Target not halted");
1642 return ERROR_TARGET_NOT_HALTED;
1645 if (!(stmqspi_info->probed)) {
1646 LOG_ERROR("Flash bank not probed");
1647 return ERROR_FLASH_BANK_NOT_PROBED;
1650 if (offset + count > bank->size) {
1651 LOG_WARNING("Write beyond end of flash. Extra data discarded.");
1652 count = bank->size - offset;
1655 /* Check sector protection */
1656 for (sector = 0; sector < bank->num_sectors; sector++) {
1657 /* Start offset in or before this sector? */
1658 /* End offset in or behind this sector? */
1659 if ((offset < (bank->sectors[sector].offset + bank->sectors[sector].size)) &&
1660 ((offset + count - 1) >= bank->sectors[sector].offset) &&
1661 bank->sectors[sector].is_protected) {
1662 LOG_ERROR("Flash sector %u protected", sector);
1663 return ERROR_FLASH_PROTECTED;
1667 if ((dual || octal_dtr) && ((offset & 1) != 0 || (count & 1) != 0)) {
1668 LOG_ERROR("In dual-QSPI and octal-DTR modes writes must be two byte aligned: "
1669 "%s: address=0x%08" PRIx32 " len=0x%08" PRIx32, __func__, offset, count);
1670 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1673 /* Abort any previous operation */
1674 retval = stmqspi_abort(bank);
1675 if (retval != ERROR_OK)
1678 /* Wait for busy to be cleared */
1679 retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1680 if (retval != ERROR_OK)
1683 return qspi_read_write_block(bank, (uint8_t *)buffer, offset, count, true);
1686 static int stmqspi_verify(struct flash_bank *bank, const uint8_t *buffer,
1687 uint32_t offset, uint32_t count)
1689 struct target *target = bank->target;
1690 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1695 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
1696 __func__, offset, count);
1698 dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
1699 octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
1701 if (target->state != TARGET_HALTED) {
1702 LOG_ERROR("Target not halted");
1703 return ERROR_TARGET_NOT_HALTED;
1706 if (!(stmqspi_info->probed)) {
1707 LOG_ERROR("Flash bank not probed");
1708 return ERROR_FLASH_BANK_NOT_PROBED;
1711 if (offset + count > bank->size) {
1712 LOG_WARNING("Verify beyond end of flash. Extra data ignored.");
1713 count = bank->size - offset;
1716 if ((dual || octal_dtr) && ((offset & 1) != 0 || (count & 1) != 0)) {
1717 LOG_ERROR("In dual-QSPI and octal-DTR modes reads must be two byte aligned: "
1718 "%s: address=0x%08" PRIx32 " len=0x%08" PRIx32, __func__, offset, count);
1719 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1722 /* Abort any previous operation */
1723 retval = stmqspi_abort(bank);
1724 if (retval != ERROR_OK)
1727 /* Wait for busy to be cleared */
1728 retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1729 if (retval != ERROR_OK)
1732 return qspi_verify(bank, (uint8_t *)buffer, offset, count);
1735 /* Find appropriate dummy setting, in particular octo mode */
1736 static int find_sfdp_dummy(struct flash_bank *bank, int len)
1738 struct target *target = bank->target;
1739 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1740 uint32_t io_base = stmqspi_info->io_base;
1742 unsigned int dual, count;
1743 bool flash1 = !(stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH));
1745 const unsigned int max_bytes = 64;
1747 dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
1749 LOG_DEBUG("%s: len=%d, dual=%u, flash1=%d",
1750 __func__, len, dual, flash1);
1752 /* Abort any previous operation */
1753 retval = target_write_u32(target, io_base + SPI_CR,
1754 stmqspi_info->saved_cr | BIT(SPI_ABORT));
1755 if (retval != ERROR_OK)
1758 /* Wait for busy to be cleared */
1759 retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1760 if (retval != ERROR_OK)
1763 /* Switch to saved_cr (had to be set accordingly before this call) */
1764 retval = target_write_u32(target, io_base + SPI_CR, stmqspi_info->saved_cr);
1765 if (retval != ERROR_OK)
1768 /* Read at most that many bytes */
1769 retval = target_write_u32(target, io_base + SPI_DLR, (max_bytes << dual) - 1);
1770 if (retval != ERROR_OK)
1773 /* Read SFDP block */
1775 retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
1776 OCTOSPI_CCR_READ_SFDP(len), SPIFLASH_READ_SFDP);
1778 retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_SFDP);
1779 if (retval != ERROR_OK)
1782 /* Read from start of sfdp block */
1783 retval = target_write_u32(target, io_base + SPI_AR, 0);
1784 if (retval != ERROR_OK)
1787 for (count = 0 ; count < max_bytes; count++) {
1788 if ((dual != 0) && !flash1) {
1789 /* discard even byte in dual flash-mode if flash2 */
1790 retval = target_read_u8(target, io_base + SPI_DR, &data);
1791 if (retval != ERROR_OK)
1795 retval = target_read_u8(target, io_base + SPI_DR, &data);
1796 if (retval != ERROR_OK)
1800 LOG_DEBUG("start of SFDP header for flash%c after %u dummy bytes",
1801 flash1 ? '1' : '2', count);
1803 stmqspi_info->sfdp_dummy1 = count;
1805 stmqspi_info->sfdp_dummy2 = count;
1809 if ((dual != 0) && flash1) {
1810 /* discard odd byte in dual flash-mode if flash1 */
1811 retval = target_read_u8(target, io_base + SPI_DR, &data);
1812 if (retval != ERROR_OK)
1817 retval = ERROR_FAIL;
1818 LOG_DEBUG("no start of SFDP header even after %u dummy bytes", count);
1821 /* Abort operation */
1822 retval = stmqspi_abort(bank);
1827 /* Read SFDP parameter block */
1828 static int read_sfdp_block(struct flash_bank *bank, uint32_t addr,
1829 uint32_t words, uint32_t *buffer)
1831 struct target *target = bank->target;
1832 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1833 uint32_t io_base = stmqspi_info->io_base;
1834 bool flash1 = !(stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH));
1835 unsigned int dual, count, len, *dummy;
1838 dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
1840 if (IS_OCTOSPI && (((stmqspi_info->saved_ccr >> SPI_DMODE_POS) & 0x7) > 3)) {
1841 /* in OCTO mode 4-byte address and (yet) unknown number of dummy clocks */
1844 /* in octo mode, use sfdp_dummy1 only */
1845 dummy = &stmqspi_info->sfdp_dummy1;
1847 retval = find_sfdp_dummy(bank, len);
1848 if (retval != ERROR_OK)
1852 /* in all other modes 3-byte-address and 8(?) dummy clocks */
1855 /* use sfdp_dummy1/2 according to currently selected flash */
1856 dummy = (stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH)) ?
1857 &stmqspi_info->sfdp_dummy2 : &stmqspi_info->sfdp_dummy1;
1859 /* according to SFDP standard, there should always be 8 dummy *CLOCKS*
1860 * giving 1, 2 or 4 dummy *BYTES*, however, this is apparently not
1861 * always implemented correctly, so determine the number of dummy bytes
1864 retval = find_sfdp_dummy(bank, len);
1865 if (retval != ERROR_OK)
1870 LOG_DEBUG("%s: addr=0x%08" PRIx32 " words=0x%08" PRIx32 " dummy=%u",
1871 __func__, addr, words, *dummy);
1873 /* Abort any previous operation */
1874 retval = target_write_u32(target, io_base + SPI_CR,
1875 stmqspi_info->saved_cr | BIT(SPI_ABORT));
1876 if (retval != ERROR_OK)
1879 /* Wait for busy to be cleared */
1880 retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1881 if (retval != ERROR_OK)
1884 /* Switch to one flash only */
1885 retval = target_write_u32(target, io_base + SPI_CR, stmqspi_info->saved_cr);
1886 if (retval != ERROR_OK)
1889 /* Read that many words plus dummy bytes */
1890 retval = target_write_u32(target, io_base + SPI_DLR,
1891 ((*dummy + words * sizeof(uint32_t)) << dual) - 1);
1892 if (retval != ERROR_OK)
1895 /* Read SFDP block */
1897 retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
1898 OCTOSPI_CCR_READ_SFDP(len), SPIFLASH_READ_SFDP);
1900 retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_SFDP);
1901 if (retval != ERROR_OK)
1904 retval = target_write_u32(target, io_base + SPI_AR, addr << dual);
1905 if (retval != ERROR_OK)
1909 for (count = *dummy << dual; count > 0; --count) {
1910 retval = target_read_u8(target, io_base + SPI_DR, (uint8_t *)buffer);
1911 if (retval != ERROR_OK)
1915 for ( ; words > 0; words--) {
1917 uint32_t word1, word2;
1919 retval = target_read_u32(target, io_base + SPI_DR, &word1);
1920 if (retval != ERROR_OK)
1922 retval = target_read_u32(target, io_base + SPI_DR, &word2);
1923 if (retval != ERROR_OK)
1927 /* shift odd numbered bytes into even numbered ones */
1932 /* pack even numbered bytes into one word */
1933 *buffer = (word1 & 0xFFU) | ((word1 & 0xFF0000U) >> 8) |
1934 ((word2 & 0xFFU) << 16) | ((word2 & 0xFF0000U) << 8);
1938 retval = target_read_u32(target, io_base + SPI_DR, buffer);
1939 if (retval != ERROR_OK)
1942 LOG_DEBUG("raw SFDP data 0x%08" PRIx32, *buffer);
1944 /* endian correction, sfdp data is always le uint32_t based */
1945 *buffer = le_to_h_u32((uint8_t *)buffer);
1953 /* Return ID of flash device(s) */
1954 /* On exit, indirect mode is kept */
1955 static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)
1957 struct target *target = bank->target;
1958 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
1959 uint32_t io_base = stmqspi_info->io_base;
1961 unsigned int type, count, len1, len2;
1962 int retval = ERROR_OK;
1964 /* invalidate both ids */
1968 if (target->state != TARGET_HALTED) {
1969 LOG_ERROR("Target not halted");
1970 return ERROR_TARGET_NOT_HALTED;
1973 /* SPIFLASH_READ_MID causes device in octal mode to go berserk, so don't use in this case */
1974 for (type = (IS_OCTOSPI && OPI_MODE) ? 1 : 0; type < 2 ; type++) {
1975 /* Abort any previous operation */
1976 retval = stmqspi_abort(bank);
1977 if (retval != ERROR_OK)
1981 retval = wait_till_ready(bank, SPI_PROBE_TIMEOUT);
1982 if (retval != ERROR_OK)
1985 /* Wait for busy to be cleared */
1986 retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
1987 if (retval != ERROR_OK)
1990 /* Read at most 16 bytes per chip */
1992 retval = target_write_u32(target, io_base + SPI_DLR,
1993 (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH) ? count * 2 : count) - 1);
1994 if (retval != ERROR_OK)
1997 /* Read id: one particular flash chip (N25Q128) switches back to SPI mode when receiving
1998 * SPI_FLASH_READ_ID in QPI mode, hence try SPIFLASH_READ_MID first */
2002 retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
2003 OCTOSPI_CCR_READ_MID, SPIFLASH_READ_MID);
2005 retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_MID);
2010 retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
2011 OCTOSPI_CCR_READ_ID, SPIFLASH_READ_ID);
2013 retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_ID);
2020 if (retval != ERROR_OK)
2023 /* Dummy address 0, only required for 8-line mode */
2024 if (IS_OCTOSPI && OPI_MODE) {
2025 retval = target_write_u32(target, io_base + SPI_AR, 0);
2026 if (retval != ERROR_OK)
2030 /* for debugging only */
2032 (void)target_read_u32(target, io_base + SPI_SR, &dummy);
2034 /* Read ID from Data Register */
2035 for (len1 = 0, len2 = 0; count > 0; --count) {
2036 if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
2037 BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) {
2038 retval = target_read_u8(target, io_base + SPI_DR, &byte);
2039 if (retval != ERROR_OK)
2041 /* collect 3 bytes without continuation codes */
2042 if ((byte != 0x7F) && (len1 < 3)) {
2043 *id1 = (*id1 >> 8) | ((uint32_t)byte) << 16;
2047 if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
2048 BIT(SPI_FSEL_FLASH))) != 0) {
2049 retval = target_read_u8(target, io_base + SPI_DR, &byte);
2050 if (retval != ERROR_OK)
2052 /* collect 3 bytes without continuation codes */
2053 if ((byte != 0x7F) && (len2 < 3)) {
2054 *id2 = (*id2 >> 8) | ((uint32_t)byte) << 16;
2060 if (((*id1 != 0x000000) && (*id1 != 0xFFFFFF)) ||
2061 ((*id2 != 0x000000) && (*id2 != 0xFFFFFF)))
2065 if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
2066 BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) {
2067 if ((*id1 == 0x000000) || (*id1 == 0xFFFFFF)) {
2068 /* no id retrieved, so id must be set manually */
2069 LOG_INFO("No id from flash1");
2070 retval = ERROR_FLASH_BANK_NOT_PROBED;
2074 if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) {
2075 if ((*id2 == 0x000000) || (*id2 == 0xFFFFFF)) {
2076 /* no id retrieved, so id must be set manually */
2077 LOG_INFO("No id from flash2");
2078 retval = ERROR_FLASH_BANK_NOT_PROBED;
2086 static int stmqspi_probe(struct flash_bank *bank)
2088 struct target *target = bank->target;
2089 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
2090 struct flash_sector *sectors = NULL;
2091 uint32_t io_base = stmqspi_info->io_base;
2092 uint32_t id1 = 0, id2 = 0, data = 0;
2093 const struct flash_device *p;
2094 const uint32_t magic = 0xAEF1510E;
2095 unsigned int dual, fsize;
2099 if (stmqspi_info->probed) {
2101 bank->num_sectors = 0;
2102 free(bank->sectors);
2103 bank->sectors = NULL;
2104 memset(&stmqspi_info->dev, 0, sizeof(stmqspi_info->dev));
2105 stmqspi_info->sfdp_dummy1 = 0;
2106 stmqspi_info->sfdp_dummy2 = 0;
2107 stmqspi_info->probed = false;
2110 /* Abort any previous operation */
2111 retval = stmqspi_abort(bank);
2112 if (retval != ERROR_OK)
2115 /* Wait for busy to be cleared */
2116 retval = poll_busy(bank, SPI_PROBE_TIMEOUT);
2117 if (retval != ERROR_OK)
2120 /* check whether QSPI_ABR is writeable and readback returns the value written */
2121 retval = target_write_u32(target, io_base + QSPI_ABR, magic);
2122 if (retval == ERROR_OK) {
2123 retval = target_read_u32(target, io_base + QSPI_ABR, &data);
2124 retval = target_write_u32(target, io_base + QSPI_ABR, 0);
2127 if (data == magic) {
2128 LOG_DEBUG("QSPI_ABR register present");
2129 stmqspi_info->octo = false;
2133 retval = target_read_u32(target, io_base + OCTOSPI_MAGIC, &magic_id);
2135 if (retval == ERROR_OK && magic_id == OCTO_MAGIC_ID) {
2136 LOG_DEBUG("OCTOSPI_MAGIC present");
2137 stmqspi_info->octo = true;
2139 LOG_ERROR("No QSPI, no OCTOSPI at 0x%08" PRIx32, io_base);
2140 stmqspi_info->probed = false;
2141 stmqspi_info->dev.name = "none";
2146 /* save current FSEL and DFM bits in QSPI/OCTOSPI_CR, current QSPI/OCTOSPI_CCR value */
2147 retval = target_read_u32(target, io_base + SPI_CR, &stmqspi_info->saved_cr);
2148 if (retval == ERROR_OK)
2149 retval = target_read_u32(target, io_base + SPI_CCR, &stmqspi_info->saved_ccr);
2154 retval = target_read_u32(target, io_base + OCTOSPI_DCR1, &dcr1);
2156 if (retval == ERROR_OK)
2157 retval = target_read_u32(target, io_base + OCTOSPI_TCR,
2158 &stmqspi_info->saved_tcr);
2160 if (retval == ERROR_OK)
2161 retval = target_read_u32(target, io_base + OCTOSPI_IR,
2162 &stmqspi_info->saved_ir);
2164 if (retval != ERROR_OK) {
2165 LOG_ERROR("No OCTOSPI at io_base 0x%08" PRIx32, io_base);
2166 stmqspi_info->probed = false;
2167 stmqspi_info->dev.name = "none";
2171 const uint32_t mtyp = (dcr1 & OCTOSPI_MTYP_MASK) >> OCTOSPI_MTYP_POS;
2173 if ((mtyp != 0x0) && (mtyp != 0x1)) {
2174 LOG_ERROR("Only regular SPI protocol supported in OCTOSPI");
2175 stmqspi_info->probed = false;
2176 stmqspi_info->dev.name = "none";
2180 LOG_DEBUG("OCTOSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", OCTOSPI_CR 0x%08"
2181 PRIx32 ", OCTOSPI_CCR 0x%08" PRIx32 ", %d-byte addr", bank->base, io_base,
2182 stmqspi_info->saved_cr, stmqspi_info->saved_ccr, SPI_ADSIZE);
2184 if (retval == ERROR_OK) {
2185 LOG_DEBUG("QSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", QSPI_CR 0x%08"
2186 PRIx32 ", QSPI_CCR 0x%08" PRIx32 ", %d-byte addr", bank->base, io_base,
2187 stmqspi_info->saved_cr, stmqspi_info->saved_ccr, SPI_ADSIZE);
2188 if (stmqspi_info->saved_ccr & (1U << QSPI_DDRM))
2189 LOG_WARNING("DDR mode is untested and suffers from some silicon bugs");
2191 LOG_ERROR("No QSPI at io_base 0x%08" PRIx32, io_base);
2192 stmqspi_info->probed = false;
2193 stmqspi_info->dev.name = "none";
2198 dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
2199 octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
2200 if (dual || octal_dtr)
2201 bank->write_start_alignment = bank->write_end_alignment = 2;
2203 bank->write_start_alignment = bank->write_end_alignment = 1;
2205 /* read and decode flash ID; returns in indirect mode */
2206 retval = read_flash_id(bank, &id1, &id2);
2207 LOG_DEBUG("id1 0x%06" PRIx32 ", id2 0x%06" PRIx32, id1, id2);
2208 if (retval == ERROR_FLASH_BANK_NOT_PROBED) {
2209 /* no id retrieved, so id must be set manually */
2210 LOG_INFO("No id - set flash parameters manually");
2215 if (retval != ERROR_OK)
2218 /* identify flash1 */
2219 for (p = flash_devices; id1 && p->name ; p++) {
2220 if (p->device_id == id1) {
2221 memcpy(&stmqspi_info->dev, p, sizeof(stmqspi_info->dev));
2222 if (p->size_in_bytes / 4096)
2223 LOG_INFO("flash1 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
2224 "kbytes", p->name, id1, p->size_in_bytes / 1024);
2226 LOG_INFO("flash1 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
2227 "bytes", p->name, id1, p->size_in_bytes);
2232 if (id1 && !p->name) {
2233 /* chip not been identified by id, then try SFDP */
2234 struct flash_device temp;
2235 uint32_t saved_cr = stmqspi_info->saved_cr;
2238 stmqspi_info->saved_cr = stmqspi_info->saved_cr & ~BIT(SPI_FSEL_FLASH);
2239 retval = spi_sfdp(bank, &temp, &read_sfdp_block);
2241 /* restore saved_cr */
2242 stmqspi_info->saved_cr = saved_cr;
2244 if (retval == ERROR_OK) {
2245 LOG_INFO("flash1 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
2246 "kbytes", temp.name, id1, temp.size_in_bytes / 1024);
2247 /* save info and retrieved *good* id as spi_sfdp clears all info */
2248 memcpy(&stmqspi_info->dev, &temp, sizeof(stmqspi_info->dev));
2249 stmqspi_info->dev.device_id = id1;
2251 /* even not identified by SFDP, then give up */
2252 LOG_WARNING("Unknown flash1 device id = 0x%06" PRIx32
2253 " - set flash parameters manually", id1);
2259 /* identify flash2 */
2260 for (p = flash_devices; id2 && p->name ; p++) {
2261 if (p->device_id == id2) {
2262 if (p->size_in_bytes / 4096)
2263 LOG_INFO("flash2 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
2264 "kbytes", p->name, id2, p->size_in_bytes / 1024);
2266 LOG_INFO("flash2 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
2267 "bytes", p->name, id2, p->size_in_bytes);
2270 memcpy(&stmqspi_info->dev, p, sizeof(stmqspi_info->dev));
2272 if ((stmqspi_info->dev.read_cmd != p->read_cmd) ||
2273 (stmqspi_info->dev.qread_cmd != p->qread_cmd) ||
2274 (stmqspi_info->dev.pprog_cmd != p->pprog_cmd) ||
2275 (stmqspi_info->dev.erase_cmd != p->erase_cmd) ||
2276 (stmqspi_info->dev.chip_erase_cmd != p->chip_erase_cmd) ||
2277 (stmqspi_info->dev.sectorsize != p->sectorsize) ||
2278 (stmqspi_info->dev.size_in_bytes != p->size_in_bytes)) {
2279 LOG_ERROR("Incompatible flash1/flash2 devices");
2282 /* page size is optional in SFDP, so accept smallest value */
2283 if (p->pagesize < stmqspi_info->dev.pagesize)
2284 stmqspi_info->dev.pagesize = p->pagesize;
2290 if (id2 && !p->name) {
2291 /* chip not been identified by id, then try SFDP */
2292 struct flash_device temp;
2293 uint32_t saved_cr = stmqspi_info->saved_cr;
2296 stmqspi_info->saved_cr = stmqspi_info->saved_cr | BIT(SPI_FSEL_FLASH);
2297 retval = spi_sfdp(bank, &temp, &read_sfdp_block);
2299 /* restore saved_cr */
2300 stmqspi_info->saved_cr = saved_cr;
2302 if (retval == ERROR_OK)
2303 LOG_INFO("flash2 \'%s\' id = 0x%06" PRIx32 " size = %" PRIu32
2304 "kbytes", temp.name, id2, temp.size_in_bytes / 1024);
2306 /* even not identified by SFDP, then give up */
2307 LOG_WARNING("Unknown flash2 device id = 0x%06" PRIx32
2308 " - set flash parameters manually", id2);
2314 memcpy(&stmqspi_info->dev, &temp, sizeof(stmqspi_info->dev));
2316 if ((stmqspi_info->dev.read_cmd != temp.read_cmd) ||
2317 (stmqspi_info->dev.qread_cmd != temp.qread_cmd) ||
2318 (stmqspi_info->dev.pprog_cmd != temp.pprog_cmd) ||
2319 (stmqspi_info->dev.erase_cmd != temp.erase_cmd) ||
2320 (stmqspi_info->dev.chip_erase_cmd != temp.chip_erase_cmd) ||
2321 (stmqspi_info->dev.sectorsize != temp.sectorsize) ||
2322 (stmqspi_info->dev.size_in_bytes != temp.size_in_bytes)) {
2323 LOG_ERROR("Incompatible flash1/flash2 devices");
2326 /* page size is optional in SFDP, so accept smallest value */
2327 if (temp.pagesize < stmqspi_info->dev.pagesize)
2328 stmqspi_info->dev.pagesize = temp.pagesize;
2332 /* Set correct size value */
2333 bank->size = stmqspi_info->dev.size_in_bytes << dual;
2336 retval = target_read_u32(target, io_base + SPI_DCR, &dcr);
2338 if (retval != ERROR_OK)
2341 fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
2343 LOG_DEBUG("FSIZE = 0x%04x", fsize);
2344 if (bank->size == BIT((fsize + 1)))
2345 LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
2346 else if (bank->size == BIT((fsize + 0)))
2347 LOG_DEBUG("FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?");
2349 LOG_ERROR("FSIZE in DCR(1) doesn't match actual capacity.");
2351 /* if no sectors, then treat whole flash as single sector */
2352 if (stmqspi_info->dev.sectorsize == 0)
2353 stmqspi_info->dev.sectorsize = stmqspi_info->dev.size_in_bytes;
2354 /* if no page_size, then use sectorsize as page_size */
2355 if (stmqspi_info->dev.pagesize == 0)
2356 stmqspi_info->dev.pagesize = stmqspi_info->dev.sectorsize;
2358 /* create and fill sectors array */
2359 bank->num_sectors = stmqspi_info->dev.size_in_bytes / stmqspi_info->dev.sectorsize;
2360 sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
2361 if (sectors == NULL) {
2362 LOG_ERROR("not enough memory");
2363 retval = ERROR_FAIL;
2367 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
2368 sectors[sector].offset = sector * (stmqspi_info->dev.sectorsize << dual);
2369 sectors[sector].size = (stmqspi_info->dev.sectorsize << dual);
2370 sectors[sector].is_erased = -1;
2371 sectors[sector].is_protected = 0;
2374 bank->sectors = sectors;
2375 stmqspi_info->probed = true;
2378 /* Switch to memory mapped mode before return to prompt */
2384 static int stmqspi_auto_probe(struct flash_bank *bank)
2386 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
2388 if (stmqspi_info->probed)
2390 stmqspi_probe(bank);
2394 static int stmqspi_protect_check(struct flash_bank *bank)
2396 /* Nothing to do. Protection is only handled in SW. */
2400 static int get_stmqspi_info(struct flash_bank *bank, char *buf, int buf_size)
2402 struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
2404 if (!(stmqspi_info->probed)) {
2405 snprintf(buf, buf_size,
2406 "\nQSPI flash bank not probed yet\n");
2407 return ERROR_FLASH_BANK_NOT_PROBED;
2410 snprintf(buf, buf_size, "flash%s%s \'%s\', device id = 0x%06" PRIx32
2411 ", flash size = %" PRIu32 "%sbytes\n(page size = %" PRIu32
2412 ", read = 0x%02" PRIx8 ", qread = 0x%02" PRIx8
2413 ", pprog = 0x%02" PRIx8 ", mass_erase = 0x%02" PRIx8
2414 ", sector size = %" PRIu32 "%sbytes, sector_erase = 0x%02" PRIx8 ")",
2415 ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
2416 BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) ? "1" : "",
2417 ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
2418 BIT(SPI_FSEL_FLASH))) != 0) ? "2" : "",
2419 stmqspi_info->dev.name, stmqspi_info->dev.device_id,
2420 bank->size / 4096 ? bank->size / 1024 : bank->size,
2421 bank->size / 4096 ? "k" : "", stmqspi_info->dev.pagesize,
2422 stmqspi_info->dev.read_cmd, stmqspi_info->dev.qread_cmd,
2423 stmqspi_info->dev.pprog_cmd, stmqspi_info->dev.chip_erase_cmd,
2424 stmqspi_info->dev.sectorsize / 4096 ?
2425 stmqspi_info->dev.sectorsize / 1024 : stmqspi_info->dev.sectorsize,
2426 stmqspi_info->dev.sectorsize / 4096 ? "k" : "",
2427 stmqspi_info->dev.erase_cmd);
2432 static const struct command_registration stmqspi_exec_command_handlers[] = {
2434 .name = "mass_erase",
2435 .handler = stmqspi_handle_mass_erase_command,
2436 .mode = COMMAND_EXEC,
2438 .help = "Mass erase entire flash device.",
2442 .handler = stmqspi_handle_set,
2443 .mode = COMMAND_EXEC,
2444 .usage = "bank_id name chip_size page_size read_cmd qread_cmd pprg_cmd "
2445 "[ mass_erase_cmd ] [ sector_size sector_erase_cmd ]",
2446 .help = "Set params of single flash chip",
2450 .handler = stmqspi_handle_cmd,
2451 .mode = COMMAND_EXEC,
2452 .usage = "bank_id num_resp cmd_byte ...",
2453 .help = "Send low-level command cmd_byte and following bytes or read num_resp.",
2455 COMMAND_REGISTRATION_DONE
2458 static const struct command_registration stmqspi_command_handlers[] = {
2461 .mode = COMMAND_ANY,
2462 .help = "stmqspi flash command group",
2464 .chain = stmqspi_exec_command_handlers,
2466 COMMAND_REGISTRATION_DONE
2469 struct flash_driver stmqspi_flash = {
2471 .commands = stmqspi_command_handlers,
2472 .flash_bank_command = stmqspi_flash_bank_command,
2473 .erase = stmqspi_erase,
2474 .protect = stmqspi_protect,
2475 .write = stmqspi_write,
2476 .read = stmqspi_read,
2477 .verify = stmqspi_verify,
2478 .probe = stmqspi_probe,
2479 .auto_probe = stmqspi_auto_probe,
2480 .erase_check = stmqspi_blank_check,
2481 .protect_check = stmqspi_protect_check,
2482 .info = get_stmqspi_info,
2483 .free_driver_priv = default_flash_free_driver_priv,