1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
34 static int stm32x_mass_erase(struct flash_bank *bank);
36 /* flash bank stm32x <base> <size> 0 0 <target#>
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
40 struct stm32x_flash_bank *stm32x_info;
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID;
48 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
49 bank->driver_priv = stm32x_info;
51 stm32x_info->write_algorithm = NULL;
52 stm32x_info->probed = 0;
57 static uint32_t stm32x_get_flash_status(struct flash_bank *bank)
59 struct target *target = bank->target;
62 target_read_u32(target, STM32_FLASH_SR, &status);
67 static uint32_t stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
69 struct target *target = bank->target;
72 /* wait for busy to clear */
73 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
75 LOG_DEBUG("status: 0x%" PRIx32 "", status);
78 /* Clear but report errors */
79 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
81 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
86 static int stm32x_read_options(struct flash_bank *bank)
89 struct stm32x_flash_bank *stm32x_info = NULL;
90 struct target *target = bank->target;
92 stm32x_info = bank->driver_priv;
94 /* read current option bytes */
95 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
97 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
98 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
100 if (optiondata & (1 << OPT_READOUT))
101 LOG_INFO("Device Security Bit Set");
103 /* each bit refers to a 4bank protection */
104 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
106 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
107 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
108 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
109 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
114 static int stm32x_erase_options(struct flash_bank *bank)
116 struct stm32x_flash_bank *stm32x_info = NULL;
117 struct target *target = bank->target;
120 stm32x_info = bank->driver_priv;
122 /* read current options */
123 stm32x_read_options(bank);
125 /* unlock flash registers */
126 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
127 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
129 /* unlock option flash registers */
130 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
131 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
133 /* erase option bytes */
134 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
135 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
137 status = stm32x_wait_status_busy(bank, 10);
139 if (status & FLASH_WRPRTERR)
140 return ERROR_FLASH_OPERATION_FAILED;
141 if (status & FLASH_PGERR)
142 return ERROR_FLASH_OPERATION_FAILED;
144 /* clear readout protection and complementary option bytes
145 * this will also force a device unlock if set */
146 stm32x_info->option_bytes.RDP = 0x5AA5;
151 static int stm32x_write_options(struct flash_bank *bank)
153 struct stm32x_flash_bank *stm32x_info = NULL;
154 struct target *target = bank->target;
157 stm32x_info = bank->driver_priv;
159 /* unlock flash registers */
160 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
161 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
163 /* unlock option flash registers */
164 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
165 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
167 /* program option bytes */
168 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
170 /* write user option byte */
171 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
173 status = stm32x_wait_status_busy(bank, 10);
175 if (status & FLASH_WRPRTERR)
176 return ERROR_FLASH_OPERATION_FAILED;
177 if (status & FLASH_PGERR)
178 return ERROR_FLASH_OPERATION_FAILED;
180 /* write protection byte 1 */
181 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
183 status = stm32x_wait_status_busy(bank, 10);
185 if (status & FLASH_WRPRTERR)
186 return ERROR_FLASH_OPERATION_FAILED;
187 if (status & FLASH_PGERR)
188 return ERROR_FLASH_OPERATION_FAILED;
190 /* write protection byte 2 */
191 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
193 status = stm32x_wait_status_busy(bank, 10);
195 if (status & FLASH_WRPRTERR)
196 return ERROR_FLASH_OPERATION_FAILED;
197 if (status & FLASH_PGERR)
198 return ERROR_FLASH_OPERATION_FAILED;
200 /* write protection byte 3 */
201 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
203 status = stm32x_wait_status_busy(bank, 10);
205 if (status & FLASH_WRPRTERR)
206 return ERROR_FLASH_OPERATION_FAILED;
207 if (status & FLASH_PGERR)
208 return ERROR_FLASH_OPERATION_FAILED;
210 /* write protection byte 4 */
211 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
213 status = stm32x_wait_status_busy(bank, 10);
215 if (status & FLASH_WRPRTERR)
216 return ERROR_FLASH_OPERATION_FAILED;
217 if (status & FLASH_PGERR)
218 return ERROR_FLASH_OPERATION_FAILED;
220 /* write readout protection bit */
221 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
223 status = stm32x_wait_status_busy(bank, 10);
225 if (status & FLASH_WRPRTERR)
226 return ERROR_FLASH_OPERATION_FAILED;
227 if (status & FLASH_PGERR)
228 return ERROR_FLASH_OPERATION_FAILED;
230 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
235 static int stm32x_protect_check(struct flash_bank *bank)
237 struct target *target = bank->target;
238 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
245 if (target->state != TARGET_HALTED)
247 LOG_ERROR("Target not halted");
248 return ERROR_TARGET_NOT_HALTED;
251 /* medium density - each bit refers to a 4bank protection
252 * high density - each bit refers to a 2bank protection */
253 target_read_u32(target, STM32_FLASH_WRPR, &protection);
255 /* medium density - each protection bit is for 4 * 1K pages
256 * high density - each protection bit is for 2 * 2K pages */
257 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
259 if (stm32x_info->ppage_size == 2)
261 /* high density flash/connectivity line protection */
265 if (protection & (1 << 31))
268 /* bit 31 controls sector 62 - 255 protection for high density
269 * bit 31 controls sector 62 - 127 protection for connectivity line */
270 for (s = 62; s < bank->num_sectors; s++)
272 bank->sectors[s].is_protected = set;
275 if (bank->num_sectors > 61)
278 for (i = 0; i < num_bits; i++)
282 if (protection & (1 << i))
285 for (s = 0; s < stm32x_info->ppage_size; s++)
286 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
291 /* low/medium density flash protection */
292 for (i = 0; i < num_bits; i++)
296 if (protection & (1 << i))
299 for (s = 0; s < stm32x_info->ppage_size; s++)
300 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
307 static int stm32x_erase(struct flash_bank *bank, int first, int last)
309 struct target *target = bank->target;
313 if (bank->target->state != TARGET_HALTED)
315 LOG_ERROR("Target not halted");
316 return ERROR_TARGET_NOT_HALTED;
319 if ((first == 0) && (last == (bank->num_sectors - 1)))
321 return stm32x_mass_erase(bank);
324 /* unlock flash registers */
325 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
326 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
328 for (i = first; i <= last; i++)
330 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
331 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
332 target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
334 status = stm32x_wait_status_busy(bank, 100);
336 if (status & FLASH_WRPRTERR)
337 return ERROR_FLASH_OPERATION_FAILED;
338 if (status & FLASH_PGERR)
339 return ERROR_FLASH_OPERATION_FAILED;
340 bank->sectors[i].is_erased = 1;
343 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
348 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
350 struct stm32x_flash_bank *stm32x_info = NULL;
351 struct target *target = bank->target;
352 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
357 stm32x_info = bank->driver_priv;
359 if (target->state != TARGET_HALTED)
361 LOG_ERROR("Target not halted");
362 return ERROR_TARGET_NOT_HALTED;
365 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) &&
366 (last + 1) % stm32x_info->ppage_size))
368 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary",
369 stm32x_info->ppage_size);
370 return ERROR_FLASH_SECTOR_INVALID;
373 /* medium density - each bit refers to a 4bank protection
374 * high density - each bit refers to a 2bank protection */
375 target_read_u32(target, STM32_FLASH_WRPR, &protection);
377 prot_reg[0] = (uint16_t)protection;
378 prot_reg[1] = (uint16_t)(protection >> 8);
379 prot_reg[2] = (uint16_t)(protection >> 16);
380 prot_reg[3] = (uint16_t)(protection >> 24);
382 if (stm32x_info->ppage_size == 2)
384 /* high density flash */
386 /* bit 7 controls sector 62 - 255 protection */
390 prot_reg[3] &= ~(1 << 7);
392 prot_reg[3] |= (1 << 7);
400 for (i = first; i <= last; i++)
402 reg = (i / stm32x_info->ppage_size) / 8;
403 bit = (i / stm32x_info->ppage_size) - (reg * 8);
406 prot_reg[reg] &= ~(1 << bit);
408 prot_reg[reg] |= (1 << bit);
413 /* medium density flash */
414 for (i = first; i <= last; i++)
416 reg = (i / stm32x_info->ppage_size) / 8;
417 bit = (i / stm32x_info->ppage_size) - (reg * 8);
420 prot_reg[reg] &= ~(1 << bit);
422 prot_reg[reg] |= (1 << bit);
426 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
429 stm32x_info->option_bytes.protection[0] = prot_reg[0];
430 stm32x_info->option_bytes.protection[1] = prot_reg[1];
431 stm32x_info->option_bytes.protection[2] = prot_reg[2];
432 stm32x_info->option_bytes.protection[3] = prot_reg[3];
434 return stm32x_write_options(bank);
437 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
438 uint32_t offset, uint32_t count)
440 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
441 struct target *target = bank->target;
442 uint32_t buffer_size = 16384;
443 struct working_area *source;
444 uint32_t address = bank->base + offset;
445 struct reg_param reg_params[4];
446 struct armv7m_algorithm armv7m_info;
447 int retval = ERROR_OK;
449 static const uint8_t stm32x_flash_write_code[] = {
451 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
452 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
453 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
454 0x23, 0x60, /* str r3, [r4, #0] */
455 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
456 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
458 0x2B, 0x68, /* ldr r3, [r5, #0] */
459 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
460 0xFB, 0xD0, /* beq busy */
461 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
462 0x01, 0xD1, /* bne exit */
463 0x01, 0x3A, /* subs r2, r2, #1 */
464 0xED, 0xD1, /* bne write */
465 0x00, 0xBE, /* bkpt #0 */
466 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
467 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
470 /* flash write code */
471 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
472 &stm32x_info->write_algorithm) != ERROR_OK)
474 LOG_WARNING("no working area available, can't do block memory writes");
475 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
478 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
479 sizeof(stm32x_flash_write_code),
480 (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
484 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
487 if (buffer_size <= 256)
489 /* if we already allocated the writing code, but failed to get a
490 * buffer, free the algorithm */
491 if (stm32x_info->write_algorithm)
492 target_free_working_area(target, stm32x_info->write_algorithm);
494 LOG_WARNING("no large enough working area available, can't do block memory writes");
495 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
499 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
500 armv7m_info.core_mode = ARMV7M_MODE_ANY;
502 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
503 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
504 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
505 init_reg_param(®_params[3], "r3", 32, PARAM_IN);
509 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
510 (buffer_size / 2) : count;
512 if ((retval = target_write_buffer(target, source->address,
513 thisrun_count * 2, buffer)) != ERROR_OK)
516 buf_set_u32(reg_params[0].value, 0, 32, source->address);
517 buf_set_u32(reg_params[1].value, 0, 32, address);
518 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
520 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
521 stm32x_info->write_algorithm->address,
522 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10),
523 10000, &armv7m_info)) != ERROR_OK)
525 LOG_ERROR("error executing stm32x flash write algorithm");
526 retval = ERROR_FLASH_OPERATION_FAILED;
530 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
532 LOG_ERROR("flash memory not erased before writing");
533 /* Clear but report errors */
534 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
535 retval = ERROR_FLASH_OPERATION_FAILED;
539 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
541 LOG_ERROR("flash memory write protected");
542 /* Clear but report errors */
543 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
544 retval = ERROR_FLASH_OPERATION_FAILED;
548 buffer += thisrun_count * 2;
549 address += thisrun_count * 2;
550 count -= thisrun_count;
553 target_free_working_area(target, source);
554 target_free_working_area(target, stm32x_info->write_algorithm);
556 destroy_reg_param(®_params[0]);
557 destroy_reg_param(®_params[1]);
558 destroy_reg_param(®_params[2]);
559 destroy_reg_param(®_params[3]);
564 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
565 uint32_t offset, uint32_t count)
567 struct target *target = bank->target;
568 uint32_t words_remaining = (count / 2);
569 uint32_t bytes_remaining = (count & 0x00000001);
570 uint32_t address = bank->base + offset;
571 uint32_t bytes_written = 0;
575 if (bank->target->state != TARGET_HALTED)
577 LOG_ERROR("Target not halted");
578 return ERROR_TARGET_NOT_HALTED;
583 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
584 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
587 /* unlock flash registers */
588 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
589 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
591 /* multiple half words (2-byte) to be programmed? */
592 if (words_remaining > 0)
594 /* try using a block write */
595 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
597 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
599 /* if block write failed (no sufficient working area),
600 * we use normal (slow) single dword accesses */
601 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
603 else if (retval == ERROR_FLASH_OPERATION_FAILED)
605 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
606 return ERROR_FLASH_OPERATION_FAILED;
611 buffer += words_remaining * 2;
612 address += words_remaining * 2;
617 while (words_remaining > 0)
620 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
622 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
623 target_write_u16(target, address, value);
625 status = stm32x_wait_status_busy(bank, 5);
627 if (status & FLASH_WRPRTERR)
629 LOG_ERROR("flash memory not erased before writing");
630 return ERROR_FLASH_OPERATION_FAILED;
632 if (status & FLASH_PGERR)
634 LOG_ERROR("flash memory write protected");
635 return ERROR_FLASH_OPERATION_FAILED;
645 uint16_t value = 0xffff;
646 memcpy(&value, buffer + bytes_written, bytes_remaining);
648 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
649 target_write_u16(target, address, value);
651 status = stm32x_wait_status_busy(bank, 5);
653 if (status & FLASH_WRPRTERR)
655 LOG_ERROR("flash memory not erased before writing");
656 return ERROR_FLASH_OPERATION_FAILED;
658 if (status & FLASH_PGERR)
660 LOG_ERROR("flash memory write protected");
661 return ERROR_FLASH_OPERATION_FAILED;
665 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
670 static int stm32x_probe(struct flash_bank *bank)
672 struct target *target = bank->target;
673 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
679 stm32x_info->probed = 0;
681 /* read stm32 device id register */
682 target_read_u32(target, 0xE0042000, &device_id);
683 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
685 /* get flash size from target */
686 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
688 /* failed reading flash size, default to max target family */
692 if ((device_id & 0x7ff) == 0x410)
694 /* medium density - we have 1k pages
695 * 4 pages for a protection area */
697 stm32x_info->ppage_size = 4;
699 /* check for early silicon */
700 if (num_pages == 0xffff)
702 /* number of sectors incorrect on revA */
703 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
707 else if ((device_id & 0x7ff) == 0x412)
709 /* low density - we have 1k pages
710 * 4 pages for a protection area */
712 stm32x_info->ppage_size = 4;
714 /* check for early silicon */
715 if (num_pages == 0xffff)
717 /* number of sectors incorrect on revA */
718 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
722 else if ((device_id & 0x7ff) == 0x414)
724 /* high density - we have 2k pages
725 * 2 pages for a protection area */
727 stm32x_info->ppage_size = 2;
729 /* check for early silicon */
730 if (num_pages == 0xffff)
732 /* number of sectors incorrect on revZ */
733 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
737 else if ((device_id & 0x7ff) == 0x418)
739 /* connectivity line density - we have 2k pages
740 * 2 pages for a protection area */
742 stm32x_info->ppage_size = 2;
744 /* check for early silicon */
745 if (num_pages == 0xffff)
747 /* number of sectors incorrect on revZ */
748 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
752 else if ((device_id & 0x7ff) == 0x420)
754 /* value line density - we have 1k pages
755 * 4 pages for a protection area */
757 stm32x_info->ppage_size = 4;
759 /* check for early silicon */
760 if (num_pages == 0xffff)
762 /* number of sectors may be incorrrect on early silicon */
763 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
769 LOG_WARNING("Cannot identify target as a STM32 family.");
770 return ERROR_FLASH_OPERATION_FAILED;
773 LOG_INFO("flash size = %dkbytes", num_pages);
775 /* calculate numbers of pages */
776 num_pages /= (page_size / 1024);
778 bank->base = 0x08000000;
779 bank->size = (num_pages * page_size);
780 bank->num_sectors = num_pages;
781 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
783 for (i = 0; i < num_pages; i++)
785 bank->sectors[i].offset = i * page_size;
786 bank->sectors[i].size = page_size;
787 bank->sectors[i].is_erased = -1;
788 bank->sectors[i].is_protected = 1;
791 stm32x_info->probed = 1;
796 static int stm32x_auto_probe(struct flash_bank *bank)
798 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
799 if (stm32x_info->probed)
801 return stm32x_probe(bank);
805 COMMAND_HANDLER(stm32x_handle_part_id_command)
811 static int stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
813 struct target *target = bank->target;
817 /* read stm32 device id register */
818 target_read_u32(target, 0xE0042000, &device_id);
820 if ((device_id & 0x7ff) == 0x410)
822 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
826 switch (device_id >> 16)
829 snprintf(buf, buf_size, "A");
833 snprintf(buf, buf_size, "B");
837 snprintf(buf, buf_size, "Z");
841 snprintf(buf, buf_size, "Y");
845 snprintf(buf, buf_size, "unknown");
849 else if ((device_id & 0x7ff) == 0x412)
851 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
855 switch (device_id >> 16)
858 snprintf(buf, buf_size, "A");
862 snprintf(buf, buf_size, "unknown");
866 else if ((device_id & 0x7ff) == 0x414)
868 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
872 switch (device_id >> 16)
875 snprintf(buf, buf_size, "A");
879 snprintf(buf, buf_size, "Z");
883 snprintf(buf, buf_size, "unknown");
887 else if ((device_id & 0x7ff) == 0x418)
889 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
893 switch (device_id >> 16)
896 snprintf(buf, buf_size, "A");
900 snprintf(buf, buf_size, "Z");
904 snprintf(buf, buf_size, "unknown");
908 else if ((device_id & 0x7ff) == 0x420)
910 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
914 switch (device_id >> 16)
917 snprintf(buf, buf_size, "A");
921 snprintf(buf, buf_size, "Z");
925 snprintf(buf, buf_size, "unknown");
931 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
932 return ERROR_FLASH_OPERATION_FAILED;
938 COMMAND_HANDLER(stm32x_handle_lock_command)
940 struct target *target = NULL;
941 struct stm32x_flash_bank *stm32x_info = NULL;
945 command_print(CMD_CTX, "stm32x lock <bank>");
949 struct flash_bank *bank;
950 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
951 if (ERROR_OK != retval)
954 stm32x_info = bank->driver_priv;
956 target = bank->target;
958 if (target->state != TARGET_HALTED)
960 LOG_ERROR("Target not halted");
961 return ERROR_TARGET_NOT_HALTED;
964 if (stm32x_erase_options(bank) != ERROR_OK)
966 command_print(CMD_CTX, "stm32x failed to erase options");
970 /* set readout protection */
971 stm32x_info->option_bytes.RDP = 0;
973 if (stm32x_write_options(bank) != ERROR_OK)
975 command_print(CMD_CTX, "stm32x failed to lock device");
979 command_print(CMD_CTX, "stm32x locked");
984 COMMAND_HANDLER(stm32x_handle_unlock_command)
986 struct target *target = NULL;
987 struct stm32x_flash_bank *stm32x_info = NULL;
991 command_print(CMD_CTX, "stm32x unlock <bank>");
995 struct flash_bank *bank;
996 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
997 if (ERROR_OK != retval)
1000 stm32x_info = bank->driver_priv;
1002 target = bank->target;
1004 if (target->state != TARGET_HALTED)
1006 LOG_ERROR("Target not halted");
1007 return ERROR_TARGET_NOT_HALTED;
1010 if (stm32x_erase_options(bank) != ERROR_OK)
1012 command_print(CMD_CTX, "stm32x failed to unlock device");
1016 if (stm32x_write_options(bank) != ERROR_OK)
1018 command_print(CMD_CTX, "stm32x failed to lock device");
1022 command_print(CMD_CTX, "stm32x unlocked.\n"
1023 "INFO: a reset or power cycle is required "
1024 "for the new settings to take effect.");
1029 COMMAND_HANDLER(stm32x_handle_options_read_command)
1031 uint32_t optionbyte;
1032 struct target *target = NULL;
1033 struct stm32x_flash_bank *stm32x_info = NULL;
1037 command_print(CMD_CTX, "stm32x options_read <bank>");
1041 struct flash_bank *bank;
1042 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1043 if (ERROR_OK != retval)
1046 stm32x_info = bank->driver_priv;
1048 target = bank->target;
1050 if (target->state != TARGET_HALTED)
1052 LOG_ERROR("Target not halted");
1053 return ERROR_TARGET_NOT_HALTED;
1056 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1057 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1059 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1060 command_print(CMD_CTX, "Option Byte Complement Error");
1062 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1063 command_print(CMD_CTX, "Readout Protection On");
1065 command_print(CMD_CTX, "Readout Protection Off");
1067 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1068 command_print(CMD_CTX, "Software Watchdog");
1070 command_print(CMD_CTX, "Hardware Watchdog");
1072 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1073 command_print(CMD_CTX, "Stop: No reset generated");
1075 command_print(CMD_CTX, "Stop: Reset generated");
1077 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1078 command_print(CMD_CTX, "Standby: No reset generated");
1080 command_print(CMD_CTX, "Standby: Reset generated");
1085 COMMAND_HANDLER(stm32x_handle_options_write_command)
1087 struct target *target = NULL;
1088 struct stm32x_flash_bank *stm32x_info = NULL;
1089 uint16_t optionbyte = 0xF8;
1093 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1097 struct flash_bank *bank;
1098 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1099 if (ERROR_OK != retval)
1102 stm32x_info = bank->driver_priv;
1104 target = bank->target;
1106 if (target->state != TARGET_HALTED)
1108 LOG_ERROR("Target not halted");
1109 return ERROR_TARGET_NOT_HALTED;
1112 /* REVISIT: ignores some options which we will display...
1113 * and doesn't insist on the specified syntax.
1117 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1119 optionbyte |= (1 << 0);
1121 else /* REVISIT must be "HWWDG" then ... */
1123 optionbyte &= ~(1 << 0);
1126 /* OPT_RDRSTSTDBY */
1127 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1129 optionbyte |= (1 << 1);
1131 else /* REVISIT must be "RSTSTNDBY" then ... */
1133 optionbyte &= ~(1 << 1);
1137 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1139 optionbyte |= (1 << 2);
1141 else /* REVISIT must be "RSTSTOP" then ... */
1143 optionbyte &= ~(1 << 2);
1146 if (stm32x_erase_options(bank) != ERROR_OK)
1148 command_print(CMD_CTX, "stm32x failed to erase options");
1152 stm32x_info->option_bytes.user_options = optionbyte;
1154 if (stm32x_write_options(bank) != ERROR_OK)
1156 command_print(CMD_CTX, "stm32x failed to write options");
1160 command_print(CMD_CTX, "stm32x write options complete.\n"
1161 "INFO: a reset or power cycle is required "
1162 "for the new settings to take effect.");
1167 static int stm32x_mass_erase(struct flash_bank *bank)
1169 struct target *target = bank->target;
1172 if (target->state != TARGET_HALTED)
1174 LOG_ERROR("Target not halted");
1175 return ERROR_TARGET_NOT_HALTED;
1178 /* unlock option flash registers */
1179 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1180 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1182 /* mass erase flash memory */
1183 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1184 target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1186 status = stm32x_wait_status_busy(bank, 100);
1188 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1190 if (status & FLASH_WRPRTERR)
1192 LOG_ERROR("stm32x device protected");
1196 if (status & FLASH_PGERR)
1198 LOG_ERROR("stm32x device programming failed");
1205 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1211 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1215 struct flash_bank *bank;
1216 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1217 if (ERROR_OK != retval)
1220 if (stm32x_mass_erase(bank) == ERROR_OK)
1222 /* set all sectors as erased */
1223 for (i = 0; i < bank->num_sectors; i++)
1225 bank->sectors[i].is_erased = 1;
1228 command_print(CMD_CTX, "stm32x mass erase complete");
1232 command_print(CMD_CTX, "stm32x mass erase failed");
1238 static const struct command_registration stm32x_exec_command_handlers[] = {
1241 .handler = stm32x_handle_lock_command,
1242 .mode = COMMAND_EXEC,
1244 .help = "Lock entire flash device.",
1248 .handler = stm32x_handle_unlock_command,
1249 .mode = COMMAND_EXEC,
1251 .help = "Unlock entire protected flash device.",
1254 .name = "mass_erase",
1255 .handler = stm32x_handle_mass_erase_command,
1256 .mode = COMMAND_EXEC,
1258 .help = "Erase entire flash device.",
1261 .name = "options_read",
1262 .handler = stm32x_handle_options_read_command,
1263 .mode = COMMAND_EXEC,
1265 .help = "Read and display device option byte.",
1268 .name = "options_write",
1269 .handler = stm32x_handle_options_write_command,
1270 .mode = COMMAND_EXEC,
1271 .usage = "bank_id ('SWWDG'|'HWWDG') "
1272 "('RSTSTNDBY'|'NORSTSTNDBY') "
1273 "('RSTSTOP'|'NORSTSTOP')",
1274 .help = "Replace bits in device option byte.",
1276 COMMAND_REGISTRATION_DONE
1279 static const struct command_registration stm32x_command_handlers[] = {
1282 .mode = COMMAND_ANY,
1283 .help = "stm32x flash command group",
1284 .chain = stm32x_exec_command_handlers,
1286 COMMAND_REGISTRATION_DONE
1289 struct flash_driver stm32x_flash = {
1291 .commands = stm32x_command_handlers,
1292 .flash_bank_command = stm32x_flash_bank_command,
1293 .erase = stm32x_erase,
1294 .protect = stm32x_protect,
1295 .write = stm32x_write,
1296 .probe = stm32x_probe,
1297 .auto_probe = stm32x_auto_probe,
1298 .erase_check = default_flash_mem_blank_check,
1299 .protect_check = stm32x_protect_check,
1300 .info = stm32x_info,