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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "stm32x.h"
  28 #include "armv7m.h"
  29 #include <helper/binarybuffer.h>
  30 #include <target/algorithm.h>
  31
  32
  33 static int stm32x_mass_erase(struct flash_bank *bank);
  34
  35 /* flash bank stm32x <base> <size> 0 0 <target#>
  36  */
  37 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
  38 {
  39         struct stm32x_flash_bank *stm32x_info;
  40
  41         if (CMD_ARGC < 6)
  42         {
  43                 LOG_WARNING("incomplete flash_bank stm32x configuration");
  44                 return ERROR_FLASH_BANK_INVALID;
  45         }
  46
  47         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
  48         bank->driver_priv = stm32x_info;
  49
  50         stm32x_info->write_algorithm = NULL;
  51         stm32x_info->probed = 0;
  52
  53         return ERROR_OK;
  54 }
  55
  56 static uint32_t stm32x_get_flash_status(struct flash_bank *bank)
  57 {
  58         struct target *target = bank->target;
  59         uint32_t status;
  60
  61         target_read_u32(target, STM32_FLASH_SR, &status);
  62
  63         return status;
  64 }
  65
  66 static uint32_t stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
  67 {
  68         struct target *target = bank->target;
  69         uint32_t status;
  70
  71         /* wait for busy to clear */
  72         while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
  73         {
  74                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
  75                 alive_sleep(1);
  76         }
  77         /* Clear but report errors */
  78         if (status & (FLASH_WRPRTERR | FLASH_PGERR))
  79         {
  80                 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
  81         }
  82         return status;
  83 }
  84
  85 static int stm32x_read_options(struct flash_bank *bank)
  86 {
  87         uint32_t optiondata;
  88         struct stm32x_flash_bank *stm32x_info = NULL;
  89         struct target *target = bank->target;
  90
  91         stm32x_info = bank->driver_priv;
  92
  93         /* read current option bytes */
  94         target_read_u32(target, STM32_FLASH_OBR, &optiondata);
  95
  96         stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
  97         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
  98
  99         if (optiondata & (1 << OPT_READOUT))
 100                 LOG_INFO("Device Security Bit Set");
 101
 102         /* each bit refers to a 4bank protection */
 103         target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
 104
 105         stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
 106         stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
 107         stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
 108         stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
 109
 110         return ERROR_OK;
 111 }
 112
 113 static int stm32x_erase_options(struct flash_bank *bank)
 114 {
 115         struct stm32x_flash_bank *stm32x_info = NULL;
 116         struct target *target = bank->target;
 117         uint32_t status;
 118
 119         stm32x_info = bank->driver_priv;
 120
 121         /* read current options */
 122         stm32x_read_options(bank);
 123
 124         /* unlock flash registers */
 125         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 126         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 127
 128         /* unlock option flash registers */
 129         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 130         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 131
 132         /* erase option bytes */
 133         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
 134         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 135
 136         status = stm32x_wait_status_busy(bank, 10);
 137
 138         if (status & FLASH_WRPRTERR)
 139                 return ERROR_FLASH_OPERATION_FAILED;
 140         if (status & FLASH_PGERR)
 141                 return ERROR_FLASH_OPERATION_FAILED;
 142
 143         /* clear readout protection and complementary option bytes
 144          * this will also force a device unlock if set */
 145         stm32x_info->option_bytes.RDP = 0x5AA5;
 146
 147         return ERROR_OK;
 148 }
 149
 150 static int stm32x_write_options(struct flash_bank *bank)
 151 {
 152         struct stm32x_flash_bank *stm32x_info = NULL;
 153         struct target *target = bank->target;
 154         uint32_t status;
 155
 156         stm32x_info = bank->driver_priv;
 157
 158         /* unlock flash registers */
 159         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 160         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 161
 162         /* unlock option flash registers */
 163         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 164         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 165
 166         /* program option bytes */
 167         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
 168
 169         /* write user option byte */
 170         target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
 171
 172         status = stm32x_wait_status_busy(bank, 10);
 173
 174         if (status & FLASH_WRPRTERR)
 175                 return ERROR_FLASH_OPERATION_FAILED;
 176         if (status & FLASH_PGERR)
 177                 return ERROR_FLASH_OPERATION_FAILED;
 178
 179         /* write protection byte 1 */
 180         target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
 181
 182         status = stm32x_wait_status_busy(bank, 10);
 183
 184         if (status & FLASH_WRPRTERR)
 185                 return ERROR_FLASH_OPERATION_FAILED;
 186         if (status & FLASH_PGERR)
 187                 return ERROR_FLASH_OPERATION_FAILED;
 188
 189         /* write protection byte 2 */
 190         target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
 191
 192         status = stm32x_wait_status_busy(bank, 10);
 193
 194         if (status & FLASH_WRPRTERR)
 195                 return ERROR_FLASH_OPERATION_FAILED;
 196         if (status & FLASH_PGERR)
 197                 return ERROR_FLASH_OPERATION_FAILED;
 198
 199         /* write protection byte 3 */
 200         target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
 201
 202         status = stm32x_wait_status_busy(bank, 10);
 203
 204         if (status & FLASH_WRPRTERR)
 205                 return ERROR_FLASH_OPERATION_FAILED;
 206         if (status & FLASH_PGERR)
 207                 return ERROR_FLASH_OPERATION_FAILED;
 208
 209         /* write protection byte 4 */
 210         target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
 211
 212         status = stm32x_wait_status_busy(bank, 10);
 213
 214         if (status & FLASH_WRPRTERR)
 215                 return ERROR_FLASH_OPERATION_FAILED;
 216         if (status & FLASH_PGERR)
 217                 return ERROR_FLASH_OPERATION_FAILED;
 218
 219         /* write readout protection bit */
 220         target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
 221
 222         status = stm32x_wait_status_busy(bank, 10);
 223
 224         if (status & FLASH_WRPRTERR)
 225                 return ERROR_FLASH_OPERATION_FAILED;
 226         if (status & FLASH_PGERR)
 227                 return ERROR_FLASH_OPERATION_FAILED;
 228
 229         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 230
 231         return ERROR_OK;
 232 }
 233
 234 static int stm32x_protect_check(struct flash_bank *bank)
 235 {
 236         struct target *target = bank->target;
 237         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 238
 239         uint32_t protection;
 240         int i, s;
 241         int num_bits;
 242         int set;
 243
 244         if (target->state != TARGET_HALTED)
 245         {
 246                 LOG_ERROR("Target not halted");
 247                 return ERROR_TARGET_NOT_HALTED;
 248         }
 249
 250         /* medium density - each bit refers to a 4bank protection
 251          * high density - each bit refers to a 2bank protection */
 252         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 253
 254         /* medium density - each protection bit is for 4 * 1K pages
 255          * high density - each protection bit is for 2 * 2K pages */
 256         num_bits = (bank->num_sectors / stm32x_info->ppage_size);
 257
 258         if (stm32x_info->ppage_size == 2)
 259         {
 260                 /* high density flash/connectivity line protection */
 261
 262                 set = 1;
 263
 264                 if (protection & (1 << 31))
 265                         set = 0;
 266
 267                 /* bit 31 controls sector 62 - 255 protection for high density
 268                  * bit 31 controls sector 62 - 127 protection for connectivity line */
 269                 for (s = 62; s < bank->num_sectors; s++)
 270                 {
 271                         bank->sectors[s].is_protected = set;
 272                 }
 273
 274                 if (bank->num_sectors > 61)
 275                         num_bits = 31;
 276
 277                 for (i = 0; i < num_bits; i++)
 278                 {
 279                         set = 1;
 280
 281                         if (protection & (1 << i))
 282                                 set = 0;
 283
 284                         for (s = 0; s < stm32x_info->ppage_size; s++)
 285                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 286                 }
 287         }
 288         else
 289         {
 290                 /* low/medium density flash protection */
 291                 for (i = 0; i < num_bits; i++)
 292                 {
 293                         set = 1;
 294
 295                         if (protection & (1 << i))
 296                                 set = 0;
 297
 298                         for (s = 0; s < stm32x_info->ppage_size; s++)
 299                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 300                 }
 301         }
 302
 303         return ERROR_OK;
 304 }
 305
 306 static int stm32x_erase(struct flash_bank *bank, int first, int last)
 307 {
 308         struct target *target = bank->target;
 309         int i;
 310         uint32_t status;
 311
 312         if (bank->target->state != TARGET_HALTED)
 313         {
 314                 LOG_ERROR("Target not halted");
 315                 return ERROR_TARGET_NOT_HALTED;
 316         }
 317
 318         if ((first == 0) && (last == (bank->num_sectors - 1)))
 319         {
 320                 return stm32x_mass_erase(bank);
 321         }
 322
 323         /* unlock flash registers */
 324         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 325         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 326
 327         for (i = first; i <= last; i++)
 328         {
 329                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
 330                 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
 331                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
 332
 333                 status = stm32x_wait_status_busy(bank, 10);
 334
 335                 if (status & FLASH_WRPRTERR)
 336                         return ERROR_FLASH_OPERATION_FAILED;
 337                 if (status & FLASH_PGERR)
 338                         return ERROR_FLASH_OPERATION_FAILED;
 339                 bank->sectors[i].is_erased = 1;
 340         }
 341
 342         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 343
 344         return ERROR_OK;
 345 }
 346
 347 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
 348 {
 349         struct stm32x_flash_bank *stm32x_info = NULL;
 350         struct target *target = bank->target;
 351         uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 352         int i, reg, bit;
 353         int status;
 354         uint32_t protection;
 355
 356         stm32x_info = bank->driver_priv;
 357
 358         if (target->state != TARGET_HALTED)
 359         {
 360                 LOG_ERROR("Target not halted");
 361                 return ERROR_TARGET_NOT_HALTED;
 362         }
 363
 364         if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
 365         {
 366                 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary", stm32x_info->ppage_size);
 367                 return ERROR_FLASH_SECTOR_INVALID;
 368         }
 369
 370         /* medium density - each bit refers to a 4bank protection
 371          * high density - each bit refers to a 2bank protection */
 372         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 373
 374         prot_reg[0] = (uint16_t)protection;
 375         prot_reg[1] = (uint16_t)(protection >> 8);
 376         prot_reg[2] = (uint16_t)(protection >> 16);
 377         prot_reg[3] = (uint16_t)(protection >> 24);
 378
 379         if (stm32x_info->ppage_size == 2)
 380         {
 381                 /* high density flash */
 382
 383                 /* bit 7 controls sector 62 - 255 protection */
 384                 if (last > 61)
 385                 {
 386                         if (set)
 387                                 prot_reg[3] &= ~(1 << 7);
 388                         else
 389                                 prot_reg[3] |= (1 << 7);
 390                 }
 391
 392                 if (first > 61)
 393                         first = 62;
 394                 if (last > 61)
 395                         last = 61;
 396
 397                 for (i = first; i <= last; i++)
 398                 {
 399                         reg = (i / stm32x_info->ppage_size) / 8;
 400                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 401
 402                         if (set)
 403                                 prot_reg[reg] &= ~(1 << bit);
 404                         else
 405                                 prot_reg[reg] |= (1 << bit);
 406                 }
 407         }
 408         else
 409         {
 410                 /* medium density flash */
 411                 for (i = first; i <= last; i++)
 412                 {
 413                         reg = (i / stm32x_info->ppage_size) / 8;
 414                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 415
 416                         if (set)
 417                                 prot_reg[reg] &= ~(1 << bit);
 418                         else
 419                                 prot_reg[reg] |= (1 << bit);
 420                 }
 421         }
 422
 423         if ((status = stm32x_erase_options(bank)) != ERROR_OK)
 424                 return status;
 425
 426         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 427         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 428         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 429         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 430
 431         return stm32x_write_options(bank);
 432 }
 433
 434 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
 435 {
 436         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 437         struct target *target = bank->target;
 438         uint32_t buffer_size = 16384;
 439         struct working_area *source;
 440         uint32_t address = bank->base + offset;
 441         struct reg_param reg_params[4];
 442         struct armv7m_algorithm armv7m_info;
 443         int retval = ERROR_OK;
 444
 445         uint8_t stm32x_flash_write_code[] = {
 446                                                                         /* write: */
 447                 0xDF, 0xF8, 0x24, 0x40,         /* ldr  r4, STM32_FLASH_CR */
 448                 0x09, 0x4D,                                     /* ldr  r5, STM32_FLASH_SR */
 449                 0x4F, 0xF0, 0x01, 0x03,         /* mov  r3, #1 */
 450                 0x23, 0x60,                                     /* str  r3, [r4, #0] */
 451                 0x30, 0xF8, 0x02, 0x3B,         /* ldrh r3, [r0], #2 */
 452                 0x21, 0xF8, 0x02, 0x3B,         /* strh r3, [r1], #2 */
 453                                                                         /* busy: */
 454                 0x2B, 0x68,                                     /* ldr  r3, [r5, #0] */
 455                 0x13, 0xF0, 0x01, 0x0F,         /* tst  r3, #0x01 */
 456                 0xFB, 0xD0,                                     /* beq  busy */
 457                 0x13, 0xF0, 0x14, 0x0F,         /* tst  r3, #0x14 */
 458                 0x01, 0xD1,                                     /* bne  exit */
 459                 0x01, 0x3A,                                     /* subs r2, r2, #1 */
 460                 0xED, 0xD1,                                     /* bne  write */
 461                                                                         /* exit: */
 462                 0xFE, 0xE7,                                     /* b exit */
 463                 0x10, 0x20, 0x02, 0x40,         /* STM32_FLASH_CR:      .word 0x40022010 */
 464                 0x0C, 0x20, 0x02, 0x40          /* STM32_FLASH_SR:      .word 0x4002200C */
 465         };
 466
 467         /* flash write code */
 468         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
 469         {
 470                 LOG_WARNING("no working area available, can't do block memory writes");
 471                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 472         };
 473
 474         if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK)
 475                 return retval;
 476
 477         /* memory buffer */
 478         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
 479         {
 480                 buffer_size /= 2;
 481                 if (buffer_size <= 256)
 482                 {
 483                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
 484                         if (stm32x_info->write_algorithm)
 485                                 target_free_working_area(target, stm32x_info->write_algorithm);
 486
 487                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 488                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 489                 }
 490         };
 491
 492         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 493         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 494
 495         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 496         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 497         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 498         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
 499
 500         while (count > 0)
 501         {
 502                 uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
 503
 504                 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer)) != ERROR_OK)
 505                         break;
 506
 507                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 508                 buf_set_u32(reg_params[1].value, 0, 32, address);
 509                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
 510
 511                 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
 512                                 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
 513                 {
 514                         LOG_ERROR("error executing stm32x flash write algorithm");
 515                         retval = ERROR_FLASH_OPERATION_FAILED;
 516                         break;
 517                 }
 518
 519                 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
 520                 {
 521                         LOG_ERROR("flash memory not erased before writing");
 522                         /* Clear but report errors */
 523                         target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
 524                         retval = ERROR_FLASH_OPERATION_FAILED;
 525                         break;
 526                 }
 527
 528                 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
 529                 {
 530                         LOG_ERROR("flash memory write protected");
 531                         /* Clear but report errors */
 532                         target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
 533                         retval = ERROR_FLASH_OPERATION_FAILED;
 534                         break;
 535                 }
 536
 537                 buffer += thisrun_count * 2;
 538                 address += thisrun_count * 2;
 539                 count -= thisrun_count;
 540         }
 541
 542         target_free_working_area(target, source);
 543         target_free_working_area(target, stm32x_info->write_algorithm);
 544
 545         destroy_reg_param(&reg_params[0]);
 546         destroy_reg_param(&reg_params[1]);
 547         destroy_reg_param(&reg_params[2]);
 548         destroy_reg_param(&reg_params[3]);
 549
 550         return retval;
 551 }
 552
 553 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
 554 {
 555         struct target *target = bank->target;
 556         uint32_t words_remaining = (count / 2);
 557         uint32_t bytes_remaining = (count & 0x00000001);
 558         uint32_t address = bank->base + offset;
 559         uint32_t bytes_written = 0;
 560         uint8_t status;
 561         int retval;
 562
 563         if (bank->target->state != TARGET_HALTED)
 564         {
 565                 LOG_ERROR("Target not halted");
 566                 return ERROR_TARGET_NOT_HALTED;
 567         }
 568
 569         if (offset & 0x1)
 570         {
 571                 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 572                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 573         }
 574
 575         /* unlock flash registers */
 576         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 577         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 578
 579         /* multiple half words (2-byte) to be programmed? */
 580         if (words_remaining > 0)
 581         {
 582                 /* try using a block write */
 583                 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
 584                 {
 585                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 586                         {
 587                                 /* if block write failed (no sufficient working area),
 588                                  * we use normal (slow) single dword accesses */
 589                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 590                         }
 591                         else if (retval == ERROR_FLASH_OPERATION_FAILED)
 592                         {
 593                                 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
 594                                 return ERROR_FLASH_OPERATION_FAILED;
 595                         }
 596                 }
 597                 else
 598                 {
 599                         buffer += words_remaining * 2;
 600                         address += words_remaining * 2;
 601                         words_remaining = 0;
 602                 }
 603         }
 604
 605         while (words_remaining > 0)
 606         {
 607                 uint16_t value;
 608                 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
 609
 610                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 611                 target_write_u16(target, address, value);
 612
 613                 status = stm32x_wait_status_busy(bank, 5);
 614
 615                 if (status & FLASH_WRPRTERR)
 616                 {
 617                         LOG_ERROR("flash memory not erased before writing");
 618                         return ERROR_FLASH_OPERATION_FAILED;
 619                 }
 620                 if (status & FLASH_PGERR)
 621                 {
 622                         LOG_ERROR("flash memory write protected");
 623                         return ERROR_FLASH_OPERATION_FAILED;
 624                 }
 625
 626                 bytes_written += 2;
 627                 words_remaining--;
 628                 address += 2;
 629         }
 630
 631         if (bytes_remaining)
 632         {
 633                 uint16_t value = 0xffff;
 634                 memcpy(&value, buffer + bytes_written, bytes_remaining);
 635
 636                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 637                 target_write_u16(target, address, value);
 638
 639                 status = stm32x_wait_status_busy(bank, 5);
 640
 641                 if (status & FLASH_WRPRTERR)
 642                 {
 643                         LOG_ERROR("flash memory not erased before writing");
 644                         return ERROR_FLASH_OPERATION_FAILED;
 645                 }
 646                 if (status & FLASH_PGERR)
 647                 {
 648                         LOG_ERROR("flash memory write protected");
 649                         return ERROR_FLASH_OPERATION_FAILED;
 650                 }
 651         }
 652
 653         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 654
 655         return ERROR_OK;
 656 }
 657
 658 static int stm32x_probe(struct flash_bank *bank)
 659 {
 660         struct target *target = bank->target;
 661         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 662         int i;
 663         uint16_t num_pages;
 664         uint32_t device_id;
 665         int page_size;
 666
 667         if (bank->target->state != TARGET_HALTED)
 668         {
 669                 LOG_ERROR("Target not halted");
 670                 return ERROR_TARGET_NOT_HALTED;
 671         }
 672
 673         stm32x_info->probed = 0;
 674
 675         /* read stm32 device id register */
 676         target_read_u32(target, 0xE0042000, &device_id);
 677         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 678
 679         /* get flash size from target */
 680         if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
 681         {
 682                 /* failed reading flash size, default to max target family */
 683                 num_pages = 0xffff;
 684         }
 685
 686         if ((device_id & 0x7ff) == 0x410)
 687         {
 688                 /* medium density - we have 1k pages
 689                  * 4 pages for a protection area */
 690                 page_size = 1024;
 691                 stm32x_info->ppage_size = 4;
 692
 693                 /* check for early silicon */
 694                 if (num_pages == 0xffff)
 695                 {
 696                         /* number of sectors incorrect on revA */
 697                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
 698                         num_pages = 128;
 699                 }
 700         }
 701         else if ((device_id & 0x7ff) == 0x412)
 702         {
 703                 /* low density - we have 1k pages
 704                  * 4 pages for a protection area */
 705                 page_size = 1024;
 706                 stm32x_info->ppage_size = 4;
 707
 708                 /* check for early silicon */
 709                 if (num_pages == 0xffff)
 710                 {
 711                         /* number of sectors incorrect on revA */
 712                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
 713                         num_pages = 32;
 714                 }
 715         }
 716         else if ((device_id & 0x7ff) == 0x414)
 717         {
 718                 /* high density - we have 2k pages
 719                  * 2 pages for a protection area */
 720                 page_size = 2048;
 721                 stm32x_info->ppage_size = 2;
 722
 723                 /* check for early silicon */
 724                 if (num_pages == 0xffff)
 725                 {
 726                         /* number of sectors incorrect on revZ */
 727                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
 728                         num_pages = 512;
 729                 }
 730         }
 731         else if ((device_id & 0x7ff) == 0x418)
 732         {
 733                 /* connectivity line density - we have 2k pages
 734                  * 2 pages for a protection area */
 735                 page_size = 2048;
 736                 stm32x_info->ppage_size = 2;
 737
 738                 /* check for early silicon */
 739                 if (num_pages == 0xffff)
 740                 {
 741                         /* number of sectors incorrect on revZ */
 742                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
 743                         num_pages = 256;
 744                 }
 745         }
 746         else
 747         {
 748                 LOG_WARNING("Cannot identify target as a STM32 family.");
 749                 return ERROR_FLASH_OPERATION_FAILED;
 750         }
 751
 752         LOG_INFO("flash size = %dkbytes", num_pages);
 753
 754         /* calculate numbers of pages */
 755         num_pages /= (page_size / 1024);
 756
 757         bank->base = 0x08000000;
 758         bank->size = (num_pages * page_size);
 759         bank->num_sectors = num_pages;
 760         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
 761
 762         for (i = 0; i < num_pages; i++)
 763         {
 764                 bank->sectors[i].offset = i * page_size;
 765                 bank->sectors[i].size = page_size;
 766                 bank->sectors[i].is_erased = -1;
 767                 bank->sectors[i].is_protected = 1;
 768         }
 769
 770         stm32x_info->probed = 1;
 771
 772         return ERROR_OK;
 773 }
 774
 775 static int stm32x_auto_probe(struct flash_bank *bank)
 776 {
 777         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 778         if (stm32x_info->probed)
 779                 return ERROR_OK;
 780         return stm32x_probe(bank);
 781 }
 782
 783 #if 0
 784 COMMAND_HANDLER(stm32x_handle_part_id_command)
 785 {
 786         return ERROR_OK;
 787 }
 788 #endif
 789
 790 static int stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
 791 {
 792         struct target *target = bank->target;
 793         uint32_t device_id;
 794         int printed;
 795
 796         /* read stm32 device id register */
 797         target_read_u32(target, 0xE0042000, &device_id);
 798
 799         if ((device_id & 0x7ff) == 0x410)
 800         {
 801                 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
 802                 buf += printed;
 803                 buf_size -= printed;
 804
 805                 switch (device_id >> 16)
 806                 {
 807                         case 0x0000:
 808                                 snprintf(buf, buf_size, "A");
 809                                 break;
 810
 811                         case 0x2000:
 812                                 snprintf(buf, buf_size, "B");
 813                                 break;
 814
 815                         case 0x2001:
 816                                 snprintf(buf, buf_size, "Z");
 817                                 break;
 818
 819                         case 0x2003:
 820                                 snprintf(buf, buf_size, "Y");
 821                                 break;
 822
 823                         default:
 824                                 snprintf(buf, buf_size, "unknown");
 825                                 break;
 826                 }
 827         }
 828         else if ((device_id & 0x7ff) == 0x412)
 829         {
 830                 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
 831                 buf += printed;
 832                 buf_size -= printed;
 833
 834                 switch (device_id >> 16)
 835                 {
 836                         case 0x1000:
 837                                 snprintf(buf, buf_size, "A");
 838                                 break;
 839
 840                         default:
 841                                 snprintf(buf, buf_size, "unknown");
 842                                 break;
 843                 }
 844         }
 845         else if ((device_id & 0x7ff) == 0x414)
 846         {
 847                 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
 848                 buf += printed;
 849                 buf_size -= printed;
 850
 851                 switch (device_id >> 16)
 852                 {
 853                         case 0x1000:
 854                                 snprintf(buf, buf_size, "A");
 855                                 break;
 856
 857                         case 0x1001:
 858                                 snprintf(buf, buf_size, "Z");
 859                                 break;
 860
 861                         default:
 862                                 snprintf(buf, buf_size, "unknown");
 863                                 break;
 864                 }
 865         }
 866         else if ((device_id & 0x7ff) == 0x418)
 867         {
 868                 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
 869                 buf += printed;
 870                 buf_size -= printed;
 871
 872                 switch (device_id >> 16)
 873                 {
 874                         case 0x1000:
 875                                 snprintf(buf, buf_size, "A");
 876                                 break;
 877
 878                         case 0x1001:
 879                                 snprintf(buf, buf_size, "Z");
 880                                 break;
 881
 882                         default:
 883                                 snprintf(buf, buf_size, "unknown");
 884                                 break;
 885                 }
 886         }
 887         else
 888         {
 889                 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
 890                 return ERROR_FLASH_OPERATION_FAILED;
 891         }
 892
 893         return ERROR_OK;
 894 }
 895
 896 COMMAND_HANDLER(stm32x_handle_lock_command)
 897 {
 898         struct target *target = NULL;
 899         struct stm32x_flash_bank *stm32x_info = NULL;
 900
 901         if (CMD_ARGC < 1)
 902         {
 903                 command_print(CMD_CTX, "stm32x lock <bank>");
 904                 return ERROR_OK;
 905         }
 906
 907         struct flash_bank *bank;
 908         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 909         if (ERROR_OK != retval)
 910                 return retval;
 911
 912         stm32x_info = bank->driver_priv;
 913
 914         target = bank->target;
 915
 916         if (target->state != TARGET_HALTED)
 917         {
 918                 LOG_ERROR("Target not halted");
 919                 return ERROR_TARGET_NOT_HALTED;
 920         }
 921
 922         if (stm32x_erase_options(bank) != ERROR_OK)
 923         {
 924                 command_print(CMD_CTX, "stm32x failed to erase options");
 925                 return ERROR_OK;
 926         }
 927
 928         /* set readout protection */
 929         stm32x_info->option_bytes.RDP = 0;
 930
 931         if (stm32x_write_options(bank) != ERROR_OK)
 932         {
 933                 command_print(CMD_CTX, "stm32x failed to lock device");
 934                 return ERROR_OK;
 935         }
 936
 937         command_print(CMD_CTX, "stm32x locked");
 938
 939         return ERROR_OK;
 940 }
 941
 942 COMMAND_HANDLER(stm32x_handle_unlock_command)
 943 {
 944         struct target *target = NULL;
 945         struct stm32x_flash_bank *stm32x_info = NULL;
 946
 947         if (CMD_ARGC < 1)
 948         {
 949                 command_print(CMD_CTX, "stm32x unlock <bank>");
 950                 return ERROR_OK;
 951         }
 952
 953         struct flash_bank *bank;
 954         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 955         if (ERROR_OK != retval)
 956                 return retval;
 957
 958         stm32x_info = bank->driver_priv;
 959
 960         target = bank->target;
 961
 962         if (target->state != TARGET_HALTED)
 963         {
 964                 LOG_ERROR("Target not halted");
 965                 return ERROR_TARGET_NOT_HALTED;
 966         }
 967
 968         if (stm32x_erase_options(bank) != ERROR_OK)
 969         {
 970                 command_print(CMD_CTX, "stm32x failed to unlock device");
 971                 return ERROR_OK;
 972         }
 973
 974         if (stm32x_write_options(bank) != ERROR_OK)
 975         {
 976                 command_print(CMD_CTX, "stm32x failed to lock device");
 977                 return ERROR_OK;
 978         }
 979
 980         command_print(CMD_CTX, "stm32x unlocked");
 981
 982         return ERROR_OK;
 983 }
 984
 985 COMMAND_HANDLER(stm32x_handle_options_read_command)
 986 {
 987         uint32_t optionbyte;
 988         struct target *target = NULL;
 989         struct stm32x_flash_bank *stm32x_info = NULL;
 990
 991         if (CMD_ARGC < 1)
 992         {
 993                 command_print(CMD_CTX, "stm32x options_read <bank>");
 994                 return ERROR_OK;
 995         }
 996
 997         struct flash_bank *bank;
 998         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 999         if (ERROR_OK != retval)
1000                 return retval;
1001
1002         stm32x_info = bank->driver_priv;
1003
1004         target = bank->target;
1005
1006         if (target->state != TARGET_HALTED)
1007         {
1008                 LOG_ERROR("Target not halted");
1009                 return ERROR_TARGET_NOT_HALTED;
1010         }
1011
1012         target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1013         command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1014
1015         if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1016                 command_print(CMD_CTX, "Option Byte Complement Error");
1017
1018         if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1019                 command_print(CMD_CTX, "Readout Protection On");
1020         else
1021                 command_print(CMD_CTX, "Readout Protection Off");
1022
1023         if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1024                 command_print(CMD_CTX, "Software Watchdog");
1025         else
1026                 command_print(CMD_CTX, "Hardware Watchdog");
1027
1028         if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1029                 command_print(CMD_CTX, "Stop: No reset generated");
1030         else
1031                 command_print(CMD_CTX, "Stop: Reset generated");
1032
1033         if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1034                 command_print(CMD_CTX, "Standby: No reset generated");
1035         else
1036                 command_print(CMD_CTX, "Standby: Reset generated");
1037
1038         return ERROR_OK;
1039 }
1040
1041 COMMAND_HANDLER(stm32x_handle_options_write_command)
1042 {
1043         struct target *target = NULL;
1044         struct stm32x_flash_bank *stm32x_info = NULL;
1045         uint16_t optionbyte = 0xF8;
1046
1047         if (CMD_ARGC < 4)
1048         {
1049                 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1050                 return ERROR_OK;
1051         }
1052
1053         struct flash_bank *bank;
1054         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1055         if (ERROR_OK != retval)
1056                 return retval;
1057
1058         stm32x_info = bank->driver_priv;
1059
1060         target = bank->target;
1061
1062         if (target->state != TARGET_HALTED)
1063         {
1064                 LOG_ERROR("Target not halted");
1065                 return ERROR_TARGET_NOT_HALTED;
1066         }
1067
1068         if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1069         {
1070                 optionbyte |= (1 << 0);
1071         }
1072         else
1073         {
1074                 optionbyte &= ~(1 << 0);
1075         }
1076
1077         if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1078         {
1079                 optionbyte |= (1 << 1);
1080         }
1081         else
1082         {
1083                 optionbyte &= ~(1 << 1);
1084         }
1085
1086         if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1087         {
1088                 optionbyte |= (1 << 2);
1089         }
1090         else
1091         {
1092                 optionbyte &= ~(1 << 2);
1093         }
1094
1095         if (stm32x_erase_options(bank) != ERROR_OK)
1096         {
1097                 command_print(CMD_CTX, "stm32x failed to erase options");
1098                 return ERROR_OK;
1099         }
1100
1101         stm32x_info->option_bytes.user_options = optionbyte;
1102
1103         if (stm32x_write_options(bank) != ERROR_OK)
1104         {
1105                 command_print(CMD_CTX, "stm32x failed to write options");
1106                 return ERROR_OK;
1107         }
1108
1109         command_print(CMD_CTX, "stm32x write options complete");
1110
1111         return ERROR_OK;
1112 }
1113
1114 static int stm32x_mass_erase(struct flash_bank *bank)
1115 {
1116         struct target *target = bank->target;
1117         uint32_t status;
1118
1119         if (target->state != TARGET_HALTED)
1120         {
1121                 LOG_ERROR("Target not halted");
1122                 return ERROR_TARGET_NOT_HALTED;
1123         }
1124
1125         /* unlock option flash registers */
1126         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1127         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1128
1129         /* mass erase flash memory */
1130         target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1131         target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1132
1133         status = stm32x_wait_status_busy(bank, 10);
1134
1135         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1136
1137         if (status & FLASH_WRPRTERR)
1138         {
1139                 LOG_ERROR("stm32x device protected");
1140                 return ERROR_OK;
1141         }
1142
1143         if (status & FLASH_PGERR)
1144         {
1145                 LOG_ERROR("stm32x device programming failed");
1146                 return ERROR_OK;
1147         }
1148
1149         return ERROR_OK;
1150 }
1151
1152 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1153 {
1154         int i;
1155
1156         if (CMD_ARGC < 1)
1157         {
1158                 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1159                 return ERROR_OK;
1160         }
1161
1162         struct flash_bank *bank;
1163         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1164         if (ERROR_OK != retval)
1165                 return retval;
1166
1167         if (stm32x_mass_erase(bank) == ERROR_OK)
1168         {
1169                 /* set all sectors as erased */
1170                 for (i = 0; i < bank->num_sectors; i++)
1171                 {
1172                         bank->sectors[i].is_erased = 1;
1173                 }
1174
1175                 command_print(CMD_CTX, "stm32x mass erase complete");
1176         }
1177         else
1178         {
1179                 command_print(CMD_CTX, "stm32x mass erase failed");
1180         }
1181
1182         return ERROR_OK;
1183 }
1184
1185 static const struct command_registration stm32x_exec_command_handlers[] = {
1186         {
1187                 .name = "lock",
1188                 .handler = &stm32x_handle_lock_command,
1189                 .mode = COMMAND_EXEC,
1190                 .help = "lock device",
1191         },
1192         {
1193                 .name = "unlock",
1194                 .handler = &stm32x_handle_unlock_command,
1195                 .mode = COMMAND_EXEC,
1196                 .help = "unlock protected device",
1197         },
1198         {
1199                 .name = "mass_erase",
1200                 .handler = &stm32x_handle_mass_erase_command,
1201                 .mode = COMMAND_EXEC,
1202                 .help = "mass erase device",
1203         },
1204         {
1205                 .name = "options_read",
1206                 .handler = &stm32x_handle_options_read_command,
1207                 .mode = COMMAND_EXEC,
1208                 .help = "read device option bytes",
1209         },
1210         {
1211                 .name = "options_write",
1212                 .handler = &stm32x_handle_options_write_command,
1213                 .mode = COMMAND_EXEC,
1214                 .help = "write device option bytes",
1215         },
1216         COMMAND_REGISTRATION_DONE
1217 };
1218 static const struct command_registration stm32x_command_handlers[] = {
1219         {
1220                 .name = "stm32x",
1221                 .mode = COMMAND_ANY,
1222                 .help = "stm32x flash command group",
1223                 .chain = stm32x_exec_command_handlers,
1224         },
1225         COMMAND_REGISTRATION_DONE
1226 };
1227
1228 struct flash_driver stm32x_flash = {
1229                 .name = "stm32x",
1230                 .commands = stm32x_command_handlers,
1231                 .flash_bank_command = &stm32x_flash_bank_command,
1232                 .erase = &stm32x_erase,
1233                 .protect = &stm32x_protect,
1234                 .write = &stm32x_write,
1235                 .probe = &stm32x_probe,
1236                 .auto_probe = &stm32x_auto_probe,
1237                 .erase_check = &default_flash_mem_blank_check,
1238                 .protect_check = &stm32x_protect_check,
1239                 .info = &stm32x_info,
1240         };