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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Clement Burin des Roziers                       *
   9  *   clement.burin-des-roziers@hikob.com                                   *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  25  ***************************************************************************/
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "imp.h"
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34 #include <target/armv7m.h>
  35 #include <target/cortex_m.h>
  36
  37 /* stm32lx flash register locations */
  38
  39 #define FLASH_ACR               0x00
  40 #define FLASH_PECR              0x04
  41 #define FLASH_PDKEYR    0x08
  42 #define FLASH_PEKEYR    0x0C
  43 #define FLASH_PRGKEYR   0x10
  44 #define FLASH_OPTKEYR   0x14
  45 #define FLASH_SR                0x18
  46 #define FLASH_OBR               0x1C
  47 #define FLASH_WRPR              0x20
  48
  49 /* FLASH_ACR bites */
  50 #define FLASH_ACR__LATENCY              (1<<0)
  51 #define FLASH_ACR__PRFTEN               (1<<1)
  52 #define FLASH_ACR__ACC64                (1<<2)
  53 #define FLASH_ACR__SLEEP_PD             (1<<3)
  54 #define FLASH_ACR__RUN_PD               (1<<4)
  55
  56 /* FLASH_PECR bits */
  57 #define FLASH_PECR__PELOCK              (1<<0)
  58 #define FLASH_PECR__PRGLOCK             (1<<1)
  59 #define FLASH_PECR__OPTLOCK             (1<<2)
  60 #define FLASH_PECR__PROG                (1<<3)
  61 #define FLASH_PECR__DATA                (1<<4)
  62 #define FLASH_PECR__FTDW                (1<<8)
  63 #define FLASH_PECR__ERASE               (1<<9)
  64 #define FLASH_PECR__FPRG                (1<<10)
  65 #define FLASH_PECR__EOPIE               (1<<16)
  66 #define FLASH_PECR__ERRIE               (1<<17)
  67 #define FLASH_PECR__OBL_LAUNCH  (1<<18)
  68
  69 /* FLASH_SR bits */
  70 #define FLASH_SR__BSY           (1<<0)
  71 #define FLASH_SR__EOP           (1<<1)
  72 #define FLASH_SR__ENDHV         (1<<2)
  73 #define FLASH_SR__READY         (1<<3)
  74 #define FLASH_SR__WRPERR        (1<<8)
  75 #define FLASH_SR__PGAERR        (1<<9)
  76 #define FLASH_SR__SIZERR        (1<<10)
  77 #define FLASH_SR__OPTVERR       (1<<11)
  78
  79 /* Unlock keys */
  80 #define PEKEY1                  0x89ABCDEF
  81 #define PEKEY2                  0x02030405
  82 #define PRGKEY1                 0x8C9DAEBF
  83 #define PRGKEY2                 0x13141516
  84 #define OPTKEY1                 0xFBEAD9C8
  85 #define OPTKEY2                 0x24252627
  86
  87 /* other registers */
  88 #define DBGMCU_IDCODE           0xE0042000
  89 #define DBGMCU_IDCODE_L0        0x40015800
  90
  91 /* Constants */
  92 #define FLASH_SECTOR_SIZE 4096
  93 #define FLASH_BANK0_ADDRESS 0x08000000
  94
  95 /* option bytes */
  96 #define OPTION_BYTES_ADDRESS 0x1FF80000
  97
  98 #define OPTION_BYTE_0_PR1 0xFFFF0000
  99 #define OPTION_BYTE_0_PR0 0xFF5500AA
 100
 101 static int stm32lx_unlock_program_memory(struct flash_bank *bank);
 102 static int stm32lx_lock_program_memory(struct flash_bank *bank);
 103 static int stm32lx_enable_write_half_page(struct flash_bank *bank);
 104 static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
 105 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
 106 static int stm32lx_mass_erase(struct flash_bank *bank);
 107 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout);
 108
 109 struct stm32lx_rev {
 110         uint16_t rev;
 111         const char *str;
 112 };
 113
 114 struct stm32lx_part_info {
 115         uint16_t id;
 116         const char *device_str;
 117         const struct stm32lx_rev *revs;
 118         size_t num_revs;
 119         unsigned int page_size;
 120         unsigned int pages_per_sector;
 121         uint16_t max_flash_size_kb;
 122         uint16_t first_bank_size_kb; /* used when has_dual_banks is true */
 123         bool has_dual_banks;
 124
 125         uint32_t flash_base;    /* Flash controller registers location */
 126         uint32_t fsize_base;    /* Location of FSIZE register */
 127 };
 128
 129 struct stm32lx_flash_bank {
 130         int probed;
 131         uint32_t idcode;
 132         uint32_t user_bank_size;
 133         uint32_t flash_base;
 134
 135         const struct stm32lx_part_info *part_info;
 136 };
 137
 138 static const struct stm32lx_rev stm32_416_revs[] = {
 139         { 0x1000, "A" }, { 0x1008, "Y" }, { 0x1038, "W" }, { 0x1078, "V" },
 140 };
 141 static const struct stm32lx_rev stm32_417_revs[] = {
 142         { 0x1000, "A" }, { 0x1008, "Z" },
 143 };
 144 static const struct stm32lx_rev stm32_427_revs[] = {
 145         { 0x1000, "A" }, { 0x1018, "Y" }, { 0x1038, "X" },
 146 };
 147 static const struct stm32lx_rev stm32_429_revs[] = {
 148         { 0x1000, "A" }, { 0x1018, "Z" },
 149 };
 150 static const struct stm32lx_rev stm32_436_revs[] = {
 151         { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" },
 152 };
 153 static const struct stm32lx_rev stm32_437_revs[] = {
 154         { 0x1000, "A" },
 155 };
 156
 157 static const struct stm32lx_part_info stm32lx_parts[] = {
 158         {
 159                 .id                                     = 0x416,
 160                 .revs                           = stm32_416_revs,
 161                 .num_revs                       = ARRAY_SIZE(stm32_416_revs),
 162                 .device_str                     = "STM32L1xx (Cat.1 - Low/Medium Density)",
 163                 .page_size                      = 256,
 164                 .pages_per_sector       = 16,
 165                 .max_flash_size_kb      = 128,
 166                 .has_dual_banks         = false,
 167                 .flash_base                     = 0x40023C00,
 168                 .fsize_base                     = 0x1FF8004C,
 169         },
 170         {
 171                 .id                                     = 0x417,
 172                 .revs                           = stm32_417_revs,
 173                 .num_revs                       = ARRAY_SIZE(stm32_417_revs),
 174                 .device_str                     = "STM32L0xx",
 175                 .page_size                      = 128,
 176                 .pages_per_sector       = 32,
 177                 .max_flash_size_kb      = 64,
 178                 .has_dual_banks         = false,
 179                 .flash_base                     = 0x40022000,
 180                 .fsize_base                     = 0x1FF8007C,
 181         },
 182         {
 183                 .id                                     = 0x427,
 184                 .revs                           = stm32_427_revs,
 185                 .num_revs                       = ARRAY_SIZE(stm32_427_revs),
 186                 .device_str                     = "STM32L1xx (Cat.3 - Medium+ Density)",
 187                 .page_size                      = 256,
 188                 .pages_per_sector       = 16,
 189                 .max_flash_size_kb      = 256,
 190                 .first_bank_size_kb     = 192,
 191                 .has_dual_banks         = true,
 192                 .flash_base                     = 0x40023C00,
 193                 .fsize_base                     = 0x1FF800CC,
 194         },
 195         {
 196                 .id                                     = 0x429,
 197                 .revs                           = stm32_429_revs,
 198                 .num_revs                       = ARRAY_SIZE(stm32_429_revs),
 199                 .device_str                     = "STM32L1xx (Cat.2)",
 200                 .page_size                      = 256,
 201                 .pages_per_sector       = 16,
 202                 .max_flash_size_kb      = 128,
 203                 .has_dual_banks         = false,
 204                 .flash_base                     = 0x40023C00,
 205                 .fsize_base                     = 0x1FF8004C,
 206         },
 207         {
 208                 .id                                     = 0x436,
 209                 .revs                           = stm32_436_revs,
 210                 .num_revs                       = ARRAY_SIZE(stm32_436_revs),
 211                 .device_str                     = "STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)",
 212                 .page_size                      = 256,
 213                 .pages_per_sector       = 16,
 214                 .max_flash_size_kb      = 384,
 215                 .first_bank_size_kb     = 192,
 216                 .has_dual_banks         = true,
 217                 .flash_base                     = 0x40023C00,
 218                 .fsize_base                     = 0x1FF800CC,
 219         },
 220         {
 221                 .id                                     = 0x437,
 222                 .revs                           = stm32_437_revs,
 223                 .num_revs                       = ARRAY_SIZE(stm32_437_revs),
 224                 .device_str                     = "STM32L1xx (Cat.5/Cat.6)",
 225                 .page_size                      = 256,
 226                 .pages_per_sector       = 16,
 227                 .max_flash_size_kb      = 512,
 228                 .first_bank_size_kb     = 256,
 229                 .has_dual_banks         = true,
 230                 .flash_base                     = 0x40023C00,
 231                 .fsize_base                     = 0x1FF800CC,
 232         },
 233 };
 234
 235 /* flash bank stm32lx <base> <size> 0 0 <target#>
 236  */
 237 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
 238 {
 239         struct stm32lx_flash_bank *stm32lx_info;
 240         if (CMD_ARGC < 6)
 241                 return ERROR_COMMAND_SYNTAX_ERROR;
 242
 243         /* Create the bank structure */
 244         stm32lx_info = calloc(1, sizeof(*stm32lx_info));
 245
 246         /* Check allocation */
 247         if (stm32lx_info == NULL) {
 248                 LOG_ERROR("failed to allocate bank structure");
 249                 return ERROR_FAIL;
 250         }
 251
 252         bank->driver_priv = stm32lx_info;
 253
 254         stm32lx_info->probed = 0;
 255         stm32lx_info->user_bank_size = bank->size;
 256
 257         /* the stm32l erased value is 0x00 */
 258         bank->default_padded_value = 0x00;
 259
 260         return ERROR_OK;
 261 }
 262
 263 COMMAND_HANDLER(stm32lx_handle_mass_erase_command)
 264 {
 265         int i;
 266
 267         if (CMD_ARGC < 1)
 268                 return ERROR_COMMAND_SYNTAX_ERROR;
 269
 270         struct flash_bank *bank;
 271         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 272         if (ERROR_OK != retval)
 273                 return retval;
 274
 275         retval = stm32lx_mass_erase(bank);
 276         if (retval == ERROR_OK) {
 277                 /* set all sectors as erased */
 278                 for (i = 0; i < bank->num_sectors; i++)
 279                         bank->sectors[i].is_erased = 1;
 280
 281                 command_print(CMD_CTX, "stm32lx mass erase complete");
 282         } else {
 283                 command_print(CMD_CTX, "stm32lx mass erase failed");
 284         }
 285
 286         return retval;
 287 }
 288
 289 static int stm32lx_protect_check(struct flash_bank *bank)
 290 {
 291         int retval;
 292         struct target *target = bank->target;
 293         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 294
 295         uint32_t wrpr;
 296
 297         /*
 298          * Read the WRPR word, and check each bit (corresponding to each
 299          * flash sector
 300          */
 301         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_WRPR,
 302                         &wrpr);
 303         if (retval != ERROR_OK)
 304                 return retval;
 305
 306         for (int i = 0; i < bank->num_sectors; i++) {
 307                 if (wrpr & (1 << i))
 308                         bank->sectors[i].is_protected = 1;
 309                 else
 310                         bank->sectors[i].is_protected = 0;
 311         }
 312         return ERROR_OK;
 313 }
 314
 315 static int stm32lx_erase(struct flash_bank *bank, int first, int last)
 316 {
 317         int retval;
 318
 319         /*
 320          * It could be possible to do a mass erase if all sectors must be
 321          * erased, but it is not implemented yet.
 322          */
 323
 324         if (bank->target->state != TARGET_HALTED) {
 325                 LOG_ERROR("Target not halted");
 326                 return ERROR_TARGET_NOT_HALTED;
 327         }
 328
 329         /*
 330          * Loop over the selected sectors and erase them
 331          */
 332         for (int i = first; i <= last; i++) {
 333                 retval = stm32lx_erase_sector(bank, i);
 334                 if (retval != ERROR_OK)
 335                         return retval;
 336                 bank->sectors[i].is_erased = 1;
 337         }
 338         return ERROR_OK;
 339 }
 340
 341 static int stm32lx_protect(struct flash_bank *bank, int set, int first,
 342                 int last)
 343 {
 344         LOG_WARNING("protection of the STM32L flash is not implemented");
 345         return ERROR_OK;
 346 }
 347
 348 static int stm32lx_write_half_pages(struct flash_bank *bank, const uint8_t *buffer,
 349                 uint32_t offset, uint32_t count)
 350 {
 351         struct target *target = bank->target;
 352         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 353
 354         uint32_t hp_nb = stm32lx_info->part_info->page_size / 2;
 355         uint32_t buffer_size = 16384;
 356         struct working_area *write_algorithm;
 357         struct working_area *source;
 358         uint32_t address = bank->base + offset;
 359
 360         struct reg_param reg_params[3];
 361         struct armv7m_algorithm armv7m_info;
 362
 363         int retval = ERROR_OK;
 364
 365         /* see contib/loaders/flash/stm32lx.S for src */
 366
 367         static const uint8_t stm32lx_flash_write_code[] = {
 368                 /* write_word: */
 369                 0x00, 0x23,             /* movs r3, #0 */
 370                 0x04, 0xe0,             /* b test_done */
 371
 372                 /* write_word: */
 373                 0x51, 0xf8, 0x04, 0xcb, /* ldr ip, [r1], #4 */
 374                 0x40, 0xf8, 0x04, 0xcb, /* str ip, [r0], #4 */
 375                 0x01, 0x33,             /* adds r3, #1 */
 376
 377                 /* test_done: */
 378                 0x93, 0x42,             /* cmp r3, r2 */
 379                 0xf8, 0xd3,             /* bcc write_word */
 380                 0x00, 0xbe,             /* bkpt 0 */
 381         };
 382
 383         /* Make sure we're performing a half-page aligned write. */
 384         if (count % hp_nb) {
 385                 LOG_ERROR("The byte count must be %" PRIu32 "B-aligned but count is %" PRIi32 "B)", hp_nb, count);
 386                 return ERROR_FAIL;
 387         }
 388
 389         /* flash write code */
 390         if (target_alloc_working_area(target, sizeof(stm32lx_flash_write_code),
 391                         &write_algorithm) != ERROR_OK) {
 392                 LOG_DEBUG("no working area for block memory writes");
 393                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 394         };
 395
 396         /* Write the flashing code */
 397         retval = target_write_buffer(target,
 398                         write_algorithm->address,
 399                         sizeof(stm32lx_flash_write_code),
 400                         stm32lx_flash_write_code);
 401         if (retval != ERROR_OK) {
 402                 target_free_working_area(target, write_algorithm);
 403                 return retval;
 404         }
 405
 406         /* Allocate half pages memory */
 407         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 408                 if (buffer_size > 1024)
 409                         buffer_size -= 1024;
 410                 else
 411                         buffer_size /= 2;
 412
 413                 if (buffer_size <= stm32lx_info->part_info->page_size) {
 414                         /* we already allocated the writing code, but failed to get a
 415                          * buffer, free the algorithm */
 416                         target_free_working_area(target, write_algorithm);
 417
 418                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 419                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 420                 }
 421         }
 422
 423         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 424         armv7m_info.core_mode = ARM_MODE_THREAD;
 425         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 426         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 427         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 428
 429         /* Enable half-page write */
 430         retval = stm32lx_enable_write_half_page(bank);
 431         if (retval != ERROR_OK) {
 432                 target_free_working_area(target, source);
 433                 target_free_working_area(target, write_algorithm);
 434
 435                 destroy_reg_param(&reg_params[0]);
 436                 destroy_reg_param(&reg_params[1]);
 437                 destroy_reg_param(&reg_params[2]);
 438                 return retval;
 439         }
 440
 441         struct armv7m_common *armv7m = target_to_armv7m(target);
 442         if (armv7m == NULL) {
 443
 444                 /* something is very wrong if armv7m is NULL */
 445                 LOG_ERROR("unable to get armv7m target");
 446                 return retval;
 447         }
 448
 449         /* save any DEMCR flags and configure target to catch any Hard Faults */
 450         uint32_t demcr_save = armv7m->demcr;
 451         armv7m->demcr = VC_HARDERR;
 452
 453         /* Loop while there are bytes to write */
 454         while (count > 0) {
 455                 uint32_t this_count;
 456                 this_count = (count > buffer_size) ? buffer_size : count;
 457
 458                 /* Write the next half pages */
 459                 retval = target_write_buffer(target, source->address, this_count, buffer);
 460                 if (retval != ERROR_OK)
 461                         break;
 462
 463                 /* 4: Store useful information in the registers */
 464                 /* the destination address of the copy (R0) */
 465                 buf_set_u32(reg_params[0].value, 0, 32, address);
 466                 /* The source address of the copy (R1) */
 467                 buf_set_u32(reg_params[1].value, 0, 32, source->address);
 468                 /* The length of the copy (R2) */
 469                 buf_set_u32(reg_params[2].value, 0, 32, this_count / 4);
 470
 471                 /* 5: Execute the bunch of code */
 472                 retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params)
 473                                 / sizeof(*reg_params), reg_params,
 474                                 write_algorithm->address, 0, 10000, &armv7m_info);
 475                 if (retval != ERROR_OK)
 476                         break;
 477
 478                 /* check for Hard Fault */
 479                 if (armv7m->exception_number == 3)
 480                         break;
 481
 482                 /* 6: Wait while busy */
 483                 retval = stm32lx_wait_until_bsy_clear(bank);
 484                 if (retval != ERROR_OK)
 485                         break;
 486
 487                 buffer += this_count;
 488                 address += this_count;
 489                 count -= this_count;
 490         }
 491
 492         /* restore previous flags */
 493         armv7m->demcr = demcr_save;
 494
 495         if (armv7m->exception_number == 3) {
 496
 497                 /* the stm32l15x devices seem to have an issue when blank.
 498                  * if a ram loader is executed on a blank device it will
 499                  * Hard Fault, this issue does not happen for a already programmed device.
 500                  * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
 501                  * The workaround of handling the Hard Fault exception does work, but makes the
 502                  * loader more complicated, as a compromise we manually write the pages, programming time
 503                  * is reduced by 50% using this slower method.
 504                  */
 505
 506                 LOG_WARNING("couldn't use loader, falling back to page memory writes");
 507
 508                 while (count > 0) {
 509                         uint32_t this_count;
 510                         this_count = (count > hp_nb) ? hp_nb : count;
 511
 512                         /* Write the next half pages */
 513                         retval = target_write_buffer(target, address, this_count, buffer);
 514                         if (retval != ERROR_OK)
 515                                 break;
 516
 517                         /* Wait while busy */
 518                         retval = stm32lx_wait_until_bsy_clear(bank);
 519                         if (retval != ERROR_OK)
 520                                 break;
 521
 522                         buffer += this_count;
 523                         address += this_count;
 524                         count -= this_count;
 525                 }
 526         }
 527
 528         if (retval == ERROR_OK)
 529                 retval = stm32lx_lock_program_memory(bank);
 530
 531         target_free_working_area(target, source);
 532         target_free_working_area(target, write_algorithm);
 533
 534         destroy_reg_param(&reg_params[0]);
 535         destroy_reg_param(&reg_params[1]);
 536         destroy_reg_param(&reg_params[2]);
 537
 538         return retval;
 539 }
 540
 541 static int stm32lx_write(struct flash_bank *bank, const uint8_t *buffer,
 542                 uint32_t offset, uint32_t count)
 543 {
 544         struct target *target = bank->target;
 545         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 546
 547         uint32_t hp_nb = stm32lx_info->part_info->page_size / 2;
 548         uint32_t halfpages_number;
 549         uint32_t bytes_remaining = 0;
 550         uint32_t address = bank->base + offset;
 551         uint32_t bytes_written = 0;
 552         int retval, retval2;
 553
 554         if (bank->target->state != TARGET_HALTED) {
 555                 LOG_ERROR("Target not halted");
 556                 return ERROR_TARGET_NOT_HALTED;
 557         }
 558
 559         if (offset & 0x3) {
 560                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
 561                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 562         }
 563
 564         retval = stm32lx_unlock_program_memory(bank);
 565         if (retval != ERROR_OK)
 566                 return retval;
 567
 568         /* first we need to write any unaligned head bytes upto
 569          * the next 128 byte page */
 570
 571         if (offset % hp_nb)
 572                 bytes_remaining = MIN(count, hp_nb - (offset % hp_nb));
 573
 574         while (bytes_remaining > 0) {
 575                 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
 576
 577                 /* copy remaining bytes into the write buffer */
 578                 uint32_t bytes_to_write = MIN(4, bytes_remaining);
 579                 memcpy(value, buffer + bytes_written, bytes_to_write);
 580
 581                 retval = target_write_buffer(target, address, 4, value);
 582                 if (retval != ERROR_OK)
 583                         goto reset_pg_and_lock;
 584
 585                 bytes_written += bytes_to_write;
 586                 bytes_remaining -= bytes_to_write;
 587                 address += 4;
 588
 589                 retval = stm32lx_wait_until_bsy_clear(bank);
 590                 if (retval != ERROR_OK)
 591                         goto reset_pg_and_lock;
 592         }
 593
 594         offset += bytes_written;
 595         count -= bytes_written;
 596
 597         /* this should always pass this check here */
 598         assert((offset % hp_nb) == 0);
 599
 600         /* calculate half pages */
 601         halfpages_number = count / hp_nb;
 602
 603         if (halfpages_number) {
 604                 retval = stm32lx_write_half_pages(bank, buffer + bytes_written, offset, hp_nb * halfpages_number);
 605                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 606                         /* attempt slow memory writes */
 607                         LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 608                         halfpages_number = 0;
 609                 } else {
 610                         if (retval != ERROR_OK)
 611                                 return ERROR_FAIL;
 612                 }
 613         }
 614
 615         /* write any remaining bytes */
 616         uint32_t page_bytes_written = hp_nb * halfpages_number;
 617         bytes_written += page_bytes_written;
 618         address += page_bytes_written;
 619         bytes_remaining = count - page_bytes_written;
 620
 621         retval = stm32lx_unlock_program_memory(bank);
 622         if (retval != ERROR_OK)
 623                 return retval;
 624
 625         while (bytes_remaining > 0) {
 626                 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
 627
 628                 /* copy remaining bytes into the write buffer */
 629                 uint32_t bytes_to_write = MIN(4, bytes_remaining);
 630                 memcpy(value, buffer + bytes_written, bytes_to_write);
 631
 632                 retval = target_write_buffer(target, address, 4, value);
 633                 if (retval != ERROR_OK)
 634                         goto reset_pg_and_lock;
 635
 636                 bytes_written += bytes_to_write;
 637                 bytes_remaining -= bytes_to_write;
 638                 address += 4;
 639
 640                 retval = stm32lx_wait_until_bsy_clear(bank);
 641                 if (retval != ERROR_OK)
 642                         goto reset_pg_and_lock;
 643         }
 644
 645 reset_pg_and_lock:
 646         retval2 = stm32lx_lock_program_memory(bank);
 647         if (retval == ERROR_OK)
 648                 retval = retval2;
 649
 650         return retval;
 651 }
 652
 653 static int stm32lx_read_id_code(struct target *target, uint32_t *id)
 654 {
 655         /* read stm32 device id register */
 656         int retval = target_read_u32(target, DBGMCU_IDCODE, id);
 657         if (retval != ERROR_OK)
 658                 return retval;
 659
 660         /* STM32L0 parts will have 0 there, try reading the L0's location for
 661          * DBG_IDCODE in case this is an L0 part. */
 662         if (*id == 0)
 663                 retval = target_read_u32(target, DBGMCU_IDCODE_L0, id);
 664
 665         return retval;
 666 }
 667
 668 static int stm32lx_probe(struct flash_bank *bank)
 669 {
 670         struct target *target = bank->target;
 671         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 672         int i;
 673         uint16_t flash_size_in_kb;
 674         uint32_t device_id;
 675         uint32_t base_address = FLASH_BANK0_ADDRESS;
 676         uint32_t second_bank_base;
 677
 678         stm32lx_info->probed = 0;
 679         stm32lx_info->part_info = NULL;
 680
 681         int retval = stm32lx_read_id_code(bank->target, &device_id);
 682         if (retval != ERROR_OK)
 683                 return retval;
 684
 685         stm32lx_info->idcode = device_id;
 686
 687         LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
 688
 689         for (unsigned int n = 0; n < ARRAY_SIZE(stm32lx_parts); n++) {
 690                 if ((device_id & 0xfff) == stm32lx_parts[n].id)
 691                         stm32lx_info->part_info = &stm32lx_parts[n];
 692         }
 693
 694         if (!stm32lx_info->part_info) {
 695                 LOG_WARNING("Cannot identify target as a STM32L family.");
 696                 return ERROR_FAIL;
 697         }
 698
 699         stm32lx_info->flash_base = stm32lx_info->part_info->flash_base;
 700
 701         /* Get the flash size from target. */
 702         retval = target_read_u16(target, stm32lx_info->part_info->fsize_base,
 703                         &flash_size_in_kb);
 704
 705         /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
 706          * or 256K, respectively.  Please see RM0038 r8 or newer and refer to
 707          * section 30.1.1. */
 708         if (retval == ERROR_OK && (device_id & 0xfff) == 0x436) {
 709                 if (flash_size_in_kb == 0)
 710                         flash_size_in_kb = 384;
 711                 else if (flash_size_in_kb == 1)
 712                         flash_size_in_kb = 256;
 713         }
 714
 715         /* Failed reading flash size or flash size invalid (early silicon),
 716          * default to max target family */
 717         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 718                 LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
 719                         stm32lx_info->part_info->max_flash_size_kb);
 720                 flash_size_in_kb = stm32lx_info->part_info->max_flash_size_kb;
 721         } else if (flash_size_in_kb > stm32lx_info->part_info->max_flash_size_kb) {
 722                 LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
 723                         flash_size_in_kb, stm32lx_info->part_info->max_flash_size_kb,
 724                         stm32lx_info->part_info->max_flash_size_kb);
 725                 flash_size_in_kb = stm32lx_info->part_info->max_flash_size_kb;
 726         }
 727
 728         if (stm32lx_info->part_info->has_dual_banks) {
 729                 /* Use the configured base address to determine if this is the first or second flash bank.
 730                  * Verify that the base address is reasonably correct and determine the flash bank size
 731                  */
 732                 second_bank_base = base_address +
 733                         stm32lx_info->part_info->first_bank_size_kb * 1024;
 734                 if (bank->base == second_bank_base || !bank->base) {
 735                         /* This is the second bank  */
 736                         base_address = second_bank_base;
 737                         flash_size_in_kb = flash_size_in_kb -
 738                                 stm32lx_info->part_info->first_bank_size_kb;
 739                 } else if (bank->base == base_address) {
 740                         /* This is the first bank */
 741                         flash_size_in_kb = stm32lx_info->part_info->first_bank_size_kb;
 742                 } else {
 743                         LOG_WARNING("STM32L flash bank base address config is incorrect."
 744                                     " 0x%" PRIx32 " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
 745                                                 bank->base, base_address, second_bank_base);
 746                         return ERROR_FAIL;
 747                 }
 748                 LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32,
 749                                 bank->bank_number, flash_size_in_kb, base_address);
 750         } else {
 751                 LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
 752         }
 753
 754         /* if the user sets the size manually then ignore the probed value
 755          * this allows us to work around devices that have a invalid flash size register value */
 756         if (stm32lx_info->user_bank_size) {
 757                 flash_size_in_kb = stm32lx_info->user_bank_size / 1024;
 758                 LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb);
 759         }
 760
 761         /* calculate numbers of sectors (4kB per sector) */
 762         int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
 763
 764         if (bank->sectors) {
 765                 free(bank->sectors);
 766                 bank->sectors = NULL;
 767         }
 768
 769         bank->size = flash_size_in_kb * 1024;
 770         bank->base = base_address;
 771         bank->num_sectors = num_sectors;
 772         bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
 773         if (bank->sectors == NULL) {
 774                 LOG_ERROR("failed to allocate bank sectors");
 775                 return ERROR_FAIL;
 776         }
 777
 778         for (i = 0; i < num_sectors; i++) {
 779                 bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
 780                 bank->sectors[i].size = FLASH_SECTOR_SIZE;
 781                 bank->sectors[i].is_erased = -1;
 782                 bank->sectors[i].is_protected = 1;
 783         }
 784
 785         stm32lx_info->probed = 1;
 786
 787         return ERROR_OK;
 788 }
 789
 790 static int stm32lx_auto_probe(struct flash_bank *bank)
 791 {
 792         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 793
 794         if (stm32lx_info->probed)
 795                 return ERROR_OK;
 796
 797         return stm32lx_probe(bank);
 798 }
 799
 800 static int stm32lx_erase_check(struct flash_bank *bank)
 801 {
 802         struct target *target = bank->target;
 803         const int buffer_size = 4096;
 804         int i;
 805         uint32_t nBytes;
 806         int retval = ERROR_OK;
 807
 808         if (bank->target->state != TARGET_HALTED) {
 809                 LOG_ERROR("Target not halted");
 810                 return ERROR_TARGET_NOT_HALTED;
 811         }
 812
 813         uint8_t *buffer = malloc(buffer_size);
 814         if (buffer == NULL) {
 815                 LOG_ERROR("failed to allocate read buffer");
 816                 return ERROR_FAIL;
 817         }
 818
 819         for (i = 0; i < bank->num_sectors; i++) {
 820                 uint32_t j;
 821                 bank->sectors[i].is_erased = 1;
 822
 823                 /* Loop chunk by chunk over the sector */
 824                 for (j = 0; j < bank->sectors[i].size; j += buffer_size) {
 825                         uint32_t chunk;
 826                         chunk = buffer_size;
 827                         if (chunk > (j - bank->sectors[i].size))
 828                                 chunk = (j - bank->sectors[i].size);
 829
 830                         retval = target_read_memory(target, bank->base
 831                                         + bank->sectors[i].offset + j, 4, chunk / 4, buffer);
 832                         if (retval != ERROR_OK)
 833                                 break;
 834
 835                         for (nBytes = 0; nBytes < chunk; nBytes++) {
 836                                 if (buffer[nBytes] != 0x00) {
 837                                         bank->sectors[i].is_erased = 0;
 838                                         break;
 839                                 }
 840                         }
 841                 }
 842                 if (retval != ERROR_OK)
 843                         break;
 844         }
 845         free(buffer);
 846
 847         return retval;
 848 }
 849
 850 /* This method must return a string displaying information about the bank */
 851 static int stm32lx_get_info(struct flash_bank *bank, char *buf, int buf_size)
 852 {
 853         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 854
 855         if (!stm32lx_info->probed) {
 856                 int retval = stm32lx_probe(bank);
 857                 if (retval != ERROR_OK) {
 858                         snprintf(buf, buf_size,
 859                                 "Unable to find bank information.");
 860                         return retval;
 861                 }
 862         }
 863
 864         const struct stm32lx_part_info *info = stm32lx_info->part_info;
 865
 866         if (info) {
 867                 const char *rev_str = NULL;
 868                 uint16_t rev_id = stm32lx_info->idcode >> 16;
 869
 870                 for (unsigned int i = 0; i < info->num_revs; i++)
 871                         if (rev_id == info->revs[i].rev)
 872                                 rev_str = info->revs[i].str;
 873
 874                 if (rev_str != NULL) {
 875                         snprintf(buf, buf_size,
 876                                 "%s - Rev: %s",
 877                                 stm32lx_info->part_info->device_str, rev_str);
 878                 } else {
 879                         snprintf(buf, buf_size,
 880                                 "%s - Rev: unknown (0x%04x)",
 881                                 stm32lx_info->part_info->device_str, rev_id);
 882                 }
 883
 884                 return ERROR_OK;
 885         } else {
 886                 snprintf(buf, buf_size, "Cannot identify target as a STM32Lx");
 887
 888                 return ERROR_FAIL;
 889         }
 890 }
 891
 892 static const struct command_registration stm32lx_exec_command_handlers[] = {
 893         {
 894                 .name = "mass_erase",
 895                 .handler = stm32lx_handle_mass_erase_command,
 896                 .mode = COMMAND_EXEC,
 897                 .usage = "bank_id",
 898                 .help = "Erase entire flash device. including available EEPROM",
 899         },
 900         COMMAND_REGISTRATION_DONE
 901 };
 902
 903 static const struct command_registration stm32lx_command_handlers[] = {
 904         {
 905                 .name = "stm32lx",
 906                 .mode = COMMAND_ANY,
 907                 .help = "stm32lx flash command group",
 908                 .usage = "",
 909                 .chain = stm32lx_exec_command_handlers,
 910         },
 911         COMMAND_REGISTRATION_DONE
 912 };
 913
 914 struct flash_driver stm32lx_flash = {
 915                 .name = "stm32lx",
 916                 .commands = stm32lx_command_handlers,
 917                 .flash_bank_command = stm32lx_flash_bank_command,
 918                 .erase = stm32lx_erase,
 919                 .protect = stm32lx_protect,
 920                 .write = stm32lx_write,
 921                 .read = default_flash_read,
 922                 .probe = stm32lx_probe,
 923                 .auto_probe = stm32lx_auto_probe,
 924                 .erase_check = stm32lx_erase_check,
 925                 .protect_check = stm32lx_protect_check,
 926                 .info = stm32lx_get_info,
 927 };
 928
 929 /* Static methods implementation */
 930 static int stm32lx_unlock_program_memory(struct flash_bank *bank)
 931 {
 932         struct target *target = bank->target;
 933         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 934         int retval;
 935         uint32_t reg32;
 936
 937         /*
 938          * Unlocking the program memory is done by unlocking the PECR,
 939          * then by writing the 2 PRGKEY to the PRGKEYR register
 940          */
 941
 942         /* check flash is not already unlocked */
 943         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
 944                         &reg32);
 945         if (retval != ERROR_OK)
 946                 return retval;
 947
 948         if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
 949                 return ERROR_OK;
 950
 951         /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
 952         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
 953                         PEKEY1);
 954         if (retval != ERROR_OK)
 955                 return retval;
 956
 957         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
 958                         PEKEY2);
 959         if (retval != ERROR_OK)
 960                 return retval;
 961
 962         /* Make sure it worked */
 963         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
 964                         &reg32);
 965         if (retval != ERROR_OK)
 966                 return retval;
 967
 968         if (reg32 & FLASH_PECR__PELOCK) {
 969                 LOG_ERROR("PELOCK is not cleared :(");
 970                 return ERROR_FLASH_OPERATION_FAILED;
 971         }
 972
 973         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
 974                         PRGKEY1);
 975         if (retval != ERROR_OK)
 976                 return retval;
 977         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
 978                         PRGKEY2);
 979         if (retval != ERROR_OK)
 980                 return retval;
 981
 982         /* Make sure it worked */
 983         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
 984                         &reg32);
 985         if (retval != ERROR_OK)
 986                 return retval;
 987
 988         if (reg32 & FLASH_PECR__PRGLOCK) {
 989                 LOG_ERROR("PRGLOCK is not cleared :(");
 990                 return ERROR_FLASH_OPERATION_FAILED;
 991         }
 992
 993         return ERROR_OK;
 994 }
 995
 996 static int stm32lx_enable_write_half_page(struct flash_bank *bank)
 997 {
 998         struct target *target = bank->target;
 999         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1000         int retval;
1001         uint32_t reg32;
1002
1003         /**
1004          * Unlock the program memory, then set the FPRG bit in the PECR register.
1005          */
1006         retval = stm32lx_unlock_program_memory(bank);
1007         if (retval != ERROR_OK)
1008                 return retval;
1009
1010         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1011                         &reg32);
1012         if (retval != ERROR_OK)
1013                 return retval;
1014
1015         reg32 |= FLASH_PECR__FPRG;
1016         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1017                         reg32);
1018         if (retval != ERROR_OK)
1019                 return retval;
1020
1021         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1022                         &reg32);
1023         if (retval != ERROR_OK)
1024                 return retval;
1025
1026         reg32 |= FLASH_PECR__PROG;
1027         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1028                         reg32);
1029
1030         return retval;
1031 }
1032
1033 static int stm32lx_lock_program_memory(struct flash_bank *bank)
1034 {
1035         struct target *target = bank->target;
1036         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1037         int retval;
1038         uint32_t reg32;
1039
1040         /* To lock the program memory, simply set the lock bit and lock PECR */
1041
1042         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1043                         &reg32);
1044         if (retval != ERROR_OK)
1045                 return retval;
1046
1047         reg32 |= FLASH_PECR__PRGLOCK;
1048         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1049                         reg32);
1050         if (retval != ERROR_OK)
1051                 return retval;
1052
1053         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1054                         &reg32);
1055         if (retval != ERROR_OK)
1056                 return retval;
1057
1058         reg32 |= FLASH_PECR__PELOCK;
1059         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1060                         reg32);
1061         if (retval != ERROR_OK)
1062                 return retval;
1063
1064         return ERROR_OK;
1065 }
1066
1067 static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
1068 {
1069         struct target *target = bank->target;
1070         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1071         int retval;
1072         uint32_t reg32;
1073
1074         /*
1075          * To erase a sector (i.e. stm32lx_info->part_info.pages_per_sector pages),
1076          * first unlock the memory, loop over the pages of this sector
1077          * and write 0x0 to its first word.
1078          */
1079
1080         retval = stm32lx_unlock_program_memory(bank);
1081         if (retval != ERROR_OK)
1082                 return retval;
1083
1084         for (int page = 0; page < (int)stm32lx_info->part_info->pages_per_sector;
1085                         page++) {
1086                 reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
1087                 retval = target_write_u32(target,
1088                                 stm32lx_info->flash_base + FLASH_PECR, reg32);
1089                 if (retval != ERROR_OK)
1090                         return retval;
1091
1092                 retval = stm32lx_wait_until_bsy_clear(bank);
1093                 if (retval != ERROR_OK)
1094                         return retval;
1095
1096                 uint32_t addr = bank->base + bank->sectors[sector].offset + (page
1097                                 * stm32lx_info->part_info->page_size);
1098                 retval = target_write_u32(target, addr, 0x0);
1099                 if (retval != ERROR_OK)
1100                         return retval;
1101
1102                 retval = stm32lx_wait_until_bsy_clear(bank);
1103                 if (retval != ERROR_OK)
1104                         return retval;
1105         }
1106
1107         retval = stm32lx_lock_program_memory(bank);
1108         if (retval != ERROR_OK)
1109                 return retval;
1110
1111         return ERROR_OK;
1112 }
1113
1114 static inline int stm32lx_get_flash_status(struct flash_bank *bank, uint32_t *status)
1115 {
1116         struct target *target = bank->target;
1117         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1118
1119         return target_read_u32(target, stm32lx_info->flash_base + FLASH_SR, status);
1120 }
1121
1122 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
1123 {
1124         return stm32lx_wait_until_bsy_clear_timeout(bank, 100);
1125 }
1126
1127 static int stm32lx_unlock_options_bytes(struct flash_bank *bank)
1128 {
1129         struct target *target = bank->target;
1130         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1131         int retval;
1132         uint32_t reg32;
1133
1134         /*
1135         * Unlocking the options bytes is done by unlocking the PECR,
1136         * then by writing the 2 FLASH_PEKEYR to the FLASH_OPTKEYR register
1137         */
1138
1139         /* check flash is not already unlocked */
1140         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
1141         if (retval != ERROR_OK)
1142                 return retval;
1143
1144         if ((reg32 & FLASH_PECR__OPTLOCK) == 0)
1145                 return ERROR_OK;
1146
1147         if ((reg32 & FLASH_PECR__PELOCK) != 0) {
1148
1149                 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY1);
1150                 if (retval != ERROR_OK)
1151                         return retval;
1152
1153                 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY2);
1154                 if (retval != ERROR_OK)
1155                         return retval;
1156         }
1157
1158         /* To unlock the PECR write the 2 OPTKEY to the FLASH_OPTKEYR register */
1159         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY1);
1160         if (retval != ERROR_OK)
1161                 return retval;
1162
1163         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY2);
1164         if (retval != ERROR_OK)
1165                 return retval;
1166
1167         return ERROR_OK;
1168 }
1169
1170 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout)
1171 {
1172         struct target *target = bank->target;
1173         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1174         uint32_t status;
1175         int retval = ERROR_OK;
1176
1177         /* wait for busy to clear */
1178         for (;;) {
1179                 retval = stm32lx_get_flash_status(bank, &status);
1180                 if (retval != ERROR_OK)
1181                         return retval;
1182
1183                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
1184                 if ((status & FLASH_SR__BSY) == 0)
1185                         break;
1186
1187                 if (timeout-- <= 0) {
1188                         LOG_ERROR("timed out waiting for flash");
1189                         return ERROR_FAIL;
1190                 }
1191                 alive_sleep(1);
1192         }
1193
1194         if (status & FLASH_SR__WRPERR) {
1195                 LOG_ERROR("access denied / write protected");
1196                 retval = ERROR_FAIL;
1197         }
1198
1199         if (status & FLASH_SR__PGAERR) {
1200                 LOG_ERROR("invalid program address");
1201                 retval = ERROR_FAIL;
1202         }
1203
1204         /* Clear but report errors */
1205         if (status & FLASH_SR__OPTVERR) {
1206                 /* If this operation fails, we ignore it and report the original retval */
1207                 target_write_u32(target, stm32lx_info->flash_base + FLASH_SR, status & FLASH_SR__OPTVERR);
1208         }
1209
1210         return retval;
1211 }
1212
1213 static int stm32lx_obl_launch(struct flash_bank *bank)
1214 {
1215         struct target *target = bank->target;
1216         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1217         int retval;
1218
1219         /* This will fail as the target gets immediately rebooted */
1220         target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1221                          FLASH_PECR__OBL_LAUNCH);
1222
1223         size_t tries = 10;
1224         do {
1225                 target_halt(target);
1226                 retval = target_poll(target);
1227         } while (--tries > 0 &&
1228                  (retval != ERROR_OK || target->state != TARGET_HALTED));
1229
1230         return tries ? ERROR_OK : ERROR_FAIL;
1231 }
1232
1233 static int stm32lx_mass_erase(struct flash_bank *bank)
1234 {
1235         int retval;
1236         struct target *target = bank->target;
1237         struct stm32lx_flash_bank *stm32lx_info = NULL;
1238         uint32_t reg32;
1239
1240         if (target->state != TARGET_HALTED) {
1241                 LOG_ERROR("Target not halted");
1242                 return ERROR_TARGET_NOT_HALTED;
1243         }
1244
1245         stm32lx_info = bank->driver_priv;
1246
1247         retval = stm32lx_unlock_options_bytes(bank);
1248         if (retval != ERROR_OK)
1249                 return retval;
1250
1251         /* mass erase flash memory */
1252         /* set the RDP protection level to 1 */
1253         retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR1);
1254         if (retval != ERROR_OK)
1255                 return retval;
1256
1257         retval = stm32lx_obl_launch(bank);
1258         if (retval != ERROR_OK)
1259                 return retval;
1260
1261         retval = stm32lx_unlock_options_bytes(bank);
1262         if (retval != ERROR_OK)
1263                 return retval;
1264
1265         /* set the RDP protection level to 0 */
1266         retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR0);
1267         if (retval != ERROR_OK)
1268                 return retval;
1269
1270         retval = stm32lx_wait_until_bsy_clear_timeout(bank, 30000);
1271         if (retval != ERROR_OK)
1272                 return retval;
1273
1274         retval = stm32lx_obl_launch(bank);
1275         if (retval != ERROR_OK)
1276                 return retval;
1277
1278         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
1279         if (retval != ERROR_OK)
1280                 return retval;
1281
1282         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR, reg32 | FLASH_PECR__OPTLOCK);
1283         if (retval != ERROR_OK)
1284                 return retval;
1285
1286         return ERROR_OK;
1287 }