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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Clement Burin des Roziers                       *
   9  *   clement.burin-des-roziers@hikob.com                                   *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "imp.h"
  30 #include <helper/binarybuffer.h>
  31 #include <target/algorithm.h>
  32 #include <target/armv7m.h>
  33 #include <target/cortex_m.h>
  34
  35 /* stm32lx flash register locations */
  36
  37 #define FLASH_ACR               0x00
  38 #define FLASH_PECR              0x04
  39 #define FLASH_PDKEYR    0x08
  40 #define FLASH_PEKEYR    0x0C
  41 #define FLASH_PRGKEYR   0x10
  42 #define FLASH_OPTKEYR   0x14
  43 #define FLASH_SR                0x18
  44 #define FLASH_OBR               0x1C
  45 #define FLASH_WRPR              0x20
  46
  47 /* FLASH_ACR bites */
  48 #define FLASH_ACR__LATENCY              (1<<0)
  49 #define FLASH_ACR__PRFTEN               (1<<1)
  50 #define FLASH_ACR__ACC64                (1<<2)
  51 #define FLASH_ACR__SLEEP_PD             (1<<3)
  52 #define FLASH_ACR__RUN_PD               (1<<4)
  53
  54 /* FLASH_PECR bits */
  55 #define FLASH_PECR__PELOCK              (1<<0)
  56 #define FLASH_PECR__PRGLOCK             (1<<1)
  57 #define FLASH_PECR__OPTLOCK             (1<<2)
  58 #define FLASH_PECR__PROG                (1<<3)
  59 #define FLASH_PECR__DATA                (1<<4)
  60 #define FLASH_PECR__FTDW                (1<<8)
  61 #define FLASH_PECR__ERASE               (1<<9)
  62 #define FLASH_PECR__FPRG                (1<<10)
  63 #define FLASH_PECR__EOPIE               (1<<16)
  64 #define FLASH_PECR__ERRIE               (1<<17)
  65 #define FLASH_PECR__OBL_LAUNCH  (1<<18)
  66
  67 /* FLASH_SR bits */
  68 #define FLASH_SR__BSY           (1<<0)
  69 #define FLASH_SR__EOP           (1<<1)
  70 #define FLASH_SR__ENDHV         (1<<2)
  71 #define FLASH_SR__READY         (1<<3)
  72 #define FLASH_SR__WRPERR        (1<<8)
  73 #define FLASH_SR__PGAERR        (1<<9)
  74 #define FLASH_SR__SIZERR        (1<<10)
  75 #define FLASH_SR__OPTVERR       (1<<11)
  76
  77 /* Unlock keys */
  78 #define PEKEY1                  0x89ABCDEF
  79 #define PEKEY2                  0x02030405
  80 #define PRGKEY1                 0x8C9DAEBF
  81 #define PRGKEY2                 0x13141516
  82 #define OPTKEY1                 0xFBEAD9C8
  83 #define OPTKEY2                 0x24252627
  84
  85 /* other registers */
  86 #define DBGMCU_IDCODE           0xE0042000
  87 #define DBGMCU_IDCODE_L0        0x40015800
  88
  89 /* Constants */
  90 #define FLASH_SECTOR_SIZE 4096
  91 #define FLASH_BANK0_ADDRESS 0x08000000
  92
  93 /* option bytes */
  94 #define OPTION_BYTES_ADDRESS 0x1FF80000
  95
  96 #define OPTION_BYTE_0_PR1 0xFFFF0000
  97 #define OPTION_BYTE_0_PR0 0xFF5500AA
  98
  99 static int stm32lx_unlock_program_memory(struct flash_bank *bank);
 100 static int stm32lx_lock_program_memory(struct flash_bank *bank);
 101 static int stm32lx_enable_write_half_page(struct flash_bank *bank);
 102 static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
 103 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
 104 static int stm32lx_lock(struct flash_bank *bank);
 105 static int stm32lx_unlock(struct flash_bank *bank);
 106 static int stm32lx_mass_erase(struct flash_bank *bank);
 107 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout);
 108 static int stm32lx_update_part_info(struct flash_bank *bank, uint16_t flash_size_in_kb);
 109
 110 struct stm32lx_rev {
 111         uint16_t rev;
 112         const char *str;
 113 };
 114
 115 struct stm32lx_part_info {
 116         uint16_t id;
 117         const char *device_str;
 118         const struct stm32lx_rev *revs;
 119         size_t num_revs;
 120         unsigned int page_size;
 121         unsigned int pages_per_sector;
 122         uint16_t max_flash_size_kb;
 123         uint16_t first_bank_size_kb; /* used when has_dual_banks is true */
 124         bool has_dual_banks;
 125
 126         uint32_t flash_base;    /* Flash controller registers location */
 127         uint32_t fsize_base;    /* Location of FSIZE register */
 128 };
 129
 130 struct stm32lx_flash_bank {
 131         bool probed;
 132         uint32_t idcode;
 133         uint32_t user_bank_size;
 134         uint32_t flash_base;
 135
 136         struct stm32lx_part_info part_info;
 137 };
 138
 139 static const struct stm32lx_rev stm32_416_revs[] = {
 140         { 0x1000, "A" }, { 0x1008, "Y" }, { 0x1038, "W" }, { 0x1078, "V" },
 141 };
 142 static const struct stm32lx_rev stm32_417_revs[] = {
 143         { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, { 0x1038, "X" }
 144 };
 145 static const struct stm32lx_rev stm32_425_revs[] = {
 146         { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" },
 147 };
 148 static const struct stm32lx_rev stm32_427_revs[] = {
 149         { 0x1000, "A" }, { 0x1018, "Y" }, { 0x1038, "X" }, { 0x10f8, "V" },
 150 };
 151 static const struct stm32lx_rev stm32_429_revs[] = {
 152         { 0x1000, "A" }, { 0x1018, "Z" },
 153 };
 154 static const struct stm32lx_rev stm32_436_revs[] = {
 155         { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" },
 156 };
 157 static const struct stm32lx_rev stm32_437_revs[] = {
 158         { 0x1000, "A" },
 159 };
 160 static const struct stm32lx_rev stm32_447_revs[] = {
 161         { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Z" },
 162 };
 163 static const struct stm32lx_rev stm32_457_revs[] = {
 164         { 0x1000, "A" }, { 0x1008, "Z" },
 165 };
 166
 167 static const struct stm32lx_part_info stm32lx_parts[] = {
 168         {
 169                 .id                                     = 0x416,
 170                 .revs                           = stm32_416_revs,
 171                 .num_revs                       = ARRAY_SIZE(stm32_416_revs),
 172                 .device_str                     = "STM32L1xx (Cat.1 - Low/Medium Density)",
 173                 .page_size                      = 256,
 174                 .pages_per_sector       = 16,
 175                 .max_flash_size_kb      = 128,
 176                 .has_dual_banks         = false,
 177                 .flash_base                     = 0x40023C00,
 178                 .fsize_base                     = 0x1FF8004C,
 179         },
 180         {
 181                 .id                                     = 0x417,
 182                 .revs                           = stm32_417_revs,
 183                 .num_revs                       = ARRAY_SIZE(stm32_417_revs),
 184                 .device_str                     = "STM32L0xx (Cat. 3)",
 185                 .page_size                      = 128,
 186                 .pages_per_sector       = 32,
 187                 .max_flash_size_kb      = 64,
 188                 .has_dual_banks         = false,
 189                 .flash_base                     = 0x40022000,
 190                 .fsize_base                     = 0x1FF8007C,
 191         },
 192         {
 193                 .id                                     = 0x425,
 194                 .revs                           = stm32_425_revs,
 195                 .num_revs                       = ARRAY_SIZE(stm32_425_revs),
 196                 .device_str                     = "STM32L0xx (Cat. 2)",
 197                 .page_size                      = 128,
 198                 .pages_per_sector       = 32,
 199                 .max_flash_size_kb      = 32,
 200                 .has_dual_banks         = false,
 201                 .flash_base                     = 0x40022000,
 202                 .fsize_base                     = 0x1FF8007C,
 203         },
 204         {
 205                 .id                                     = 0x427,
 206                 .revs                           = stm32_427_revs,
 207                 .num_revs                       = ARRAY_SIZE(stm32_427_revs),
 208                 .device_str                     = "STM32L1xx (Cat.3 - Medium+ Density)",
 209                 .page_size                      = 256,
 210                 .pages_per_sector       = 16,
 211                 .max_flash_size_kb      = 256,
 212                 .has_dual_banks         = false,
 213                 .flash_base                     = 0x40023C00,
 214                 .fsize_base                     = 0x1FF800CC,
 215         },
 216         {
 217                 .id                                     = 0x429,
 218                 .revs                           = stm32_429_revs,
 219                 .num_revs                       = ARRAY_SIZE(stm32_429_revs),
 220                 .device_str                     = "STM32L1xx (Cat.2)",
 221                 .page_size                      = 256,
 222                 .pages_per_sector       = 16,
 223                 .max_flash_size_kb      = 128,
 224                 .has_dual_banks         = false,
 225                 .flash_base                     = 0x40023C00,
 226                 .fsize_base                     = 0x1FF8004C,
 227         },
 228         {
 229                 .id                                     = 0x436,
 230                 .revs                           = stm32_436_revs,
 231                 .num_revs                       = ARRAY_SIZE(stm32_436_revs),
 232                 .device_str                     = "STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)",
 233                 .page_size                      = 256,
 234                 .pages_per_sector       = 16,
 235                 .max_flash_size_kb      = 384,
 236                 .first_bank_size_kb     = 192,
 237                 .has_dual_banks         = true,
 238                 .flash_base                     = 0x40023C00,
 239                 .fsize_base                     = 0x1FF800CC,
 240         },
 241         {
 242                 .id                                     = 0x437,
 243                 .revs                           = stm32_437_revs,
 244                 .num_revs                       = ARRAY_SIZE(stm32_437_revs),
 245                 .device_str                     = "STM32L1xx (Cat.5/Cat.6)",
 246                 .page_size                      = 256,
 247                 .pages_per_sector       = 16,
 248                 .max_flash_size_kb      = 512,
 249                 .first_bank_size_kb     = 0,            /* determined in runtime */
 250                 .has_dual_banks         = true,
 251                 .flash_base                     = 0x40023C00,
 252                 .fsize_base                     = 0x1FF800CC,
 253         },
 254         {
 255                 .id                                     = 0x447,
 256                 .revs                           = stm32_447_revs,
 257                 .num_revs                       = ARRAY_SIZE(stm32_447_revs),
 258                 .device_str                     = "STM32L0xx (Cat.5)",
 259                 .page_size                      = 128,
 260                 .pages_per_sector       = 32,
 261                 .max_flash_size_kb      = 192,
 262                 .first_bank_size_kb     = 0,            /* determined in runtime */
 263                 .has_dual_banks         = false,        /* determined in runtime */
 264                 .flash_base                     = 0x40022000,
 265                 .fsize_base                     = 0x1FF8007C,
 266         },
 267         {
 268                 .id                                     = 0x457,
 269                 .revs                           = stm32_457_revs,
 270                 .num_revs                       = ARRAY_SIZE(stm32_457_revs),
 271                 .device_str                     = "STM32L0xx (Cat.1)",
 272                 .page_size                      = 128,
 273                 .pages_per_sector       = 32,
 274                 .max_flash_size_kb      = 16,
 275                 .has_dual_banks         = false,
 276                 .flash_base                     = 0x40022000,
 277                 .fsize_base                     = 0x1FF8007C,
 278         },
 279 };
 280
 281 /* flash bank stm32lx <base> <size> 0 0 <target#>
 282  */
 283 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
 284 {
 285         struct stm32lx_flash_bank *stm32lx_info;
 286         if (CMD_ARGC < 6)
 287                 return ERROR_COMMAND_SYNTAX_ERROR;
 288
 289         /* Create the bank structure */
 290         stm32lx_info = calloc(1, sizeof(*stm32lx_info));
 291
 292         /* Check allocation */
 293         if (!stm32lx_info) {
 294                 LOG_ERROR("failed to allocate bank structure");
 295                 return ERROR_FAIL;
 296         }
 297
 298         bank->driver_priv = stm32lx_info;
 299
 300         stm32lx_info->probed = false;
 301         stm32lx_info->user_bank_size = bank->size;
 302
 303         /* the stm32l erased value is 0x00 */
 304         bank->default_padded_value = bank->erased_value = 0x00;
 305
 306         return ERROR_OK;
 307 }
 308
 309 COMMAND_HANDLER(stm32lx_handle_mass_erase_command)
 310 {
 311         if (CMD_ARGC < 1)
 312                 return ERROR_COMMAND_SYNTAX_ERROR;
 313
 314         struct flash_bank *bank;
 315         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 316         if (retval != ERROR_OK)
 317                 return retval;
 318
 319         retval = stm32lx_mass_erase(bank);
 320         if (retval == ERROR_OK)
 321                 command_print(CMD, "stm32lx mass erase complete");
 322         else
 323                 command_print(CMD, "stm32lx mass erase failed");
 324
 325         return retval;
 326 }
 327
 328 COMMAND_HANDLER(stm32lx_handle_lock_command)
 329 {
 330         if (CMD_ARGC < 1)
 331                 return ERROR_COMMAND_SYNTAX_ERROR;
 332
 333         struct flash_bank *bank;
 334         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 335         if (retval != ERROR_OK)
 336                 return retval;
 337
 338         retval = stm32lx_lock(bank);
 339
 340         if (retval == ERROR_OK)
 341                 command_print(CMD, "STM32Lx locked, takes effect after power cycle.");
 342         else
 343                 command_print(CMD, "STM32Lx lock failed");
 344
 345         return retval;
 346 }
 347
 348 COMMAND_HANDLER(stm32lx_handle_unlock_command)
 349 {
 350         if (CMD_ARGC < 1)
 351                 return ERROR_COMMAND_SYNTAX_ERROR;
 352
 353         struct flash_bank *bank;
 354         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 355         if (retval != ERROR_OK)
 356                 return retval;
 357
 358         retval = stm32lx_unlock(bank);
 359
 360         if (retval == ERROR_OK)
 361                 command_print(CMD, "STM32Lx unlocked, takes effect after power cycle.");
 362         else
 363                 command_print(CMD, "STM32Lx unlock failed");
 364
 365         return retval;
 366 }
 367
 368 static int stm32lx_protect_check(struct flash_bank *bank)
 369 {
 370         int retval;
 371         struct target *target = bank->target;
 372         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 373
 374         uint32_t wrpr;
 375
 376         /*
 377          * Read the WRPR word, and check each bit (corresponding to each
 378          * flash sector
 379          */
 380         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_WRPR,
 381                         &wrpr);
 382         if (retval != ERROR_OK)
 383                 return retval;
 384
 385         for (unsigned int i = 0; i < bank->num_sectors; i++) {
 386                 if (wrpr & (1 << i))
 387                         bank->sectors[i].is_protected = 1;
 388                 else
 389                         bank->sectors[i].is_protected = 0;
 390         }
 391         return ERROR_OK;
 392 }
 393
 394 static int stm32lx_erase(struct flash_bank *bank, unsigned int first,
 395                 unsigned int last)
 396 {
 397         int retval;
 398
 399         /*
 400          * It could be possible to do a mass erase if all sectors must be
 401          * erased, but it is not implemented yet.
 402          */
 403
 404         if (bank->target->state != TARGET_HALTED) {
 405                 LOG_ERROR("Target not halted");
 406                 return ERROR_TARGET_NOT_HALTED;
 407         }
 408
 409         /*
 410          * Loop over the selected sectors and erase them
 411          */
 412         for (unsigned int i = first; i <= last; i++) {
 413                 retval = stm32lx_erase_sector(bank, i);
 414                 if (retval != ERROR_OK)
 415                         return retval;
 416                 bank->sectors[i].is_erased = 1;
 417         }
 418         return ERROR_OK;
 419 }
 420
 421 static int stm32lx_write_half_pages(struct flash_bank *bank, const uint8_t *buffer,
 422                 uint32_t offset, uint32_t count)
 423 {
 424         struct target *target = bank->target;
 425         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 426
 427         uint32_t hp_nb = stm32lx_info->part_info.page_size / 2;
 428         uint32_t buffer_size = (16384 / hp_nb) * hp_nb; /* must be multiple of hp_nb */
 429         struct working_area *write_algorithm;
 430         struct working_area *source;
 431         uint32_t address = bank->base + offset;
 432
 433         struct reg_param reg_params[5];
 434         struct armv7m_algorithm armv7m_info;
 435
 436         int retval = ERROR_OK;
 437
 438         static const uint8_t stm32lx_flash_write_code[] = {
 439 #include "../../../contrib/loaders/flash/stm32/stm32lx.inc"
 440         };
 441
 442         /* Make sure we're performing a half-page aligned write. */
 443         if (offset % hp_nb) {
 444                 LOG_ERROR("The offset must be %" PRIu32 "B-aligned but it is %" PRIi32 "B)", hp_nb, offset);
 445                 return ERROR_FAIL;
 446         }
 447         if (count % hp_nb) {
 448                 LOG_ERROR("The byte count must be %" PRIu32 "B-aligned but count is %" PRIu32 "B)", hp_nb, count);
 449                 return ERROR_FAIL;
 450         }
 451
 452         /* flash write code */
 453         if (target_alloc_working_area(target, sizeof(stm32lx_flash_write_code),
 454                         &write_algorithm) != ERROR_OK) {
 455                 LOG_DEBUG("no working area for block memory writes");
 456                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 457         }
 458
 459         /* Write the flashing code */
 460         retval = target_write_buffer(target,
 461                         write_algorithm->address,
 462                         sizeof(stm32lx_flash_write_code),
 463                         stm32lx_flash_write_code);
 464         if (retval != ERROR_OK) {
 465                 target_free_working_area(target, write_algorithm);
 466                 return retval;
 467         }
 468
 469         /* Allocate half pages memory */
 470         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 471                 if (buffer_size > 1024)
 472                         buffer_size -= 1024;
 473                 else
 474                         buffer_size /= 2;
 475
 476                 if (buffer_size <= stm32lx_info->part_info.page_size) {
 477                         /* we already allocated the writing code, but failed to get a
 478                          * buffer, free the algorithm */
 479                         target_free_working_area(target, write_algorithm);
 480
 481                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 482                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 483                 } else {
 484                         /* Make sure we're still asking for an integral number of half-pages */
 485                         buffer_size -= buffer_size % hp_nb;
 486                 }
 487         }
 488
 489         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 490         armv7m_info.core_mode = ARM_MODE_THREAD;
 491         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 492         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 493         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 494         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
 495         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
 496
 497         /* Enable half-page write */
 498         retval = stm32lx_enable_write_half_page(bank);
 499         if (retval != ERROR_OK) {
 500                 target_free_working_area(target, source);
 501                 target_free_working_area(target, write_algorithm);
 502
 503                 destroy_reg_param(&reg_params[0]);
 504                 destroy_reg_param(&reg_params[1]);
 505                 destroy_reg_param(&reg_params[2]);
 506                 destroy_reg_param(&reg_params[3]);
 507                 destroy_reg_param(&reg_params[4]);
 508                 return retval;
 509         }
 510
 511         struct armv7m_common *armv7m = target_to_armv7m(target);
 512         if (!armv7m) {
 513
 514                 /* something is very wrong if armv7m is NULL */
 515                 LOG_ERROR("unable to get armv7m target");
 516                 return retval;
 517         }
 518
 519         /* save any DEMCR flags and configure target to catch any Hard Faults */
 520         uint32_t demcr_save = armv7m->demcr;
 521         armv7m->demcr = VC_HARDERR;
 522
 523         /* Loop while there are bytes to write */
 524         while (count > 0) {
 525                 uint32_t this_count;
 526                 this_count = (count > buffer_size) ? buffer_size : count;
 527
 528                 /* Write the next half pages */
 529                 retval = target_write_buffer(target, source->address, this_count, buffer);
 530                 if (retval != ERROR_OK)
 531                         break;
 532
 533                 /* 4: Store useful information in the registers */
 534                 /* the destination address of the copy (R0) */
 535                 buf_set_u32(reg_params[0].value, 0, 32, address);
 536                 /* The source address of the copy (R1) */
 537                 buf_set_u32(reg_params[1].value, 0, 32, source->address);
 538                 /* The number of half pages to copy (R2) */
 539                 buf_set_u32(reg_params[2].value, 0, 32, this_count / hp_nb);
 540                 /* The size in byes of a half page (R3) */
 541                 buf_set_u32(reg_params[3].value, 0, 32, hp_nb);
 542                 /* The flash base address (R4) */
 543                 buf_set_u32(reg_params[4].value, 0, 32, stm32lx_info->flash_base);
 544
 545                 /* 5: Execute the bunch of code */
 546                 retval = target_run_algorithm(target, 0, NULL,
 547                                 ARRAY_SIZE(reg_params), reg_params,
 548                                 write_algorithm->address, 0, 10000, &armv7m_info);
 549                 if (retval != ERROR_OK)
 550                         break;
 551
 552                 /* check for Hard Fault */
 553                 if (armv7m->exception_number == 3)
 554                         break;
 555
 556                 /* 6: Wait while busy */
 557                 retval = stm32lx_wait_until_bsy_clear(bank);
 558                 if (retval != ERROR_OK)
 559                         break;
 560
 561                 buffer += this_count;
 562                 address += this_count;
 563                 count -= this_count;
 564         }
 565
 566         /* restore previous flags */
 567         armv7m->demcr = demcr_save;
 568
 569         if (armv7m->exception_number == 3) {
 570
 571                 /* the stm32l15x devices seem to have an issue when blank.
 572                  * if a ram loader is executed on a blank device it will
 573                  * Hard Fault, this issue does not happen for a already programmed device.
 574                  * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
 575                  * The workaround of handling the Hard Fault exception does work, but makes the
 576                  * loader more complicated, as a compromise we manually write the pages, programming time
 577                  * is reduced by 50% using this slower method.
 578                  */
 579
 580                 LOG_WARNING("Couldn't use loader, falling back to page memory writes");
 581
 582                 while (count > 0) {
 583                         uint32_t this_count;
 584                         this_count = (count > hp_nb) ? hp_nb : count;
 585
 586                         /* Write the next half pages */
 587                         retval = target_write_buffer(target, address, this_count, buffer);
 588                         if (retval != ERROR_OK)
 589                                 break;
 590
 591                         /* Wait while busy */
 592                         retval = stm32lx_wait_until_bsy_clear(bank);
 593                         if (retval != ERROR_OK)
 594                                 break;
 595
 596                         buffer += this_count;
 597                         address += this_count;
 598                         count -= this_count;
 599                 }
 600         }
 601
 602         if (retval == ERROR_OK)
 603                 retval = stm32lx_lock_program_memory(bank);
 604
 605         target_free_working_area(target, source);
 606         target_free_working_area(target, write_algorithm);
 607
 608         destroy_reg_param(&reg_params[0]);
 609         destroy_reg_param(&reg_params[1]);
 610         destroy_reg_param(&reg_params[2]);
 611         destroy_reg_param(&reg_params[3]);
 612         destroy_reg_param(&reg_params[4]);
 613
 614         return retval;
 615 }
 616
 617 static int stm32lx_write(struct flash_bank *bank, const uint8_t *buffer,
 618                 uint32_t offset, uint32_t count)
 619 {
 620         struct target *target = bank->target;
 621         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 622
 623         uint32_t hp_nb = stm32lx_info->part_info.page_size / 2;
 624         uint32_t halfpages_number;
 625         uint32_t bytes_remaining = 0;
 626         uint32_t address = bank->base + offset;
 627         uint32_t bytes_written = 0;
 628         int retval, retval2;
 629
 630         if (bank->target->state != TARGET_HALTED) {
 631                 LOG_ERROR("Target not halted");
 632                 return ERROR_TARGET_NOT_HALTED;
 633         }
 634
 635         if (offset & 0x3) {
 636                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
 637                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 638         }
 639
 640         retval = stm32lx_unlock_program_memory(bank);
 641         if (retval != ERROR_OK)
 642                 return retval;
 643
 644         /* first we need to write any unaligned head bytes up to
 645          * the next 128 byte page */
 646
 647         if (offset % hp_nb)
 648                 bytes_remaining = MIN(count, hp_nb - (offset % hp_nb));
 649
 650         while (bytes_remaining > 0) {
 651                 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
 652
 653                 /* copy remaining bytes into the write buffer */
 654                 uint32_t bytes_to_write = MIN(4, bytes_remaining);
 655                 memcpy(value, buffer + bytes_written, bytes_to_write);
 656
 657                 retval = target_write_buffer(target, address, 4, value);
 658                 if (retval != ERROR_OK)
 659                         goto reset_pg_and_lock;
 660
 661                 bytes_written += bytes_to_write;
 662                 bytes_remaining -= bytes_to_write;
 663                 address += 4;
 664
 665                 retval = stm32lx_wait_until_bsy_clear(bank);
 666                 if (retval != ERROR_OK)
 667                         goto reset_pg_and_lock;
 668         }
 669
 670         offset += bytes_written;
 671         count -= bytes_written;
 672
 673         /* this should always pass this check here */
 674         assert((offset % hp_nb) == 0);
 675
 676         /* calculate half pages */
 677         halfpages_number = count / hp_nb;
 678
 679         if (halfpages_number) {
 680                 retval = stm32lx_write_half_pages(bank, buffer + bytes_written, offset, hp_nb * halfpages_number);
 681                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 682                         /* attempt slow memory writes */
 683                         LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 684                         halfpages_number = 0;
 685                 } else {
 686                         if (retval != ERROR_OK)
 687                                 return ERROR_FAIL;
 688                 }
 689         }
 690
 691         /* write any remaining bytes */
 692         uint32_t page_bytes_written = hp_nb * halfpages_number;
 693         bytes_written += page_bytes_written;
 694         address += page_bytes_written;
 695         bytes_remaining = count - page_bytes_written;
 696
 697         retval = stm32lx_unlock_program_memory(bank);
 698         if (retval != ERROR_OK)
 699                 return retval;
 700
 701         while (bytes_remaining > 0) {
 702                 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
 703
 704                 /* copy remaining bytes into the write buffer */
 705                 uint32_t bytes_to_write = MIN(4, bytes_remaining);
 706                 memcpy(value, buffer + bytes_written, bytes_to_write);
 707
 708                 retval = target_write_buffer(target, address, 4, value);
 709                 if (retval != ERROR_OK)
 710                         goto reset_pg_and_lock;
 711
 712                 bytes_written += bytes_to_write;
 713                 bytes_remaining -= bytes_to_write;
 714                 address += 4;
 715
 716                 retval = stm32lx_wait_until_bsy_clear(bank);
 717                 if (retval != ERROR_OK)
 718                         goto reset_pg_and_lock;
 719         }
 720
 721 reset_pg_and_lock:
 722         retval2 = stm32lx_lock_program_memory(bank);
 723         if (retval == ERROR_OK)
 724                 retval = retval2;
 725
 726         return retval;
 727 }
 728
 729 static int stm32lx_read_id_code(struct target *target, uint32_t *id)
 730 {
 731         struct armv7m_common *armv7m = target_to_armv7m(target);
 732         int retval;
 733         if (armv7m->arm.arch == ARM_ARCH_V6M)
 734                 retval = target_read_u32(target, DBGMCU_IDCODE_L0, id);
 735         else
 736         /* read stm32 device id register */
 737                 retval = target_read_u32(target, DBGMCU_IDCODE, id);
 738         return retval;
 739 }
 740
 741 static int stm32lx_probe(struct flash_bank *bank)
 742 {
 743         struct target *target = bank->target;
 744         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 745         uint16_t flash_size_in_kb;
 746         uint32_t device_id;
 747         uint32_t base_address = FLASH_BANK0_ADDRESS;
 748         uint32_t second_bank_base;
 749         unsigned int n;
 750
 751         stm32lx_info->probed = false;
 752
 753         int retval = stm32lx_read_id_code(bank->target, &device_id);
 754         if (retval != ERROR_OK)
 755                 return retval;
 756
 757         stm32lx_info->idcode = device_id;
 758
 759         LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
 760
 761         for (n = 0; n < ARRAY_SIZE(stm32lx_parts); n++) {
 762                 if ((device_id & 0xfff) == stm32lx_parts[n].id) {
 763                         stm32lx_info->part_info = stm32lx_parts[n];
 764                         break;
 765                 }
 766         }
 767
 768         if (n == ARRAY_SIZE(stm32lx_parts)) {
 769                 LOG_ERROR("Cannot identify target as an STM32 L0 or L1 family device.");
 770                 return ERROR_FAIL;
 771         } else {
 772                 LOG_INFO("Device: %s", stm32lx_info->part_info.device_str);
 773         }
 774
 775         stm32lx_info->flash_base = stm32lx_info->part_info.flash_base;
 776
 777         /* Get the flash size from target. */
 778         retval = target_read_u16(target, stm32lx_info->part_info.fsize_base,
 779                         &flash_size_in_kb);
 780
 781         /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
 782          * or 256K, respectively.  Please see RM0038 r8 or newer and refer to
 783          * section 30.1.1. */
 784         if (retval == ERROR_OK && (device_id & 0xfff) == 0x436) {
 785                 if (flash_size_in_kb == 0)
 786                         flash_size_in_kb = 384;
 787                 else if (flash_size_in_kb == 1)
 788                         flash_size_in_kb = 256;
 789         }
 790
 791         /* 0x429 devices only use the lowest 8 bits of the flash size register */
 792         if (retval == ERROR_OK && (device_id & 0xfff) == 0x429) {
 793                 flash_size_in_kb &= 0xff;
 794         }
 795
 796         /* Failed reading flash size or flash size invalid (early silicon),
 797          * default to max target family */
 798         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 799                 LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
 800                         stm32lx_info->part_info.max_flash_size_kb);
 801                 flash_size_in_kb = stm32lx_info->part_info.max_flash_size_kb;
 802         } else if (flash_size_in_kb > stm32lx_info->part_info.max_flash_size_kb) {
 803                 LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
 804                         flash_size_in_kb, stm32lx_info->part_info.max_flash_size_kb,
 805                         stm32lx_info->part_info.max_flash_size_kb);
 806                 flash_size_in_kb = stm32lx_info->part_info.max_flash_size_kb;
 807         }
 808
 809         /* Overwrite default dual-bank configuration */
 810         retval = stm32lx_update_part_info(bank, flash_size_in_kb);
 811         if (retval != ERROR_OK)
 812                 return ERROR_FAIL;
 813
 814         if (stm32lx_info->part_info.has_dual_banks) {
 815                 /* Use the configured base address to determine if this is the first or second flash bank.
 816                  * Verify that the base address is reasonably correct and determine the flash bank size
 817                  */
 818                 second_bank_base = base_address +
 819                         stm32lx_info->part_info.first_bank_size_kb * 1024;
 820                 if (bank->base == second_bank_base || !bank->base) {
 821                         /* This is the second bank  */
 822                         base_address = second_bank_base;
 823                         flash_size_in_kb = flash_size_in_kb -
 824                                 stm32lx_info->part_info.first_bank_size_kb;
 825                 } else if (bank->base == base_address) {
 826                         /* This is the first bank */
 827                         flash_size_in_kb = stm32lx_info->part_info.first_bank_size_kb;
 828                 } else {
 829                         LOG_WARNING("STM32L flash bank base address config is incorrect. "
 830                                         TARGET_ADDR_FMT " but should rather be 0x%" PRIx32
 831                                         " or 0x%" PRIx32,
 832                                                 bank->base, base_address, second_bank_base);
 833                         return ERROR_FAIL;
 834                 }
 835                 LOG_INFO("STM32L flash has dual banks. Bank (%u) size is %dkb, base address is 0x%" PRIx32,
 836                                 bank->bank_number, flash_size_in_kb, base_address);
 837         } else {
 838                 LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
 839         }
 840
 841         /* if the user sets the size manually then ignore the probed value
 842          * this allows us to work around devices that have a invalid flash size register value */
 843         if (stm32lx_info->user_bank_size) {
 844                 flash_size_in_kb = stm32lx_info->user_bank_size / 1024;
 845                 LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb);
 846         }
 847
 848         /* calculate numbers of sectors (4kB per sector) */
 849         unsigned int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
 850
 851         free(bank->sectors);
 852
 853         bank->size = flash_size_in_kb * 1024;
 854         bank->base = base_address;
 855         bank->num_sectors = num_sectors;
 856         bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
 857         if (!bank->sectors) {
 858                 LOG_ERROR("failed to allocate bank sectors");
 859                 return ERROR_FAIL;
 860         }
 861
 862         for (unsigned int i = 0; i < num_sectors; i++) {
 863                 bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
 864                 bank->sectors[i].size = FLASH_SECTOR_SIZE;
 865                 bank->sectors[i].is_erased = -1;
 866                 bank->sectors[i].is_protected = -1;
 867         }
 868
 869         stm32lx_info->probed = true;
 870
 871         return ERROR_OK;
 872 }
 873
 874 static int stm32lx_auto_probe(struct flash_bank *bank)
 875 {
 876         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 877
 878         if (stm32lx_info->probed)
 879                 return ERROR_OK;
 880
 881         return stm32lx_probe(bank);
 882 }
 883
 884 /* This method must return a string displaying information about the bank */
 885 static int stm32lx_get_info(struct flash_bank *bank, struct command_invocation *cmd)
 886 {
 887         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 888         const struct stm32lx_part_info *info = &stm32lx_info->part_info;
 889         uint16_t rev_id = stm32lx_info->idcode >> 16;
 890         const char *rev_str = NULL;
 891
 892         if (!stm32lx_info->probed) {
 893                 int retval = stm32lx_probe(bank);
 894                 if (retval != ERROR_OK) {
 895                         command_print_sameline(cmd, "Unable to find bank information.");
 896                         return retval;
 897                 }
 898         }
 899
 900         for (unsigned int i = 0; i < info->num_revs; i++)
 901                 if (rev_id == info->revs[i].rev)
 902                         rev_str = info->revs[i].str;
 903
 904         if (rev_str) {
 905                 command_print_sameline(cmd, "%s - Rev: %s", info->device_str, rev_str);
 906         } else {
 907                 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", info->device_str, rev_id);
 908         }
 909
 910         return ERROR_OK;
 911 }
 912
 913 static const struct command_registration stm32lx_exec_command_handlers[] = {
 914         {
 915                 .name = "mass_erase",
 916                 .handler = stm32lx_handle_mass_erase_command,
 917                 .mode = COMMAND_EXEC,
 918                 .usage = "bank_id",
 919                 .help = "Erase entire flash device. including available EEPROM",
 920         },
 921         {
 922                 .name = "lock",
 923                 .handler = stm32lx_handle_lock_command,
 924                 .mode = COMMAND_EXEC,
 925                 .usage = "bank_id",
 926                 .help = "Increase the readout protection to Level 1.",
 927         },
 928         {
 929                 .name = "unlock",
 930                 .handler = stm32lx_handle_unlock_command,
 931                 .mode = COMMAND_EXEC,
 932                 .usage = "bank_id",
 933                 .help = "Lower the readout protection from Level 1 to 0.",
 934         },
 935         COMMAND_REGISTRATION_DONE
 936 };
 937
 938 static const struct command_registration stm32lx_command_handlers[] = {
 939         {
 940                 .name = "stm32lx",
 941                 .mode = COMMAND_ANY,
 942                 .help = "stm32lx flash command group",
 943                 .usage = "",
 944                 .chain = stm32lx_exec_command_handlers,
 945         },
 946         COMMAND_REGISTRATION_DONE
 947 };
 948
 949 const struct flash_driver stm32lx_flash = {
 950                 .name = "stm32lx",
 951                 .commands = stm32lx_command_handlers,
 952                 .flash_bank_command = stm32lx_flash_bank_command,
 953                 .erase = stm32lx_erase,
 954                 .write = stm32lx_write,
 955                 .read = default_flash_read,
 956                 .probe = stm32lx_probe,
 957                 .auto_probe = stm32lx_auto_probe,
 958                 .erase_check = default_flash_blank_check,
 959                 .protect_check = stm32lx_protect_check,
 960                 .info = stm32lx_get_info,
 961                 .free_driver_priv = default_flash_free_driver_priv,
 962 };
 963
 964 /* Static methods implementation */
 965 static int stm32lx_unlock_program_memory(struct flash_bank *bank)
 966 {
 967         struct target *target = bank->target;
 968         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
 969         int retval;
 970         uint32_t reg32;
 971
 972         /*
 973          * Unlocking the program memory is done by unlocking the PECR,
 974          * then by writing the 2 PRGKEY to the PRGKEYR register
 975          */
 976
 977         /* check flash is not already unlocked */
 978         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
 979                         &reg32);
 980         if (retval != ERROR_OK)
 981                 return retval;
 982
 983         if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
 984                 return ERROR_OK;
 985
 986         /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
 987         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
 988                         PEKEY1);
 989         if (retval != ERROR_OK)
 990                 return retval;
 991
 992         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
 993                         PEKEY2);
 994         if (retval != ERROR_OK)
 995                 return retval;
 996
 997         /* Make sure it worked */
 998         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
 999                         &reg32);
1000         if (retval != ERROR_OK)
1001                 return retval;
1002
1003         if (reg32 & FLASH_PECR__PELOCK) {
1004                 LOG_ERROR("PELOCK is not cleared :(");
1005                 return ERROR_FLASH_OPERATION_FAILED;
1006         }
1007
1008         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
1009                         PRGKEY1);
1010         if (retval != ERROR_OK)
1011                 return retval;
1012         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
1013                         PRGKEY2);
1014         if (retval != ERROR_OK)
1015                 return retval;
1016
1017         /* Make sure it worked */
1018         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1019                         &reg32);
1020         if (retval != ERROR_OK)
1021                 return retval;
1022
1023         if (reg32 & FLASH_PECR__PRGLOCK) {
1024                 LOG_ERROR("PRGLOCK is not cleared :(");
1025                 return ERROR_FLASH_OPERATION_FAILED;
1026         }
1027
1028         return ERROR_OK;
1029 }
1030
1031 static int stm32lx_enable_write_half_page(struct flash_bank *bank)
1032 {
1033         struct target *target = bank->target;
1034         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1035         int retval;
1036         uint32_t reg32;
1037
1038         /**
1039          * Unlock the program memory, then set the FPRG bit in the PECR register.
1040          */
1041         retval = stm32lx_unlock_program_memory(bank);
1042         if (retval != ERROR_OK)
1043                 return retval;
1044
1045         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1046                         &reg32);
1047         if (retval != ERROR_OK)
1048                 return retval;
1049
1050         reg32 |= FLASH_PECR__FPRG;
1051         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1052                         reg32);
1053         if (retval != ERROR_OK)
1054                 return retval;
1055
1056         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1057                         &reg32);
1058         if (retval != ERROR_OK)
1059                 return retval;
1060
1061         reg32 |= FLASH_PECR__PROG;
1062         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1063                         reg32);
1064
1065         return retval;
1066 }
1067
1068 static int stm32lx_lock_program_memory(struct flash_bank *bank)
1069 {
1070         struct target *target = bank->target;
1071         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1072         int retval;
1073         uint32_t reg32;
1074
1075         /* To lock the program memory, simply set the lock bit and lock PECR */
1076
1077         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1078                         &reg32);
1079         if (retval != ERROR_OK)
1080                 return retval;
1081
1082         reg32 |= FLASH_PECR__PRGLOCK;
1083         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1084                         reg32);
1085         if (retval != ERROR_OK)
1086                 return retval;
1087
1088         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1089                         &reg32);
1090         if (retval != ERROR_OK)
1091                 return retval;
1092
1093         reg32 |= FLASH_PECR__PELOCK;
1094         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1095                         reg32);
1096         if (retval != ERROR_OK)
1097                 return retval;
1098
1099         return ERROR_OK;
1100 }
1101
1102 static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
1103 {
1104         struct target *target = bank->target;
1105         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1106         int retval;
1107         uint32_t reg32;
1108
1109         /*
1110          * To erase a sector (i.e. stm32lx_info->part_info.pages_per_sector pages),
1111          * first unlock the memory, loop over the pages of this sector
1112          * and write 0x0 to its first word.
1113          */
1114
1115         retval = stm32lx_unlock_program_memory(bank);
1116         if (retval != ERROR_OK)
1117                 return retval;
1118
1119         for (int page = 0; page < (int)stm32lx_info->part_info.pages_per_sector;
1120                         page++) {
1121                 reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
1122                 retval = target_write_u32(target,
1123                                 stm32lx_info->flash_base + FLASH_PECR, reg32);
1124                 if (retval != ERROR_OK)
1125                         return retval;
1126
1127                 retval = stm32lx_wait_until_bsy_clear(bank);
1128                 if (retval != ERROR_OK)
1129                         return retval;
1130
1131                 uint32_t addr = bank->base + bank->sectors[sector].offset + (page
1132                                 * stm32lx_info->part_info.page_size);
1133                 retval = target_write_u32(target, addr, 0x0);
1134                 if (retval != ERROR_OK)
1135                         return retval;
1136
1137                 retval = stm32lx_wait_until_bsy_clear(bank);
1138                 if (retval != ERROR_OK)
1139                         return retval;
1140         }
1141
1142         retval = stm32lx_lock_program_memory(bank);
1143         if (retval != ERROR_OK)
1144                 return retval;
1145
1146         return ERROR_OK;
1147 }
1148
1149 static inline int stm32lx_get_flash_status(struct flash_bank *bank, uint32_t *status)
1150 {
1151         struct target *target = bank->target;
1152         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1153
1154         return target_read_u32(target, stm32lx_info->flash_base + FLASH_SR, status);
1155 }
1156
1157 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
1158 {
1159         return stm32lx_wait_until_bsy_clear_timeout(bank, 100);
1160 }
1161
1162 static int stm32lx_unlock_options_bytes(struct flash_bank *bank)
1163 {
1164         struct target *target = bank->target;
1165         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1166         int retval;
1167         uint32_t reg32;
1168
1169         /*
1170         * Unlocking the options bytes is done by unlocking the PECR,
1171         * then by writing the 2 FLASH_PEKEYR to the FLASH_OPTKEYR register
1172         */
1173
1174         /* check flash is not already unlocked */
1175         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
1176         if (retval != ERROR_OK)
1177                 return retval;
1178
1179         if ((reg32 & FLASH_PECR__OPTLOCK) == 0)
1180                 return ERROR_OK;
1181
1182         if ((reg32 & FLASH_PECR__PELOCK) != 0) {
1183
1184                 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY1);
1185                 if (retval != ERROR_OK)
1186                         return retval;
1187
1188                 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY2);
1189                 if (retval != ERROR_OK)
1190                         return retval;
1191         }
1192
1193         /* To unlock the PECR write the 2 OPTKEY to the FLASH_OPTKEYR register */
1194         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY1);
1195         if (retval != ERROR_OK)
1196                 return retval;
1197
1198         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY2);
1199         if (retval != ERROR_OK)
1200                 return retval;
1201
1202         return ERROR_OK;
1203 }
1204
1205 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout)
1206 {
1207         struct target *target = bank->target;
1208         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1209         uint32_t status;
1210         int retval = ERROR_OK;
1211
1212         /* wait for busy to clear */
1213         for (;;) {
1214                 retval = stm32lx_get_flash_status(bank, &status);
1215                 if (retval != ERROR_OK)
1216                         return retval;
1217
1218                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
1219                 if ((status & FLASH_SR__BSY) == 0)
1220                         break;
1221
1222                 if (timeout-- <= 0) {
1223                         LOG_ERROR("timed out waiting for flash");
1224                         return ERROR_FAIL;
1225                 }
1226                 alive_sleep(1);
1227         }
1228
1229         if (status & FLASH_SR__WRPERR) {
1230                 LOG_ERROR("access denied / write protected");
1231                 retval = ERROR_FAIL;
1232         }
1233
1234         if (status & FLASH_SR__PGAERR) {
1235                 LOG_ERROR("invalid program address");
1236                 retval = ERROR_FAIL;
1237         }
1238
1239         /* Clear but report errors */
1240         if (status & FLASH_SR__OPTVERR) {
1241                 /* If this operation fails, we ignore it and report the original retval */
1242                 target_write_u32(target, stm32lx_info->flash_base + FLASH_SR, status & FLASH_SR__OPTVERR);
1243         }
1244
1245         return retval;
1246 }
1247
1248 static int stm32lx_obl_launch(struct flash_bank *bank)
1249 {
1250         struct target *target = bank->target;
1251         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1252         int retval;
1253
1254         /* This will fail as the target gets immediately rebooted */
1255         target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1256                          FLASH_PECR__OBL_LAUNCH);
1257
1258         size_t tries = 10;
1259         do {
1260                 target_halt(target);
1261                 retval = target_poll(target);
1262         } while (--tries > 0 &&
1263                  (retval != ERROR_OK || target->state != TARGET_HALTED));
1264
1265         return tries ? ERROR_OK : ERROR_FAIL;
1266 }
1267
1268 static int stm32lx_lock(struct flash_bank *bank)
1269 {
1270         int retval;
1271         struct target *target = bank->target;
1272
1273         if (target->state != TARGET_HALTED) {
1274                 LOG_ERROR("Target not halted");
1275                 return ERROR_TARGET_NOT_HALTED;
1276         }
1277
1278         retval = stm32lx_unlock_options_bytes(bank);
1279         if (retval != ERROR_OK)
1280                 return retval;
1281
1282         /* set the RDP protection level to 1 */
1283         retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR1);
1284         if (retval != ERROR_OK)
1285                 return retval;
1286
1287         return ERROR_OK;
1288 }
1289
1290 static int stm32lx_unlock(struct flash_bank *bank)
1291 {
1292         int retval;
1293         struct target *target = bank->target;
1294
1295         if (target->state != TARGET_HALTED) {
1296                 LOG_ERROR("Target not halted");
1297                 return ERROR_TARGET_NOT_HALTED;
1298         }
1299
1300         retval = stm32lx_unlock_options_bytes(bank);
1301         if (retval != ERROR_OK)
1302                 return retval;
1303
1304         /* set the RDP protection level to 0 */
1305         retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR0);
1306         if (retval != ERROR_OK)
1307                 return retval;
1308
1309         retval = stm32lx_wait_until_bsy_clear_timeout(bank, 30000);
1310         if (retval != ERROR_OK)
1311                 return retval;
1312
1313         return ERROR_OK;
1314 }
1315
1316 static int stm32lx_mass_erase(struct flash_bank *bank)
1317 {
1318         int retval;
1319         struct target *target = bank->target;
1320         struct stm32lx_flash_bank *stm32lx_info = NULL;
1321         uint32_t reg32;
1322
1323         if (target->state != TARGET_HALTED) {
1324                 LOG_ERROR("Target not halted");
1325                 return ERROR_TARGET_NOT_HALTED;
1326         }
1327
1328         stm32lx_info = bank->driver_priv;
1329
1330         retval = stm32lx_lock(bank);
1331         if (retval != ERROR_OK)
1332                 return retval;
1333
1334         retval = stm32lx_obl_launch(bank);
1335         if (retval != ERROR_OK)
1336                 return retval;
1337
1338         retval = stm32lx_unlock(bank);
1339         if (retval != ERROR_OK)
1340                 return retval;
1341
1342         retval = stm32lx_obl_launch(bank);
1343         if (retval != ERROR_OK)
1344                 return retval;
1345
1346         retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
1347         if (retval != ERROR_OK)
1348                 return retval;
1349
1350         retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR, reg32 | FLASH_PECR__OPTLOCK);
1351         if (retval != ERROR_OK)
1352                 return retval;
1353
1354         return ERROR_OK;
1355 }
1356
1357 static int stm32lx_update_part_info(struct flash_bank *bank, uint16_t flash_size_in_kb)
1358 {
1359         struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1360
1361         switch (stm32lx_info->part_info.id) {
1362         case 0x447: /* STM32L0xx (Cat.5) devices */
1363                 if (flash_size_in_kb == 192 || flash_size_in_kb == 128) {
1364                         stm32lx_info->part_info.first_bank_size_kb = flash_size_in_kb / 2;
1365                         stm32lx_info->part_info.has_dual_banks = true;
1366                 }
1367                 break;
1368         case 0x437: /* STM32L1xx (Cat.5/Cat.6) */
1369                 stm32lx_info->part_info.first_bank_size_kb = flash_size_in_kb / 2;
1370                 break;
1371         }
1372
1373         return ERROR_OK;
1374 }