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   1 /***************************************************************************
   2  *   Copyright (C) 2015 by Uwe Bonnes                                      *
   3  *   bon@elektron.ikp.physik.tu-darmstadt.de                               *
   4  *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifndef OPENOCD_FLASH_NOR_STM32L4X
  20 #define OPENOCD_FLASH_NOR_STM32L4X
  21
  22 /* Flash registers offsets */
  23 #define STM32_FLASH_ACR                 0x00
  24 #define STM32_FLASH_KEYR                0x08
  25 #define STM32_FLASH_OPTKEYR             0x0c
  26 #define STM32_FLASH_SR                  0x10
  27 #define STM32_FLASH_CR                  0x14
  28 #define STM32_FLASH_OPTR                0x20
  29 #define STM32_FLASH_WRP1AR              0x2c
  30 #define STM32_FLASH_WRP1BR              0x30
  31 #define STM32_FLASH_WRP2AR              0x4c
  32 #define STM32_FLASH_WRP2BR              0x50
  33
  34 /* FLASH_CR register bits */
  35 #define FLASH_PG                                (1 << 0)
  36 #define FLASH_PER                               (1 << 1)
  37 #define FLASH_MER1                              (1 << 2)
  38 #define FLASH_PAGE_SHIFT                3
  39 #define FLASH_CR_BKER                   (1 << 11)
  40 #define FLASH_MER2                              (1 << 15)
  41 #define FLASH_STRT                              (1 << 16)
  42 #define FLASH_OPTSTRT                   (1 << 17)
  43 #define FLASH_EOPIE                             (1 << 24)
  44 #define FLASH_ERRIE                             (1 << 25)
  45 #define FLASH_OBL_LAUNCH                (1 << 27)
  46 #define FLASH_OPTLOCK                   (1 << 30)
  47 #define FLASH_LOCK                              (1 << 31)
  48
  49 /* FLASH_SR register bits */
  50 #define FLASH_BSY                               (1 << 16)
  51
  52 /* Fast programming not used => related errors not used*/
  53 #define FLASH_PGSERR                    (1 << 7) /* Programming sequence error */
  54 #define FLASH_SIZERR                    (1 << 6) /* Size error */
  55 #define FLASH_PGAERR                    (1 << 5) /* Programming alignment error */
  56 #define FLASH_WRPERR                    (1 << 4) /* Write protection error */
  57 #define FLASH_PROGERR                   (1 << 3) /* Programming error */
  58 #define FLASH_OPERR                             (1 << 1) /* Operation error */
  59 #define FLASH_EOP                               (1 << 0) /* End of operation */
  60 #define FLASH_ERROR                             (FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | \
  61                                                                 FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
  62
  63 /* register unlock keys */
  64 #define KEY1                                    0x45670123
  65 #define KEY2                                    0xCDEF89AB
  66
  67 /* option register unlock key */
  68 #define OPTKEY1                                 0x08192A3B
  69 #define OPTKEY2                                 0x4C5D6E7F
  70
  71 #define RDP_LEVEL_0                             0xAA
  72 #define RDP_LEVEL_1                             0xBB
  73 #define RDP_LEVEL_2                             0xCC
  74
  75 /* other registers */
  76 #define DBGMCU_IDCODE_G0                0x40015800
  77 #define DBGMCU_IDCODE_L4_G4             0xE0042000
  78 #define DBGMCU_IDCODE_L5                0xE0044000
  79
  80 #define STM32_FLASH_BANK_BASE   0x08000000
  81
  82 #endif