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   1 /***************************************************************************
   2  *   Copyright (C) 2015 by Uwe Bonnes                                      *
   3  *   bon@elektron.ikp.physik.tu-darmstadt.de                               *
   4  *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifndef OPENOCD_FLASH_NOR_STM32L4X
  20 #define OPENOCD_FLASH_NOR_STM32L4X
  21
  22 /* IMPORTANT: this file is included by stm32l4x driver and flashloader,
  23  * so please when changing this file, do not forget to check the flashloader */
  24
  25 /* FIXME: #include "helper/bits.h" cause build errors when compiling
  26  * the flashloader, for now just redefine the needed 'BIT 'macro */
  27
  28 #ifndef BIT
  29 #define BIT(nr)                 (1UL << (nr))
  30 #endif
  31
  32 /* FLASH_CR register bits */
  33 #define FLASH_PG                                BIT(0)
  34 #define FLASH_PER                               BIT(1)
  35 #define FLASH_MER1                              BIT(2)
  36 #define FLASH_PAGE_SHIFT                3
  37 #define FLASH_BKER                              BIT(11)
  38 #define FLASH_BKER_G0                   BIT(13)
  39 #define FLASH_MER2                              BIT(15)
  40 #define FLASH_STRT                              BIT(16)
  41 #define FLASH_OPTSTRT                   BIT(17)
  42 #define FLASH_EOPIE                             BIT(24)
  43 #define FLASH_ERRIE                             BIT(25)
  44 #define FLASH_OBL_LAUNCH                BIT(27)
  45 #define FLASH_OPTLOCK                   BIT(30)
  46 #define FLASH_LOCK                              BIT(31)
  47
  48 /* FLASH_SR register bits */
  49 #define FLASH_BSY                               BIT(16)
  50 #define FLASH_BSY2                              BIT(17)
  51
  52 /* Fast programming not used => related errors not used*/
  53 #define FLASH_PGSERR                    BIT(7) /* Programming sequence error */
  54 #define FLASH_SIZERR                    BIT(6) /* Size error */
  55 #define FLASH_PGAERR                    BIT(5) /* Programming alignment error */
  56 #define FLASH_WRPERR                    BIT(4) /* Write protection error */
  57 #define FLASH_PROGERR                   BIT(3) /* Programming error */
  58 #define FLASH_OPERR                             BIT(1) /* Operation error */
  59 #define FLASH_EOP                               BIT(0) /* End of operation */
  60 #define FLASH_ERROR                             (FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | \
  61                                                                 FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
  62
  63 /* register unlock keys */
  64 #define KEY1                                    0x45670123
  65 #define KEY2                                    0xCDEF89AB
  66
  67 /* option register unlock key */
  68 #define OPTKEY1                                 0x08192A3B
  69 #define OPTKEY2                                 0x4C5D6E7F
  70
  71 /* FLASH_OPTR register bits */
  72 #define FLASH_RDP_MASK                  0xFF
  73 #define FLASH_G0_DUAL_BANK              BIT(21)
  74 #define FLASH_G4_DUAL_BANK              BIT(22)
  75 #define FLASH_L4_DUAL_BANK              BIT(21)
  76 #define FLASH_L4R_DBANK                 BIT(22)
  77 #define FLASH_LRR_DB1M                  BIT(21)
  78 #define FLASH_L5_DBANK                  BIT(22)
  79 #define FLASH_L5_DB256                  BIT(21)
  80 #define FLASH_U5_DUALBANK               BIT(21)
  81 #define FLASH_TZEN                              BIT(31)
  82
  83 /* FLASH secure block based bank 1/2 register offsets */
  84 #define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
  85 #define FLASH_SECBB2(X) (0xA0 + 4 * (X - 1))
  86
  87 #define FLASH_SECBB_SECURE      0xFFFFFFFF
  88 #define FLASH_SECBB_NON_SECURE  0
  89
  90 /* IDCODE register possible addresses */
  91 #define DBGMCU_IDCODE_G0                0x40015800
  92 #define DBGMCU_IDCODE_L4_G4             0xE0042000
  93 #define DBGMCU_IDCODE_L5                0xE0044000
  94 #define UID64_DEVNUM                    0x1FFF7580
  95 #define UID64_IDS                               0x1FFF7584
  96 #define UID64_IDS_STM32WL               0x0080E115
  97
  98 /* Supported device IDs */
  99 #define DEVID_STM32L47_L48XX    0x415
 100 #define DEVID_STM32L43_L44XX    0x435
 101 #define DEVID_STM32G05_G06XX    0x456
 102 #define DEVID_STM32G07_G08XX    0x460
 103 #define DEVID_STM32L49_L4AXX    0x461
 104 #define DEVID_STM32L45_L46XX    0x462
 105 #define DEVID_STM32L41_L42XX    0x464
 106 #define DEVID_STM32G03_G04XX    0x466
 107 #define DEVID_STM32G0B_G0CXX    0x467
 108 #define DEVID_STM32G43_G44XX    0x468
 109 #define DEVID_STM32G47_G48XX    0x469
 110 #define DEVID_STM32L4R_L4SXX    0x470
 111 #define DEVID_STM32L4P_L4QXX    0x471
 112 #define DEVID_STM32L55_L56XX    0x472
 113 #define DEVID_STM32G49_G4AXX    0x479
 114 #define DEVID_STM32U57_U58XX    0x482
 115 #define DEVID_STM32WB1XX                0x494
 116 #define DEVID_STM32WB5XX                0x495
 117 #define DEVID_STM32WB3XX                0x496
 118 #define DEVID_STM32WLE_WL5XX    0x497
 119
 120 /* known Flash base addresses */
 121 #define STM32_FLASH_BANK_BASE   0x08000000
 122 #define STM32_FLASH_S_BANK_BASE 0x0C000000
 123
 124 /* offset between non-secure and secure flash registers */
 125 #define STM32L5_REGS_SEC_OFFSET 0x10000000
 126
 127 /* 100 bytes as loader stack should be large enough for the loader to operate */
 128 #define LDR_STACK_SIZE                  100
 129
 130 struct stm32l4_work_area {
 131         struct stm32l4_loader_params {
 132                 uint32_t flash_sr_addr;
 133                 uint32_t flash_cr_addr;
 134                 uint32_t flash_word_size;
 135                 uint32_t flash_sr_bsy_mask;
 136         } params;
 137         uint8_t stack[LDR_STACK_SIZE];
 138         struct flash_async_algorithm_circbuf {
 139                 uint8_t *wp;
 140                 uint8_t *rp;
 141                 uint8_t *buf;
 142         } fifo;
 143 };
 144
 145 #endif