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   1 /***************************************************************************
   2  *   Copyright (C) 2015 by Uwe Bonnes                                      *
   3  *   bon@elektron.ikp.physik.tu-darmstadt.de                               *
   4  *                                                                         *
   5  *   Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics           *
   6  *   tarek.bouchkati@gmail.com                                             *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  20  ***************************************************************************/
  21
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "imp.h"
  27 #include <helper/binarybuffer.h>
  28 #include <target/algorithm.h>
  29 #include <target/armv7m.h>
  30 #include "bits.h"
  31
  32 /* STM32L4xxx series for reference.
  33  *
  34  * RM0351 (STM32L4x5/STM32L4x6)
  35  * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
  36  *
  37  * RM0394 (STM32L43x/44x/45x/46x)
  38  * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
  39  *
  40  * RM0432 (STM32L4R/4Sxx)
  41  * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
  42  *
  43  * STM32L476RG Datasheet (for erase timing)
  44  * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
  45  *
  46  * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
  47  * an option byte is available to map all sectors to the first bank.
  48  * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
  49  * handlers do!
  50  *
  51  * RM0394 devices have a single bank only.
  52  *
  53  * RM0432 devices have single and dual bank operating modes.
  54  * The FLASH size is 1Mbyte or 2Mbyte.
  55  * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
  56  *
  57  * Bank mode is controlled by two different bits in option bytes register.
  58  * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
  59  * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
  60  *
  61  */
  62
  63 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
  64
  65 #define FLASH_ERASE_TIMEOUT 250
  66
  67 /* Flash registers offsets */
  68 #define STM32_FLASH_ACR     0x00
  69 #define STM32_FLASH_KEYR    0x08
  70 #define STM32_FLASH_OPTKEYR 0x0c
  71 #define STM32_FLASH_SR      0x10
  72 #define STM32_FLASH_CR      0x14
  73 #define STM32_FLASH_OPTR    0x20
  74 #define STM32_FLASH_WRP1AR  0x2c
  75 #define STM32_FLASH_WRP1BR  0x30
  76 #define STM32_FLASH_WRP2AR  0x4c
  77 #define STM32_FLASH_WRP2BR  0x50
  78
  79 /* FLASH_CR register bits */
  80 #define FLASH_PG        (1 << 0)
  81 #define FLASH_PER       (1 << 1)
  82 #define FLASH_MER1      (1 << 2)
  83 #define FLASH_PAGE_SHIFT      3
  84 #define FLASH_CR_BKER   (1 << 11)
  85 #define FLASH_MER2      (1 << 15)
  86 #define FLASH_STRT      (1 << 16)
  87 #define FLASH_OPTSTRT   (1 << 17)
  88 #define FLASH_EOPIE     (1 << 24)
  89 #define FLASH_ERRIE     (1 << 25)
  90 #define FLASH_OBLLAUNCH (1 << 27)
  91 #define FLASH_OPTLOCK   (1 << 30)
  92 #define FLASH_LOCK      (1 << 31)
  93
  94 /* FLASH_SR register bits */
  95 #define FLASH_BSY      (1 << 16)
  96 /* Fast programming not used => related errors not used*/
  97 #define FLASH_PGSERR   (1 << 7) /* Programming sequence error */
  98 #define FLASH_SIZERR   (1 << 6) /* Size error */
  99 #define FLASH_PGAERR   (1 << 5) /* Programming alignment error */
 100 #define FLASH_WRPERR   (1 << 4) /* Write protection error */
 101 #define FLASH_PROGERR  (1 << 3) /* Programming error */
 102 #define FLASH_OPERR    (1 << 1) /* Operation error */
 103 #define FLASH_EOP      (1 << 0) /* End of operation */
 104 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
 105
 106 /* register unlock keys */
 107 #define KEY1           0x45670123
 108 #define KEY2           0xCDEF89AB
 109
 110 /* option register unlock key */
 111 #define OPTKEY1        0x08192A3B
 112 #define OPTKEY2        0x4C5D6E7F
 113
 114 #define RDP_LEVEL_0        0xAA
 115 #define RDP_LEVEL_1        0xBB
 116 #define RDP_LEVEL_2        0xCC
 117
 118
 119 /* other registers */
 120 #define DBGMCU_IDCODE   0xE0042000
 121
 122
 123 struct stm32l4_rev {
 124         const uint16_t rev;
 125         const char *str;
 126 };
 127
 128 struct stm32l4_part_info {
 129         uint16_t id;
 130         const char *device_str;
 131         const struct stm32l4_rev *revs;
 132         const size_t num_revs;
 133         const uint16_t max_flash_size_kb;
 134         const bool has_dual_bank;
 135         const uint32_t flash_regs_base;
 136         const uint32_t fsize_addr;
 137 };
 138
 139 struct stm32l4_flash_bank {
 140         int probed;
 141         uint32_t idcode;
 142         int bank1_sectors;
 143         bool dual_bank_mode;
 144         int hole_sectors;
 145         const struct stm32l4_part_info *part_info;
 146 };
 147
 148 static const struct stm32l4_rev stm32_415_revs[] = {
 149         { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
 150 };
 151
 152 static const struct stm32l4_rev stm32_435_revs[] = {
 153         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
 154 };
 155
 156 static const struct stm32l4_rev stm32_461_revs[] = {
 157         { 0x1000, "A" }, { 0x2000, "B" },
 158 };
 159
 160 static const struct stm32l4_rev stm32_462_revs[] = {
 161                 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
 162 };
 163
 164 static const struct stm32l4_rev stm32_470_revs[] = {
 165         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
 166 };
 167
 168 static const struct stm32l4_part_info stm32l4_parts[] = {
 169         {
 170           .id                    = 0x415,
 171           .revs                  = stm32_415_revs,
 172           .num_revs              = ARRAY_SIZE(stm32_415_revs),
 173           .device_str            = "STM32L47/L48xx",
 174           .max_flash_size_kb     = 1024,
 175           .has_dual_bank         = true,
 176           .flash_regs_base       = 0x40022000,
 177           .fsize_addr            = 0x1FFF75E0,
 178         },
 179         {
 180           .id                    = 0x435,
 181           .revs                  = stm32_435_revs,
 182           .num_revs              = ARRAY_SIZE(stm32_435_revs),
 183           .device_str            = "STM32L43/L44xx",
 184           .max_flash_size_kb     = 256,
 185           .has_dual_bank         = false,
 186           .flash_regs_base       = 0x40022000,
 187           .fsize_addr            = 0x1FFF75E0,
 188         },
 189         {
 190           .id                    = 0x461,
 191           .revs                  = stm32_461_revs,
 192           .num_revs              = ARRAY_SIZE(stm32_461_revs),
 193           .device_str            = "STM32L49/L4Axx",
 194           .max_flash_size_kb     = 1024,
 195           .has_dual_bank         = true,
 196           .flash_regs_base       = 0x40022000,
 197           .fsize_addr            = 0x1FFF75E0,
 198         },
 199         {
 200           .id                    = 0x462,
 201           .revs                  = stm32_462_revs,
 202           .num_revs              = ARRAY_SIZE(stm32_462_revs),
 203           .device_str            = "STM32L45/L46xx",
 204           .max_flash_size_kb     = 512,
 205           .has_dual_bank         = false,
 206           .flash_regs_base       = 0x40022000,
 207           .fsize_addr            = 0x1FFF75E0,
 208         },
 209         {
 210           .id                    = 0x470,
 211           .revs                  = stm32_470_revs,
 212           .num_revs              = ARRAY_SIZE(stm32_470_revs),
 213           .device_str            = "STM32L4R/L4Sxx",
 214           .max_flash_size_kb     = 2048,
 215           .has_dual_bank         = true,
 216           .flash_regs_base       = 0x40022000,
 217           .fsize_addr            = 0x1FFF75E0,
 218         },
 219 };
 220
 221 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
 222 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
 223 {
 224         struct stm32l4_flash_bank *stm32l4_info;
 225
 226         if (CMD_ARGC < 6)
 227                 return ERROR_COMMAND_SYNTAX_ERROR;
 228
 229         stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
 230         if (!stm32l4_info)
 231                 return ERROR_FAIL; /* Checkme: What better error to use?*/
 232         bank->driver_priv = stm32l4_info;
 233
 234         stm32l4_info->probed = 0;
 235
 236         return ERROR_OK;
 237 }
 238
 239 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
 240 {
 241         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 242         return stm32l4_info->part_info->flash_regs_base + reg_offset;
 243 }
 244
 245 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
 246 {
 247         return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
 248 }
 249
 250 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
 251 {
 252         return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
 253 }
 254
 255 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
 256 {
 257         uint32_t status;
 258         int retval = ERROR_OK;
 259
 260         /* wait for busy to clear */
 261         for (;;) {
 262                 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_SR, &status);
 263                 if (retval != ERROR_OK)
 264                         return retval;
 265                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 266                 if ((status & FLASH_BSY) == 0)
 267                         break;
 268                 if (timeout-- <= 0) {
 269                         LOG_ERROR("timed out waiting for flash");
 270                         return ERROR_FAIL;
 271                 }
 272                 alive_sleep(1);
 273         }
 274
 275
 276         if (status & FLASH_WRPERR) {
 277                 LOG_ERROR("stm32x device protected");
 278                 retval = ERROR_FAIL;
 279         }
 280
 281         /* Clear but report errors */
 282         if (status & FLASH_ERROR) {
 283                 if (retval == ERROR_OK)
 284                         retval = ERROR_FAIL;
 285                 /* If this operation fails, we ignore it and report the original
 286                  * retval
 287                  */
 288                 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, status & FLASH_ERROR);
 289         }
 290
 291         return retval;
 292 }
 293
 294 static int stm32l4_unlock_reg(struct flash_bank *bank)
 295 {
 296         uint32_t ctrl;
 297
 298         /* first check if not already unlocked
 299          * otherwise writing on STM32_FLASH_KEYR will fail
 300          */
 301         int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
 302         if (retval != ERROR_OK)
 303                 return retval;
 304
 305         if ((ctrl & FLASH_LOCK) == 0)
 306                 return ERROR_OK;
 307
 308         /* unlock flash registers */
 309         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY1);
 310         if (retval != ERROR_OK)
 311                 return retval;
 312
 313         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY2);
 314         if (retval != ERROR_OK)
 315                 return retval;
 316
 317         retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
 318         if (retval != ERROR_OK)
 319                 return retval;
 320
 321         if (ctrl & FLASH_LOCK) {
 322                 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
 323                 return ERROR_TARGET_FAILURE;
 324         }
 325
 326         return ERROR_OK;
 327 }
 328
 329 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
 330 {
 331         uint32_t ctrl;
 332
 333         int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
 334         if (retval != ERROR_OK)
 335                 return retval;
 336
 337         if ((ctrl & FLASH_OPTLOCK) == 0)
 338                 return ERROR_OK;
 339
 340         /* unlock option registers */
 341         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY1);
 342         if (retval != ERROR_OK)
 343                 return retval;
 344
 345         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY2);
 346         if (retval != ERROR_OK)
 347                 return retval;
 348
 349         retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
 350         if (retval != ERROR_OK)
 351                 return retval;
 352
 353         if (ctrl & FLASH_OPTLOCK) {
 354                 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
 355                 return ERROR_TARGET_FAILURE;
 356         }
 357
 358         return ERROR_OK;
 359 }
 360
 361 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
 362 {
 363         uint32_t optiondata;
 364
 365         int retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
 366         if (retval != ERROR_OK)
 367                 return retval;
 368
 369         retval = stm32l4_unlock_reg(bank);
 370         if (retval != ERROR_OK)
 371                 return retval;
 372
 373         retval = stm32l4_unlock_option_reg(bank);
 374         if (retval != ERROR_OK)
 375                 return retval;
 376
 377         optiondata = (optiondata & ~mask) | (value & mask);
 378
 379         retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
 380         if (retval != ERROR_OK)
 381                 return retval;
 382
 383         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OPTSTRT);
 384         if (retval != ERROR_OK)
 385                 return retval;
 386
 387         retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 388         if (retval != ERROR_OK)
 389                 return retval;
 390
 391         return retval;
 392 }
 393
 394 static int stm32l4_protect_check(struct flash_bank *bank)
 395 {
 396         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 397
 398         uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
 399         stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar);
 400         stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br);
 401         stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
 402         stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
 403
 404         const uint8_t wrp1a_start = wrp1ar & 0xFF;
 405         const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
 406         const uint8_t wrp1b_start = wrp1br & 0xFF;
 407         const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
 408         const uint8_t wrp2a_start = wrp2ar & 0xFF;
 409         const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
 410         const uint8_t wrp2b_start = wrp2br & 0xFF;
 411         const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
 412
 413         for (int i = 0; i < bank->num_sectors; i++) {
 414                 if (i < stm32l4_info->bank1_sectors) {
 415                         if (((i >= wrp1a_start) &&
 416                                  (i <= wrp1a_end)) ||
 417                                 ((i >= wrp1b_start) &&
 418                                  (i <= wrp1b_end)))
 419                                 bank->sectors[i].is_protected = 1;
 420                         else
 421                                 bank->sectors[i].is_protected = 0;
 422                 } else {
 423                         uint8_t snb;
 424                         snb = i - stm32l4_info->bank1_sectors;
 425                         if (((snb >= wrp2a_start) &&
 426                                  (snb <= wrp2a_end)) ||
 427                                 ((snb >= wrp2b_start) &&
 428                                  (snb <= wrp2b_end)))
 429                                 bank->sectors[i].is_protected = 1;
 430                         else
 431                                 bank->sectors[i].is_protected = 0;
 432                 }
 433         }
 434         return ERROR_OK;
 435 }
 436
 437 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
 438 {
 439         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 440         int i;
 441         int retval;
 442
 443         assert(first < bank->num_sectors);
 444         assert(last < bank->num_sectors);
 445
 446         if (bank->target->state != TARGET_HALTED) {
 447                 LOG_ERROR("Target not halted");
 448                 return ERROR_TARGET_NOT_HALTED;
 449         }
 450
 451         retval = stm32l4_unlock_reg(bank);
 452         if (retval != ERROR_OK)
 453                 return retval;
 454
 455         /*
 456         Sector Erase
 457         To erase a sector, follow the procedure below:
 458         1. Check that no Flash memory operation is ongoing by
 459        checking the BSY bit in the FLASH_SR register
 460         2. Set the PER bit and select the page and bank
 461            you wish to erase in the FLASH_CR register
 462         3. Set the STRT bit in the FLASH_CR register
 463         4. Wait for the BSY bit to be cleared
 464          */
 465
 466         for (i = first; i <= last; i++) {
 467                 uint32_t erase_flags;
 468                 erase_flags = FLASH_PER | FLASH_STRT;
 469
 470                 if (i >= stm32l4_info->bank1_sectors) {
 471                         uint8_t snb;
 472                         snb = i - stm32l4_info->bank1_sectors;
 473                         erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
 474                 } else
 475                         erase_flags |= i << FLASH_PAGE_SHIFT;
 476                 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, erase_flags);
 477                 if (retval != ERROR_OK)
 478                         return retval;
 479
 480                 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 481                 if (retval != ERROR_OK)
 482                         return retval;
 483
 484                 bank->sectors[i].is_erased = 1;
 485         }
 486
 487         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
 488         if (retval != ERROR_OK)
 489                 return retval;
 490
 491         return ERROR_OK;
 492 }
 493
 494 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
 495 {
 496         struct target *target = bank->target;
 497         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 498
 499         if (target->state != TARGET_HALTED) {
 500                 LOG_ERROR("Target not halted");
 501                 return ERROR_TARGET_NOT_HALTED;
 502         }
 503
 504         int ret = ERROR_OK;
 505         /* Bank 2 */
 506         uint32_t reg_value = 0xFF; /* Default to bank un-protected */
 507         if (last >= stm32l4_info->bank1_sectors) {
 508                 if (set == 1) {
 509                         uint8_t begin = first > stm32l4_info->bank1_sectors ? first : 0x00;
 510                         reg_value = ((last & 0xFF) << 16) | begin;
 511                 }
 512
 513                 ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
 514         }
 515         /* Bank 1 */
 516         reg_value = 0xFF; /* Default to bank un-protected */
 517         if (first < stm32l4_info->bank1_sectors) {
 518                 if (set == 1) {
 519                         uint8_t end = last >= stm32l4_info->bank1_sectors ? 0xFF : last;
 520                         reg_value = (end << 16) | (first & 0xFF);
 521                 }
 522
 523                 ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
 524         }
 525
 526         return ret;
 527 }
 528
 529 /* Count is in halfwords */
 530 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
 531                 uint32_t offset, uint32_t count)
 532 {
 533         struct target *target = bank->target;
 534         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 535         uint32_t buffer_size = 16384;
 536         struct working_area *write_algorithm;
 537         struct working_area *source;
 538         uint32_t address = bank->base + offset;
 539         struct reg_param reg_params[5];
 540         struct armv7m_algorithm armv7m_info;
 541         int retval = ERROR_OK;
 542
 543         static const uint8_t stm32l4_flash_write_code[] = {
 544 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
 545         };
 546
 547         if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
 548                         &write_algorithm) != ERROR_OK) {
 549                 LOG_WARNING("no working area available, can't do block memory writes");
 550                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 551         }
 552
 553         retval = target_write_buffer(target, write_algorithm->address,
 554                         sizeof(stm32l4_flash_write_code),
 555                         stm32l4_flash_write_code);
 556         if (retval != ERROR_OK) {
 557                 target_free_working_area(target, write_algorithm);
 558                 return retval;
 559         }
 560
 561         /* memory buffer */
 562         while (target_alloc_working_area_try(target, buffer_size, &source) !=
 563                    ERROR_OK) {
 564                 buffer_size /= 2;
 565                 if (buffer_size <= 256) {
 566                         /* we already allocated the writing code, but failed to get a
 567                          * buffer, free the algorithm */
 568                         target_free_working_area(target, write_algorithm);
 569
 570                         LOG_WARNING("large enough working area not available, can't do block memory writes");
 571                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 572                 }
 573         }
 574
 575         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 576         armv7m_info.core_mode = ARM_MODE_THREAD;
 577
 578         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
 579         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* buffer end */
 580         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* target address */
 581         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* count (double word-64bit) */
 582         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);    /* flash base */
 583
 584         buf_set_u32(reg_params[0].value, 0, 32, source->address);
 585         buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
 586         buf_set_u32(reg_params[2].value, 0, 32, address);
 587         buf_set_u32(reg_params[3].value, 0, 32, count / 4);
 588         buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base);
 589
 590         retval = target_run_flash_async_algorithm(target, buffer, count, 2,
 591                         0, NULL,
 592                         5, reg_params,
 593                         source->address, source->size,
 594                         write_algorithm->address, 0,
 595                         &armv7m_info);
 596
 597         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 598                 LOG_ERROR("error executing stm32l4 flash write algorithm");
 599
 600                 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
 601
 602                 if (error & FLASH_WRPERR)
 603                         LOG_ERROR("flash memory write protected");
 604
 605                 if (error != 0) {
 606                         LOG_ERROR("flash write failed = %08" PRIx32, error);
 607                         /* Clear but report errors */
 608                         stm32l4_write_flash_reg(bank, STM32_FLASH_SR, error);
 609                         retval = ERROR_FAIL;
 610                 }
 611         }
 612
 613         target_free_working_area(target, source);
 614         target_free_working_area(target, write_algorithm);
 615
 616         destroy_reg_param(&reg_params[0]);
 617         destroy_reg_param(&reg_params[1]);
 618         destroy_reg_param(&reg_params[2]);
 619         destroy_reg_param(&reg_params[3]);
 620         destroy_reg_param(&reg_params[4]);
 621
 622         return retval;
 623 }
 624
 625 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
 626                 uint32_t offset, uint32_t count)
 627 {
 628         int retval;
 629
 630         if (bank->target->state != TARGET_HALTED) {
 631                 LOG_ERROR("Target not halted");
 632                 return ERROR_TARGET_NOT_HALTED;
 633         }
 634
 635         if (offset & 0x7) {
 636                 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment",
 637                                         offset);
 638                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 639         }
 640
 641         if (count & 0x7) {
 642                 LOG_WARNING("Padding %d bytes to keep 8-byte write size",
 643                                         count & 7);
 644                 count = (count + 7) & ~7;
 645                 /* This pads the write chunk with random bytes by overrunning the
 646                  * write buffer. Padding with the erased pattern 0xff is purely
 647                  * cosmetical, as 8-byte flash words are ECC secured and the first
 648                  * write will program the ECC bits. A second write would need
 649                  * to reprogramm these ECC bits.
 650                  * But this can only be done after erase!
 651                  */
 652         }
 653
 654         retval = stm32l4_unlock_reg(bank);
 655         if (retval != ERROR_OK)
 656                 return retval;
 657
 658         /* Only full double words (8-byte) can be programmed*/
 659         retval = stm32l4_write_block(bank, buffer, offset, count / 2);
 660         if (retval != ERROR_OK) {
 661                 LOG_WARNING("block write failed");
 662                 return retval;
 663         }
 664
 665         LOG_WARNING("block write succeeded");
 666         return stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
 667 }
 668
 669 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
 670 {
 671         int retval = target_read_u32(bank->target, DBGMCU_IDCODE, id);
 672         if (retval != ERROR_OK)
 673                 return retval;
 674
 675         return retval;
 676 }
 677
 678 static int stm32l4_probe(struct flash_bank *bank)
 679 {
 680         struct target *target = bank->target;
 681         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 682         const struct stm32l4_part_info *part_info;
 683         int i;
 684         uint16_t flash_size_in_kb = 0xffff;
 685         uint32_t device_id;
 686         uint32_t options;
 687
 688         stm32l4_info->probed = 0;
 689
 690         /* read stm32 device id register */
 691         int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
 692         if (retval != ERROR_OK)
 693                 return retval;
 694
 695         device_id = stm32l4_info->idcode & 0xFFF;
 696
 697         for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
 698                 if (device_id == stm32l4_parts[n].id)
 699                         stm32l4_info->part_info = &stm32l4_parts[n];
 700         }
 701
 702         if (!stm32l4_info->part_info) {
 703                 LOG_WARNING("Cannot identify target as an STM32L4 family device.");
 704                 return ERROR_FAIL;
 705         }
 706
 707         part_info = stm32l4_info->part_info;
 708
 709         char device_info[1024];
 710         retval = bank->driver->info(bank, device_info, sizeof(device_info));
 711         if (retval != ERROR_OK)
 712                 return retval;
 713
 714         LOG_INFO("device idcode = 0x%08" PRIx32 " (%s)", stm32l4_info->idcode, device_info);
 715
 716         /* get flash size from target. */
 717         retval = target_read_u16(target, part_info->fsize_addr, &flash_size_in_kb);
 718
 719         /* failed reading flash size or flash size invalid (early silicon),
 720          * default to max target family */
 721         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0
 722                         || flash_size_in_kb > part_info->max_flash_size_kb) {
 723                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 724                         part_info->max_flash_size_kb);
 725                 flash_size_in_kb = part_info->max_flash_size_kb;
 726         }
 727
 728         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 729
 730         /* did we assign a flash size? */
 731         assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
 732
 733         /* read flash option register */
 734         retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options);
 735         if (retval != ERROR_OK)
 736                 return retval;
 737
 738         stm32l4_info->bank1_sectors = 0;
 739         stm32l4_info->hole_sectors = 0;
 740
 741         int num_pages = 0;
 742         int page_size = 0;
 743
 744         stm32l4_info->dual_bank_mode = false;
 745
 746         switch (device_id) {
 747         case 0x415:
 748         case 0x461:
 749                 /* if flash size is max (1M) the device is always dual bank
 750                  * 0x415: has variants with 512K
 751                  * 0x461: has variants with 512 and 256
 752                  * for these variants:
 753                  *   if DUAL_BANK = 0 -> single bank
 754                  *   else -> dual bank without gap
 755                  * note: the page size is invariant
 756                  */
 757                 page_size = 2048;
 758                 num_pages = flash_size_in_kb / 2;
 759                 stm32l4_info->bank1_sectors = num_pages;
 760
 761                 /* check DUAL_BANK bit[21] if the flash is less than 1M */
 762                 if (flash_size_in_kb == 1024 || (options & BIT(21))) {
 763                         stm32l4_info->dual_bank_mode = true;
 764                         stm32l4_info->bank1_sectors = num_pages / 2;
 765                 }
 766                 break;
 767         case 0x435:
 768         case 0x462:
 769                 /* single bank flash */
 770                 page_size = 2048;
 771                 num_pages = flash_size_in_kb / 2;
 772                 stm32l4_info->bank1_sectors = num_pages;
 773                 break;
 774         case 0x470:
 775                 /* STM32L4R/S can be single/dual bank:
 776                  *   if size = 2M check DBANK bit(22)
 777                  *   if size = 1M check DB1M bit(21)
 778                  * in single bank configuration the page size is 8K
 779                  * else (dual bank) the page size is 4K without gap between banks
 780                  */
 781                 page_size = 8192;
 782                 num_pages = flash_size_in_kb / 8;
 783                 stm32l4_info->bank1_sectors = num_pages;
 784                 if ((flash_size_in_kb == 2048 && (options & BIT(22))) ||
 785                         (flash_size_in_kb == 1024 && (options & BIT(21)))) {
 786                         stm32l4_info->dual_bank_mode = true;
 787                         page_size = 4096;
 788                         num_pages = flash_size_in_kb / 4;
 789                         stm32l4_info->bank1_sectors = num_pages / 2;
 790                 }
 791                 break;
 792         default:
 793                 LOG_ERROR("unsupported device");
 794                 return ERROR_FAIL;
 795         }
 796
 797         LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
 798
 799         const int gap_size = stm32l4_info->hole_sectors * page_size;
 800
 801         if (stm32l4_info->dual_bank_mode & gap_size) {
 802                 LOG_INFO("gap detected starting from %0x08" PRIx32 " to %0x08" PRIx32,
 803                                 0x8000000 + stm32l4_info->bank1_sectors * page_size,
 804                                 0x8000000 + stm32l4_info->bank1_sectors * page_size + gap_size);
 805         }
 806
 807         if (bank->sectors) {
 808                 free(bank->sectors);
 809                 bank->sectors = NULL;
 810         }
 811
 812         bank->size = flash_size_in_kb * 1024 + gap_size;
 813         bank->base = 0x08000000;
 814         bank->num_sectors = num_pages;
 815         bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 816         if (bank->sectors == NULL) {
 817                 LOG_ERROR("failed to allocate bank sectors");
 818                 return ERROR_FAIL;
 819         }
 820
 821         for (i = 0; i < bank->num_sectors; i++) {
 822                 bank->sectors[i].offset = i * page_size;
 823                 /* in dual bank configuration, if there is a gap between banks
 824                  * we fix up the sector offset to consider this gap */
 825                 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
 826                         bank->sectors[i].offset += gap_size;
 827                 bank->sectors[i].size = page_size;
 828                 bank->sectors[i].is_erased = -1;
 829                 bank->sectors[i].is_protected = 1;
 830         }
 831
 832         stm32l4_info->probed = 1;
 833         return ERROR_OK;
 834 }
 835
 836 static int stm32l4_auto_probe(struct flash_bank *bank)
 837 {
 838         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 839         if (stm32l4_info->probed)
 840                 return ERROR_OK;
 841
 842         return stm32l4_probe(bank);
 843 }
 844
 845 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
 846 {
 847         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 848         const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
 849
 850         if (part_info) {
 851                 const char *rev_str = NULL;
 852                 uint16_t rev_id = stm32l4_info->idcode >> 16;
 853                 for (unsigned int i = 0; i < part_info->num_revs; i++) {
 854                         if (rev_id == part_info->revs[i].rev) {
 855                                 rev_str = part_info->revs[i].str;
 856
 857                                 if (rev_str != NULL) {
 858                                         snprintf(buf, buf_size, "%s - Rev: %s",
 859                                                         part_info->device_str, rev_str);
 860                                         return ERROR_OK;
 861                                 }
 862                         }
 863                 }
 864
 865                 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)",
 866                                 part_info->device_str, rev_id);
 867                 return ERROR_OK;
 868         } else {
 869                 snprintf(buf, buf_size, "Cannot identify target as a STM32L4x device");
 870                 return ERROR_FAIL;
 871         }
 872
 873         return ERROR_OK;
 874 }
 875
 876 static int stm32l4_mass_erase(struct flash_bank *bank)
 877 {
 878         int retval;
 879         struct target *target = bank->target;
 880         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 881
 882         uint32_t action = FLASH_MER1;
 883
 884         if (stm32l4_info->part_info->has_dual_bank)
 885                 action |= FLASH_MER2;
 886
 887         if (target->state != TARGET_HALTED) {
 888                 LOG_ERROR("Target not halted");
 889                 return ERROR_TARGET_NOT_HALTED;
 890         }
 891
 892         retval = stm32l4_unlock_reg(bank);
 893         if (retval != ERROR_OK)
 894                 return retval;
 895
 896         /* mass erase flash memory */
 897         retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
 898         if (retval != ERROR_OK)
 899                 return retval;
 900
 901         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action);
 902         if (retval != ERROR_OK)
 903                 return retval;
 904         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action | FLASH_STRT);
 905         if (retval != ERROR_OK)
 906                 return retval;
 907
 908         retval = stm32l4_wait_status_busy(bank,  FLASH_ERASE_TIMEOUT);
 909         if (retval != ERROR_OK)
 910                 return retval;
 911
 912         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
 913         if (retval != ERROR_OK)
 914                 return retval;
 915
 916         return ERROR_OK;
 917 }
 918
 919 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
 920 {
 921         int i;
 922
 923         if (CMD_ARGC < 1) {
 924                 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
 925                 return ERROR_COMMAND_SYNTAX_ERROR;
 926         }
 927
 928         struct flash_bank *bank;
 929         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 930         if (ERROR_OK != retval)
 931                 return retval;
 932
 933         retval = stm32l4_mass_erase(bank);
 934         if (retval == ERROR_OK) {
 935                 /* set all sectors as erased */
 936                 for (i = 0; i < bank->num_sectors; i++)
 937                         bank->sectors[i].is_erased = 1;
 938
 939                 command_print(CMD, "stm32l4x mass erase complete");
 940         } else {
 941                 command_print(CMD, "stm32l4x mass erase failed");
 942         }
 943
 944         return retval;
 945 }
 946
 947 COMMAND_HANDLER(stm32l4_handle_option_read_command)
 948 {
 949         if (CMD_ARGC < 2) {
 950                 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
 951                 return ERROR_COMMAND_SYNTAX_ERROR;
 952         }
 953
 954         struct flash_bank *bank;
 955         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 956         if (ERROR_OK != retval)
 957                 return retval;
 958
 959         uint32_t reg_offset, reg_addr;
 960         uint32_t value = 0;
 961
 962         reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
 963         reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
 964
 965         retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
 966         if (ERROR_OK != retval)
 967                 return retval;
 968
 969         command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
 970
 971         return retval;
 972 }
 973
 974 COMMAND_HANDLER(stm32l4_handle_option_write_command)
 975 {
 976         if (CMD_ARGC < 3) {
 977                 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
 978                 return ERROR_COMMAND_SYNTAX_ERROR;
 979         }
 980
 981         struct flash_bank *bank;
 982         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 983         if (ERROR_OK != retval)
 984                 return retval;
 985
 986         uint32_t reg_offset;
 987         uint32_t value = 0;
 988         uint32_t mask = 0xFFFFFFFF;
 989
 990         reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
 991         value = strtoul(CMD_ARGV[2], NULL, 16);
 992         if (CMD_ARGC > 3)
 993                 mask = strtoul(CMD_ARGV[3], NULL, 16);
 994
 995         command_print(CMD, "%s Option written.\n"
 996                                 "INFO: a reset or power cycle is required "
 997                                 "for the new settings to take effect.", bank->driver->name);
 998
 999         retval = stm32l4_write_option(bank, reg_offset, value, mask);
1000         return retval;
1001 }
1002
1003 COMMAND_HANDLER(stm32l4_handle_option_load_command)
1004 {
1005         if (CMD_ARGC < 1)
1006                 return ERROR_COMMAND_SYNTAX_ERROR;
1007
1008         struct flash_bank *bank;
1009         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1010         if (ERROR_OK != retval)
1011                 return retval;
1012
1013         retval = stm32l4_unlock_reg(bank);
1014         if (ERROR_OK != retval)
1015                 return retval;
1016
1017         retval = stm32l4_unlock_option_reg(bank);
1018         if (ERROR_OK != retval)
1019                 return retval;
1020
1021         /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
1022         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBLLAUNCH);
1023
1024         command_print(CMD, "stm32l4x option load (POR) completed.");
1025         return retval;
1026 }
1027
1028 COMMAND_HANDLER(stm32l4_handle_lock_command)
1029 {
1030         struct target *target = NULL;
1031
1032         if (CMD_ARGC < 1)
1033                 return ERROR_COMMAND_SYNTAX_ERROR;
1034
1035         struct flash_bank *bank;
1036         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1037         if (ERROR_OK != retval)
1038                 return retval;
1039
1040         target = bank->target;
1041
1042         if (target->state != TARGET_HALTED) {
1043                 LOG_ERROR("Target not halted");
1044                 return ERROR_TARGET_NOT_HALTED;
1045         }
1046
1047         /* set readout protection level 1 by erasing the RDP option byte */
1048         if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
1049                 command_print(CMD, "%s failed to lock device", bank->driver->name);
1050                 return ERROR_OK;
1051         }
1052
1053         return ERROR_OK;
1054 }
1055
1056 COMMAND_HANDLER(stm32l4_handle_unlock_command)
1057 {
1058         struct target *target = NULL;
1059
1060         if (CMD_ARGC < 1)
1061                 return ERROR_COMMAND_SYNTAX_ERROR;
1062
1063         struct flash_bank *bank;
1064         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1065         if (ERROR_OK != retval)
1066                 return retval;
1067
1068         target = bank->target;
1069
1070         if (target->state != TARGET_HALTED) {
1071                 LOG_ERROR("Target not halted");
1072                 return ERROR_TARGET_NOT_HALTED;
1073         }
1074
1075         if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
1076                 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1077                 return ERROR_OK;
1078         }
1079
1080         return ERROR_OK;
1081 }
1082
1083 static const struct command_registration stm32l4_exec_command_handlers[] = {
1084         {
1085                 .name = "lock",
1086                 .handler = stm32l4_handle_lock_command,
1087                 .mode = COMMAND_EXEC,
1088                 .usage = "bank_id",
1089                 .help = "Lock entire flash device.",
1090         },
1091         {
1092                 .name = "unlock",
1093                 .handler = stm32l4_handle_unlock_command,
1094                 .mode = COMMAND_EXEC,
1095                 .usage = "bank_id",
1096                 .help = "Unlock entire protected flash device.",
1097         },
1098         {
1099                 .name = "mass_erase",
1100                 .handler = stm32l4_handle_mass_erase_command,
1101                 .mode = COMMAND_EXEC,
1102                 .usage = "bank_id",
1103                 .help = "Erase entire flash device.",
1104         },
1105         {
1106                 .name = "option_read",
1107                 .handler = stm32l4_handle_option_read_command,
1108                 .mode = COMMAND_EXEC,
1109                 .usage = "bank_id reg_offset",
1110                 .help = "Read & Display device option bytes.",
1111         },
1112         {
1113                 .name = "option_write",
1114                 .handler = stm32l4_handle_option_write_command,
1115                 .mode = COMMAND_EXEC,
1116                 .usage = "bank_id reg_offset value mask",
1117                 .help = "Write device option bit fields with provided value.",
1118         },
1119         {
1120                 .name = "option_load",
1121                 .handler = stm32l4_handle_option_load_command,
1122                 .mode = COMMAND_EXEC,
1123                 .usage = "bank_id",
1124                 .help = "Force re-load of device options (will cause device reset).",
1125         },
1126         COMMAND_REGISTRATION_DONE
1127 };
1128
1129 static const struct command_registration stm32l4_command_handlers[] = {
1130         {
1131                 .name = "stm32l4x",
1132                 .mode = COMMAND_ANY,
1133                 .help = "stm32l4x flash command group",
1134                 .usage = "",
1135                 .chain = stm32l4_exec_command_handlers,
1136         },
1137         COMMAND_REGISTRATION_DONE
1138 };
1139
1140 const struct flash_driver stm32l4x_flash = {
1141         .name = "stm32l4x",
1142         .commands = stm32l4_command_handlers,
1143         .flash_bank_command = stm32l4_flash_bank_command,
1144         .erase = stm32l4_erase,
1145         .protect = stm32l4_protect,
1146         .write = stm32l4_write,
1147         .read = default_flash_read,
1148         .probe = stm32l4_probe,
1149         .auto_probe = stm32l4_auto_probe,
1150         .erase_check = default_flash_blank_check,
1151         .protect_check = stm32l4_protect_check,
1152         .info = get_stm32l4_info,
1153         .free_driver_priv = default_flash_free_driver_priv,
1154 };