1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
27 #include <helper/align.h>
28 #include <helper/binarybuffer.h>
29 #include <helper/bits.h>
30 #include <target/algorithm.h>
31 #include <target/arm_adi_v5.h>
32 #include <target/cortex_m.h>
35 /* STM32L4xxx series for reference.
37 * RM0351 (STM32L4x5/STM32L4x6)
38 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
40 * RM0394 (STM32L43x/44x/45x/46x)
41 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
43 * RM0432 (STM32L4R/4Sxx)
44 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
46 * STM32L476RG Datasheet (for erase timing)
47 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
49 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
50 * an option byte is available to map all sectors to the first bank.
51 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
54 * RM0394 devices have a single bank only.
56 * RM0432 devices have single and dual bank operating modes.
57 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
58 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
59 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
61 * Bank mode is controlled by two different bits in option bytes register.
63 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
64 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
66 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
67 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
70 /* STM32WBxxx series for reference.
72 * RM0434 (STM32WB55/WB35x)
73 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
75 * RM0471 (STM32WB50/WB30x)
76 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
79 * http://www.st.com/resource/en/reference_manual/dm00649196.pdf
82 * http://www.st.com/resource/en/reference_manual/dm00689203.pdf
85 /* STM32WLxxx series for reference.
88 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
91 * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
94 /* STM32G0xxx series for reference.
97 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
100 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
103 /* STM32G4xxx series for reference.
105 * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
106 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
108 * Cat. 2 devices have single bank only, page size is 2kByte.
110 * Cat. 3 devices have single and dual bank operating modes,
111 * Page size is 2kByte (dual mode) or 4kByte (single mode).
113 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
114 * Both banks are treated as a single OpenOCD bank.
116 * Cat. 4 devices have single bank only, page size is 2kByte.
119 /* STM32L5xxx series for reference.
121 * RM0428 (STM32L552xx/STM32L562xx)
122 * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
125 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
127 #define FLASH_ERASE_TIMEOUT 250
128 #define FLASH_WRITE_TIMEOUT 50
131 /* relevant STM32L4 flags ****************************************************/
133 /* this flag indicates if the device flash is with dual bank architecture */
134 #define F_HAS_DUAL_BANK BIT(0)
135 /* this flags is used for dual bank devices only, it indicates if the
136 * 4 WRPxx are usable if the device is configured in single-bank mode */
137 #define F_USE_ALL_WRPXX BIT(1)
138 /* this flag indicates if the device embeds a TrustZone security feature */
139 #define F_HAS_TZ BIT(2)
140 /* this flag indicates if the device has the same flash registers as STM32L5 */
141 #define F_HAS_L5_FLASH_REGS BIT(3)
142 /* this flag indicates that programming should be done in quad-word
143 * the default programming word size is double-word */
144 #define F_QUAD_WORD_PROG BIT(4)
145 /* end of STM32L4 flags ******************************************************/
148 enum stm32l4_flash_reg_index {
149 STM32_FLASH_ACR_INDEX,
150 STM32_FLASH_KEYR_INDEX,
151 STM32_FLASH_OPTKEYR_INDEX,
152 STM32_FLASH_SR_INDEX,
153 STM32_FLASH_CR_INDEX,
154 /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
155 * so it uses the C2CR for flash operations and CR for checking locks and locking */
156 STM32_FLASH_CR_WLK_INDEX, /* FLASH_CR_WITH_LOCK */
157 STM32_FLASH_OPTR_INDEX,
158 STM32_FLASH_WRP1AR_INDEX,
159 STM32_FLASH_WRP1BR_INDEX,
160 STM32_FLASH_WRP2AR_INDEX,
161 STM32_FLASH_WRP2BR_INDEX,
162 STM32_FLASH_REG_INDEX_NUM,
167 RDP_LEVEL_0_5 = 0x55, /* for devices with TrustZone enabled */
172 static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
173 [STM32_FLASH_ACR_INDEX] = 0x000,
174 [STM32_FLASH_KEYR_INDEX] = 0x008,
175 [STM32_FLASH_OPTKEYR_INDEX] = 0x00C,
176 [STM32_FLASH_SR_INDEX] = 0x010,
177 [STM32_FLASH_CR_INDEX] = 0x014,
178 [STM32_FLASH_OPTR_INDEX] = 0x020,
179 [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
180 [STM32_FLASH_WRP1BR_INDEX] = 0x030,
181 [STM32_FLASH_WRP2AR_INDEX] = 0x04C,
182 [STM32_FLASH_WRP2BR_INDEX] = 0x050,
185 static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
186 [STM32_FLASH_ACR_INDEX] = 0x000,
187 [STM32_FLASH_KEYR_INDEX] = 0x008,
188 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
189 [STM32_FLASH_SR_INDEX] = 0x060,
190 [STM32_FLASH_CR_INDEX] = 0x064,
191 [STM32_FLASH_CR_WLK_INDEX] = 0x014,
192 [STM32_FLASH_OPTR_INDEX] = 0x020,
193 [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
194 [STM32_FLASH_WRP1BR_INDEX] = 0x030,
197 static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
198 [STM32_FLASH_ACR_INDEX] = 0x000,
199 [STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
200 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
201 [STM32_FLASH_SR_INDEX] = 0x020, /* NSSR */
202 [STM32_FLASH_CR_INDEX] = 0x028, /* NSCR */
203 [STM32_FLASH_OPTR_INDEX] = 0x040,
204 [STM32_FLASH_WRP1AR_INDEX] = 0x058,
205 [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
206 [STM32_FLASH_WRP2AR_INDEX] = 0x068,
207 [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
210 static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
211 [STM32_FLASH_ACR_INDEX] = 0x000,
212 [STM32_FLASH_KEYR_INDEX] = 0x00C, /* SECKEYR */
213 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
214 [STM32_FLASH_SR_INDEX] = 0x024, /* SECSR */
215 [STM32_FLASH_CR_INDEX] = 0x02C, /* SECCR */
216 [STM32_FLASH_OPTR_INDEX] = 0x040,
217 [STM32_FLASH_WRP1AR_INDEX] = 0x058,
218 [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
219 [STM32_FLASH_WRP2AR_INDEX] = 0x068,
220 [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
228 struct stm32l4_part_info {
230 const char *device_str;
231 const struct stm32l4_rev *revs;
232 const size_t num_revs;
233 const uint16_t max_flash_size_kb;
234 const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
235 const uint32_t flash_regs_base;
236 const uint32_t fsize_addr;
237 const uint32_t otp_base;
238 const uint32_t otp_size;
241 struct stm32l4_flash_bank {
244 unsigned int bank1_sectors;
247 uint32_t user_bank_size;
249 uint32_t cr_bker_mask;
250 uint32_t sr_bsy_mask;
251 uint32_t wrpxxr_mask;
252 const struct stm32l4_part_info *part_info;
253 uint32_t flash_regs_base;
254 const uint32_t *flash_regs;
256 enum stm32l4_rdp rdp;
268 enum stm32l4_flash_reg_index reg_idx;
276 /* human readable list of families this drivers supports (sorted alphabetically) */
277 static const char *device_families = "STM32G0/G4/L4/L4+/L5/U5/WB/WL";
279 static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
280 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
283 static const struct stm32l4_rev stm32l43_l44xx_revs[] = {
284 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
287 static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
291 static const struct stm32l4_rev stm32_g07_g08xx_revs[] = {
292 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
295 static const struct stm32l4_rev stm32l49_l4axx_revs[] = {
296 { 0x1000, "A" }, { 0x2000, "B" },
299 static const struct stm32l4_rev stm32l45_l46xx_revs[] = {
300 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
303 static const struct stm32l4_rev stm32l41_L42xx_revs[] = {
304 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
307 static const struct stm32l4_rev stm32g03_g04xx_revs[] = {
308 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
311 static const struct stm32l4_rev stm32g0b_g0cxx_revs[] = {
315 static const struct stm32l4_rev stm32g43_g44xx_revs[] = {
316 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
319 static const struct stm32l4_rev stm32g47_g48xx_revs[] = {
320 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
323 static const struct stm32l4_rev stm32l4r_l4sxx_revs[] = {
324 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
327 static const struct stm32l4_rev stm32l4p_l4qxx_revs[] = {
331 static const struct stm32l4_rev stm32l55_l56xx_revs[] = {
332 { 0x1000, "A" }, { 0x2000, "B" },
335 static const struct stm32l4_rev stm32g49_g4axx_revs[] = {
339 static const struct stm32l4_rev stm32u57_u58xx_revs[] = {
340 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
343 static const struct stm32l4_rev stm32wb1xx_revs[] = {
344 { 0x1000, "A" }, { 0x2000, "B" },
347 static const struct stm32l4_rev stm32wb5xx_revs[] = {
351 static const struct stm32l4_rev stm32wb3xx_revs[] = {
355 static const struct stm32l4_rev stm32wle_wl5xx_revs[] = {
359 static const struct stm32l4_part_info stm32l4_parts[] = {
361 .id = DEVID_STM32L47_L48XX,
362 .revs = stm32l47_l48xx_revs,
363 .num_revs = ARRAY_SIZE(stm32l47_l48xx_revs),
364 .device_str = "STM32L47/L48xx",
365 .max_flash_size_kb = 1024,
366 .flags = F_HAS_DUAL_BANK,
367 .flash_regs_base = 0x40022000,
368 .fsize_addr = 0x1FFF75E0,
369 .otp_base = 0x1FFF7000,
373 .id = DEVID_STM32L43_L44XX,
374 .revs = stm32l43_l44xx_revs,
375 .num_revs = ARRAY_SIZE(stm32l43_l44xx_revs),
376 .device_str = "STM32L43/L44xx",
377 .max_flash_size_kb = 256,
379 .flash_regs_base = 0x40022000,
380 .fsize_addr = 0x1FFF75E0,
381 .otp_base = 0x1FFF7000,
385 .id = DEVID_STM32G05_G06XX,
386 .revs = stm32g05_g06xx_revs,
387 .num_revs = ARRAY_SIZE(stm32g05_g06xx_revs),
388 .device_str = "STM32G05/G06xx",
389 .max_flash_size_kb = 64,
391 .flash_regs_base = 0x40022000,
392 .fsize_addr = 0x1FFF75E0,
393 .otp_base = 0x1FFF7000,
397 .id = DEVID_STM32G07_G08XX,
398 .revs = stm32_g07_g08xx_revs,
399 .num_revs = ARRAY_SIZE(stm32_g07_g08xx_revs),
400 .device_str = "STM32G07/G08xx",
401 .max_flash_size_kb = 128,
403 .flash_regs_base = 0x40022000,
404 .fsize_addr = 0x1FFF75E0,
405 .otp_base = 0x1FFF7000,
409 .id = DEVID_STM32L49_L4AXX,
410 .revs = stm32l49_l4axx_revs,
411 .num_revs = ARRAY_SIZE(stm32l49_l4axx_revs),
412 .device_str = "STM32L49/L4Axx",
413 .max_flash_size_kb = 1024,
414 .flags = F_HAS_DUAL_BANK,
415 .flash_regs_base = 0x40022000,
416 .fsize_addr = 0x1FFF75E0,
417 .otp_base = 0x1FFF7000,
421 .id = DEVID_STM32L45_L46XX,
422 .revs = stm32l45_l46xx_revs,
423 .num_revs = ARRAY_SIZE(stm32l45_l46xx_revs),
424 .device_str = "STM32L45/L46xx",
425 .max_flash_size_kb = 512,
427 .flash_regs_base = 0x40022000,
428 .fsize_addr = 0x1FFF75E0,
429 .otp_base = 0x1FFF7000,
433 .id = DEVID_STM32L41_L42XX,
434 .revs = stm32l41_L42xx_revs,
435 .num_revs = ARRAY_SIZE(stm32l41_L42xx_revs),
436 .device_str = "STM32L41/L42xx",
437 .max_flash_size_kb = 128,
439 .flash_regs_base = 0x40022000,
440 .fsize_addr = 0x1FFF75E0,
441 .otp_base = 0x1FFF7000,
445 .id = DEVID_STM32G03_G04XX,
446 .revs = stm32g03_g04xx_revs,
447 .num_revs = ARRAY_SIZE(stm32g03_g04xx_revs),
448 .device_str = "STM32G03x/G04xx",
449 .max_flash_size_kb = 64,
451 .flash_regs_base = 0x40022000,
452 .fsize_addr = 0x1FFF75E0,
453 .otp_base = 0x1FFF7000,
457 .id = DEVID_STM32G0B_G0CXX,
458 .revs = stm32g0b_g0cxx_revs,
459 .num_revs = ARRAY_SIZE(stm32g0b_g0cxx_revs),
460 .device_str = "STM32G0B/G0Cx",
461 .max_flash_size_kb = 512,
462 .flags = F_HAS_DUAL_BANK,
463 .flash_regs_base = 0x40022000,
464 .fsize_addr = 0x1FFF75E0,
465 .otp_base = 0x1FFF7000,
469 .id = DEVID_STM32G43_G44XX,
470 .revs = stm32g43_g44xx_revs,
471 .num_revs = ARRAY_SIZE(stm32g43_g44xx_revs),
472 .device_str = "STM32G43/G44xx",
473 .max_flash_size_kb = 128,
475 .flash_regs_base = 0x40022000,
476 .fsize_addr = 0x1FFF75E0,
477 .otp_base = 0x1FFF7000,
481 .id = DEVID_STM32G47_G48XX,
482 .revs = stm32g47_g48xx_revs,
483 .num_revs = ARRAY_SIZE(stm32g47_g48xx_revs),
484 .device_str = "STM32G47/G48xx",
485 .max_flash_size_kb = 512,
486 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
487 .flash_regs_base = 0x40022000,
488 .fsize_addr = 0x1FFF75E0,
489 .otp_base = 0x1FFF7000,
493 .id = DEVID_STM32L4R_L4SXX,
494 .revs = stm32l4r_l4sxx_revs,
495 .num_revs = ARRAY_SIZE(stm32l4r_l4sxx_revs),
496 .device_str = "STM32L4R/L4Sxx",
497 .max_flash_size_kb = 2048,
498 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
499 .flash_regs_base = 0x40022000,
500 .fsize_addr = 0x1FFF75E0,
501 .otp_base = 0x1FFF7000,
505 .id = DEVID_STM32L4P_L4QXX,
506 .revs = stm32l4p_l4qxx_revs,
507 .num_revs = ARRAY_SIZE(stm32l4p_l4qxx_revs),
508 .device_str = "STM32L4P/L4Qxx",
509 .max_flash_size_kb = 1024,
510 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
511 .flash_regs_base = 0x40022000,
512 .fsize_addr = 0x1FFF75E0,
513 .otp_base = 0x1FFF7000,
517 .id = DEVID_STM32L55_L56XX,
518 .revs = stm32l55_l56xx_revs,
519 .num_revs = ARRAY_SIZE(stm32l55_l56xx_revs),
520 .device_str = "STM32L55/L56xx",
521 .max_flash_size_kb = 512,
522 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
523 .flash_regs_base = 0x40022000,
524 .fsize_addr = 0x0BFA05E0,
525 .otp_base = 0x0BFA0000,
529 .id = DEVID_STM32G49_G4AXX,
530 .revs = stm32g49_g4axx_revs,
531 .num_revs = ARRAY_SIZE(stm32g49_g4axx_revs),
532 .device_str = "STM32G49/G4Axx",
533 .max_flash_size_kb = 512,
535 .flash_regs_base = 0x40022000,
536 .fsize_addr = 0x1FFF75E0,
537 .otp_base = 0x1FFF7000,
541 .id = DEVID_STM32U57_U58XX,
542 .revs = stm32u57_u58xx_revs,
543 .num_revs = ARRAY_SIZE(stm32u57_u58xx_revs),
544 .device_str = "STM32U57/U58xx",
545 .max_flash_size_kb = 2048,
546 .flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
547 .flash_regs_base = 0x40022000,
548 .fsize_addr = 0x0BFA07A0,
549 .otp_base = 0x0BFA0000,
553 .id = DEVID_STM32WB1XX,
554 .revs = stm32wb1xx_revs,
555 .num_revs = ARRAY_SIZE(stm32wb1xx_revs),
556 .device_str = "STM32WB1x",
557 .max_flash_size_kb = 320,
559 .flash_regs_base = 0x58004000,
560 .fsize_addr = 0x1FFF75E0,
561 .otp_base = 0x1FFF7000,
565 .id = DEVID_STM32WB5XX,
566 .revs = stm32wb5xx_revs,
567 .num_revs = ARRAY_SIZE(stm32wb5xx_revs),
568 .device_str = "STM32WB5x",
569 .max_flash_size_kb = 1024,
571 .flash_regs_base = 0x58004000,
572 .fsize_addr = 0x1FFF75E0,
573 .otp_base = 0x1FFF7000,
577 .id = DEVID_STM32WB3XX,
578 .revs = stm32wb3xx_revs,
579 .num_revs = ARRAY_SIZE(stm32wb3xx_revs),
580 .device_str = "STM32WB3x",
581 .max_flash_size_kb = 512,
583 .flash_regs_base = 0x58004000,
584 .fsize_addr = 0x1FFF75E0,
585 .otp_base = 0x1FFF7000,
589 .id = DEVID_STM32WLE_WL5XX,
590 .revs = stm32wle_wl5xx_revs,
591 .num_revs = ARRAY_SIZE(stm32wle_wl5xx_revs),
592 .device_str = "STM32WLE/WL5x",
593 .max_flash_size_kb = 256,
595 .flash_regs_base = 0x58004000,
596 .fsize_addr = 0x1FFF75E0,
597 .otp_base = 0x1FFF7000,
602 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
603 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
605 struct stm32l4_flash_bank *stm32l4_info;
608 return ERROR_COMMAND_SYNTAX_ERROR;
610 /* fix-up bank base address: 0 is used for normal flash memory */
612 bank->base = STM32_FLASH_BANK_BASE;
614 stm32l4_info = calloc(1, sizeof(struct stm32l4_flash_bank));
616 return ERROR_FAIL; /* Checkme: What better error to use?*/
617 bank->driver_priv = stm32l4_info;
619 stm32l4_info->probed = false;
620 stm32l4_info->otp_enabled = false;
621 stm32l4_info->user_bank_size = bank->size;
626 /* bitmap helper extension */
632 static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits,
633 struct range *ranges, unsigned int *ranges_count) {
635 bool last_bit = 0, cur_bit;
636 for (unsigned int i = 0; i < nbits; i++) {
637 cur_bit = test_bit(i, bitmap);
639 if (cur_bit && !last_bit) {
641 ranges[*ranges_count - 1].start = i;
642 ranges[*ranges_count - 1].end = i;
643 } else if (cur_bit && last_bit) {
644 /* update (increment) the end this range */
645 ranges[*ranges_count - 1].end = i;
652 static inline int range_print_one(struct range *range, char *str)
654 if (range->start == range->end)
655 return sprintf(str, "[%d]", range->start);
657 return sprintf(str, "[%d,%d]", range->start, range->end);
660 static char *range_print_alloc(struct range *ranges, unsigned int ranges_count)
662 /* each range will be printed like the following: [start,end]
663 * start and end, both are unsigned int, an unsigned int takes 10 characters max
664 * plus 3 characters for '[', ',' and ']'
665 * thus means each range can take maximum 23 character
666 * after each range we add a ' ' as separator and finally we need the '\0'
667 * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
668 char *str = calloc(1, ranges_count * (24 * sizeof(char)) + 1);
671 for (unsigned int i = 0; i < ranges_count; i++) {
672 ptr += range_print_one(&(ranges[i]), ptr);
674 if (i < ranges_count - 1)
681 /* end of bitmap helper extension */
683 static inline bool stm32l4_is_otp(struct flash_bank *bank)
685 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
686 return bank->base == stm32l4_info->part_info->otp_base;
689 static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
691 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
693 if (!stm32l4_is_otp(bank))
696 char *op_str = enable ? "enabled" : "disabled";
698 LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
700 stm32l4_info->otp_enabled == enable ? "already " : "",
703 stm32l4_info->otp_enabled = enable;
708 static inline bool stm32l4_otp_is_enabled(struct flash_bank *bank)
710 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
711 return stm32l4_info->otp_enabled;
714 static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
716 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
720 if (stm32l4_info->part_info->flags & F_HAS_TZ)
721 tzen = (stm32l4_info->optr & FLASH_TZEN) != 0;
723 uint32_t rdp = stm32l4_info->optr & FLASH_RDP_MASK;
725 /* for devices without TrustZone:
726 * RDP level 0 and 2 values are to 0xAA and 0xCC
727 * Any other value corresponds to RDP level 1
728 * for devices with TrusZone:
729 * RDP level 0 and 2 values are 0xAA and 0xCC
730 * RDP level 0.5 value is 0x55 only if TZEN = 1
731 * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
734 if (rdp != RDP_LEVEL_0 && rdp != RDP_LEVEL_2) {
735 if (!tzen || (tzen && rdp != RDP_LEVEL_0_5))
739 stm32l4_info->tzen = tzen;
740 stm32l4_info->rdp = rdp;
743 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
745 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
746 return stm32l4_info->flash_regs_base + reg_offset;
749 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
750 enum stm32l4_flash_reg_index reg_index)
752 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
753 return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]);
756 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
758 return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
761 static inline int stm32l4_read_flash_reg_by_index(struct flash_bank *bank,
762 enum stm32l4_flash_reg_index reg_index, uint32_t *value)
764 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
765 return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
768 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
770 return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
773 static inline int stm32l4_write_flash_reg_by_index(struct flash_bank *bank,
774 enum stm32l4_flash_reg_index reg_index, uint32_t value)
776 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
777 return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
780 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
782 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
784 int retval = ERROR_OK;
786 /* wait for busy to clear */
788 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &status);
789 if (retval != ERROR_OK)
791 LOG_DEBUG("status: 0x%" PRIx32 "", status);
792 if ((status & stm32l4_info->sr_bsy_mask) == 0)
794 if (timeout-- <= 0) {
795 LOG_ERROR("timed out waiting for flash");
801 if (status & FLASH_WRPERR) {
802 LOG_ERROR("stm32x device protected");
806 /* Clear but report errors */
807 if (status & FLASH_ERROR) {
808 if (retval == ERROR_OK)
810 /* If this operation fails, we ignore it and report the original
813 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status & FLASH_ERROR);
819 /** set all FLASH_SECBB registers to the same value */
820 static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
822 /* This function should be used only with device with TrustZone, do just a security check */
823 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
824 assert(stm32l4_info->part_info->flags & F_HAS_TZ);
826 /* based on RM0438 Rev6 for STM32L5x devices:
827 * to modify a page block-based security attribution, it is recommended to
828 * 1- check that no flash operation is ongoing on the related page
829 * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
830 * this step is not need in case of JTAG direct access
832 int retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
833 if (retval != ERROR_OK)
836 /* write SECBBxRy registers */
837 LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
839 const uint8_t secbb_regs[] = {
840 FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
841 FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
845 unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs);
847 /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
848 * then consider only the first half of secbb_regs
850 if (!stm32l4_info->dual_bank_mode)
853 for (unsigned int i = 0; i < num_secbb_regs; i++) {
854 retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value);
855 if (retval != ERROR_OK)
862 static inline int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
864 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
865 return (stm32l4_info->flash_regs[STM32_FLASH_CR_WLK_INDEX]) ?
866 STM32_FLASH_CR_WLK_INDEX : STM32_FLASH_CR_INDEX;
869 static int stm32l4_unlock_reg(struct flash_bank *bank)
871 const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
874 /* first check if not already unlocked
875 * otherwise writing on STM32_FLASH_KEYR will fail
877 int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
878 if (retval != ERROR_OK)
881 if ((ctrl & FLASH_LOCK) == 0)
884 /* unlock flash registers */
885 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY1);
886 if (retval != ERROR_OK)
889 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY2);
890 if (retval != ERROR_OK)
893 retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
894 if (retval != ERROR_OK)
897 if (ctrl & FLASH_LOCK) {
898 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
899 return ERROR_TARGET_FAILURE;
905 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
907 const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
910 int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
911 if (retval != ERROR_OK)
914 if ((ctrl & FLASH_OPTLOCK) == 0)
917 /* unlock option registers */
918 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY1);
919 if (retval != ERROR_OK)
922 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY2);
923 if (retval != ERROR_OK)
926 retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
927 if (retval != ERROR_OK)
930 if (ctrl & FLASH_OPTLOCK) {
931 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
932 return ERROR_TARGET_FAILURE;
938 static int stm32l4_perform_obl_launch(struct flash_bank *bank)
942 retval = stm32l4_unlock_reg(bank);
943 if (retval != ERROR_OK)
946 retval = stm32l4_unlock_option_reg(bank);
947 if (retval != ERROR_OK)
950 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
951 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
952 * "Note: If the read protection is set while the debugger is still
953 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
956 /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
957 /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
958 * then just ignore the returned value */
959 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH);
961 /* Need to re-probe after change */
962 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
963 stm32l4_info->probed = false;
966 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
967 FLASH_LOCK | FLASH_OPTLOCK);
969 if (retval != ERROR_OK)
975 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
976 uint32_t value, uint32_t mask)
978 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
982 retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
983 if (retval != ERROR_OK)
986 /* for STM32L5 and similar devices, use always non-secure
987 * registers for option bytes programming */
988 const uint32_t *saved_flash_regs = stm32l4_info->flash_regs;
989 if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
990 stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
992 retval = stm32l4_unlock_reg(bank);
993 if (retval != ERROR_OK)
996 retval = stm32l4_unlock_option_reg(bank);
997 if (retval != ERROR_OK)
1000 optiondata = (optiondata & ~mask) | (value & mask);
1002 retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
1003 if (retval != ERROR_OK)
1006 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OPTSTRT);
1007 if (retval != ERROR_OK)
1010 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1013 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
1014 FLASH_LOCK | FLASH_OPTLOCK);
1015 stm32l4_info->flash_regs = saved_flash_regs;
1017 if (retval != ERROR_OK)
1023 static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy,
1024 enum stm32l4_flash_reg_index reg_idx, int offset)
1026 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1029 wrpxy->reg_idx = reg_idx;
1030 wrpxy->offset = offset;
1032 ret = stm32l4_read_flash_reg_by_index(bank, wrpxy->reg_idx , &wrpxy->value);
1033 if (ret != ERROR_OK)
1036 wrpxy->first = (wrpxy->value & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1037 wrpxy->last = ((wrpxy->value >> 16) & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1038 wrpxy->used = wrpxy->first <= wrpxy->last;
1043 static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id,
1044 struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
1046 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1051 /* for single bank devices there is 2 WRP regions.
1052 * for dual bank devices there is 2 WRP regions per bank,
1053 * if configured as single bank only 2 WRP are usable
1054 * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
1055 * note: this should be revised, if a device will have the SWAP banks option
1058 int wrp2y_sectors_offset = -1; /* -1 : unused */
1060 /* if bank_id is BANK1 or ALL_BANKS */
1061 if (dev_bank_id != STM32_BANK2) {
1062 /* get FLASH_WRP1AR */
1063 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1AR_INDEX, 0);
1064 if (ret != ERROR_OK)
1068 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1BR_INDEX, 0);
1069 if (ret != ERROR_OK)
1072 /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
1073 if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
1074 wrp2y_sectors_offset = 0;
1077 /* if bank_id is BANK2 or ALL_BANKS */
1078 if (dev_bank_id != STM32_BANK1 && stm32l4_info->dual_bank_mode)
1079 wrp2y_sectors_offset = stm32l4_info->bank1_sectors;
1081 if (wrp2y_sectors_offset > -1) {
1083 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2AR_INDEX, wrp2y_sectors_offset);
1084 if (ret != ERROR_OK)
1088 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2BR_INDEX, wrp2y_sectors_offset);
1089 if (ret != ERROR_OK)
1096 static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
1098 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1100 int wrp_start = wrpxy->first - wrpxy->offset;
1101 int wrp_end = wrpxy->last - wrpxy->offset;
1103 uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
1105 return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
1108 static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
1112 for (unsigned int i = 0; i < n_wrp; i++) {
1113 ret = stm32l4_write_one_wrpxy(bank, &wrpxy[i]);
1114 if (ret != ERROR_OK)
1121 static int stm32l4_protect_check(struct flash_bank *bank)
1124 struct stm32l4_wrp wrpxy[4];
1126 int ret = stm32l4_get_all_wrpxy(bank, STM32_ALL_BANKS, wrpxy, &n_wrp);
1127 if (ret != ERROR_OK)
1130 /* initialize all sectors as unprotected */
1131 for (unsigned int i = 0; i < bank->num_sectors; i++)
1132 bank->sectors[i].is_protected = 0;
1134 /* now check WRPxy and mark the protected sectors */
1135 for (unsigned int i = 0; i < n_wrp; i++) {
1136 if (wrpxy[i].used) {
1137 for (int s = wrpxy[i].first; s <= wrpxy[i].last; s++)
1138 bank->sectors[s].is_protected = 1;
1145 static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
1148 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1149 int retval, retval2;
1151 assert((first <= last) && (last < bank->num_sectors));
1153 if (stm32l4_is_otp(bank)) {
1154 LOG_ERROR("cannot erase OTP memory");
1155 return ERROR_FLASH_OPER_UNSUPPORTED;
1158 if (bank->target->state != TARGET_HALTED) {
1159 LOG_ERROR("Target not halted");
1160 return ERROR_TARGET_NOT_HALTED;
1163 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1164 /* set all FLASH pages as secure */
1165 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
1166 if (retval != ERROR_OK) {
1167 /* restore all FLASH pages as non-secure */
1168 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1173 retval = stm32l4_unlock_reg(bank);
1174 if (retval != ERROR_OK)
1179 To erase a sector, follow the procedure below:
1180 1. Check that no Flash memory operation is ongoing by
1181 checking the BSY bit in the FLASH_SR register
1182 2. Set the PER bit and select the page and bank
1183 you wish to erase in the FLASH_CR register
1184 3. Set the STRT bit in the FLASH_CR register
1185 4. Wait for the BSY bit to be cleared
1188 for (unsigned int i = first; i <= last; i++) {
1189 uint32_t erase_flags;
1190 erase_flags = FLASH_PER | FLASH_STRT;
1192 if (i >= stm32l4_info->bank1_sectors) {
1194 snb = i - stm32l4_info->bank1_sectors;
1195 erase_flags |= snb << FLASH_PAGE_SHIFT | stm32l4_info->cr_bker_mask;
1197 erase_flags |= i << FLASH_PAGE_SHIFT;
1198 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, erase_flags);
1199 if (retval != ERROR_OK)
1202 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1203 if (retval != ERROR_OK)
1208 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
1210 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1211 /* restore all FLASH pages as non-secure */
1212 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
1213 if (retval3 != ERROR_OK)
1217 if (retval != ERROR_OK)
1223 static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
1225 struct target *target = bank->target;
1226 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1230 if (stm32l4_is_otp(bank)) {
1231 LOG_ERROR("cannot protect/unprotect OTP memory");
1232 return ERROR_FLASH_OPER_UNSUPPORTED;
1235 if (target->state != TARGET_HALTED) {
1236 LOG_ERROR("Target not halted");
1237 return ERROR_TARGET_NOT_HALTED;
1240 /* the requested sectors could be located into bank1 and/or bank2 */
1241 bool use_bank2 = false;
1242 if (last >= stm32l4_info->bank1_sectors) {
1243 if (first < stm32l4_info->bank1_sectors) {
1244 /* the requested sectors for (un)protection are shared between
1245 * bank 1 and 2, then split the operation */
1247 /* 1- deal with bank 1 sectors */
1248 LOG_DEBUG("The requested sectors for %s are shared between bank 1 and 2",
1249 set ? "protection" : "unprotection");
1250 ret = stm32l4_protect(bank, set, first, stm32l4_info->bank1_sectors - 1);
1251 if (ret != ERROR_OK)
1254 /* 2- then continue with bank 2 sectors */
1255 first = stm32l4_info->bank1_sectors;
1261 /* refresh the sectors' protection */
1262 ret = stm32l4_protect_check(bank);
1263 if (ret != ERROR_OK)
1266 /* check if the desired protection is already configured */
1267 for (i = first; i <= last; i++) {
1268 if (bank->sectors[i].is_protected != set)
1270 else if (i == last) {
1271 LOG_INFO("The specified sectors are already %s", set ? "protected" : "unprotected");
1276 /* all sectors from first to last (or part of them) could have different
1277 * protection other than the requested */
1279 struct stm32l4_wrp wrpxy[4];
1281 ret = stm32l4_get_all_wrpxy(bank, use_bank2 ? STM32_BANK2 : STM32_BANK1, wrpxy, &n_wrp);
1282 if (ret != ERROR_OK)
1285 /* use bitmap and range helpers to optimize the WRP usage */
1286 DECLARE_BITMAP(pages, bank->num_sectors);
1287 bitmap_zero(pages, bank->num_sectors);
1289 for (i = 0; i < n_wrp; i++) {
1290 if (wrpxy[i].used) {
1291 for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
1296 /* we have at most 'n_wrp' WRP areas
1297 * add one range if the user is trying to protect a fifth range */
1298 struct range ranges[n_wrp + 1];
1299 unsigned int ranges_count = 0;
1301 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1303 /* pretty-print the currently protected ranges */
1304 if (ranges_count > 0) {
1305 char *ranges_str = range_print_alloc(ranges, ranges_count);
1306 LOG_DEBUG("current protected areas: %s", ranges_str);
1309 LOG_DEBUG("current protected areas: none");
1311 if (set) { /* flash protect */
1312 for (i = first; i <= last; i++)
1314 } else { /* flash unprotect */
1315 for (i = first; i <= last; i++)
1316 clear_bit(i, pages);
1319 /* check the ranges_count after the user request */
1320 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1322 /* pretty-print the requested areas for protection */
1323 if (ranges_count > 0) {
1324 char *ranges_str = range_print_alloc(ranges, ranges_count);
1325 LOG_DEBUG("requested areas for protection: %s", ranges_str);
1328 LOG_DEBUG("requested areas for protection: none");
1330 if (ranges_count > n_wrp) {
1331 LOG_ERROR("cannot set the requested protection "
1332 "(only %u write protection areas are available)" , n_wrp);
1336 /* re-init all WRPxy as disabled (first > last)*/
1337 for (i = 0; i < n_wrp; i++) {
1338 wrpxy[i].first = wrpxy[i].offset + 1;
1339 wrpxy[i].last = wrpxy[i].offset;
1342 /* then configure WRPxy areas */
1343 for (i = 0; i < ranges_count; i++) {
1344 wrpxy[i].first = ranges[i].start;
1345 wrpxy[i].last = ranges[i].end;
1348 /* finally write WRPxy registers */
1349 return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp);
1352 /* count is the size divided by stm32l4_info->data_width */
1353 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
1354 uint32_t offset, uint32_t count)
1356 struct target *target = bank->target;
1357 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1358 struct working_area *write_algorithm;
1359 struct working_area *source;
1360 uint32_t address = bank->base + offset;
1361 struct reg_param reg_params[5];
1362 struct armv7m_algorithm armv7m_info;
1363 int retval = ERROR_OK;
1365 static const uint8_t stm32l4_flash_write_code[] = {
1366 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1369 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
1370 &write_algorithm) != ERROR_OK) {
1371 LOG_WARNING("no working area available, can't do block memory writes");
1372 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1375 retval = target_write_buffer(target, write_algorithm->address,
1376 sizeof(stm32l4_flash_write_code),
1377 stm32l4_flash_write_code);
1378 if (retval != ERROR_OK) {
1379 target_free_working_area(target, write_algorithm);
1383 /* data_width should be multiple of double-word */
1384 assert(stm32l4_info->data_width % 8 == 0);
1385 const size_t extra_size = sizeof(struct stm32l4_work_area);
1386 uint32_t buffer_size = target_get_working_area_avail(target) - extra_size;
1387 /* buffer_size should be multiple of stm32l4_info->data_width */
1388 buffer_size &= ~(stm32l4_info->data_width - 1);
1390 if (buffer_size < 256) {
1391 LOG_WARNING("large enough working area not available, can't do block memory writes");
1392 target_free_working_area(target, write_algorithm);
1393 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1394 } else if (buffer_size > 16384) {
1395 /* probably won't benefit from more than 16k ... */
1396 buffer_size = 16384;
1399 if (target_alloc_working_area_try(target, buffer_size + extra_size, &source) != ERROR_OK) {
1400 LOG_ERROR("allocating working area failed");
1401 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1404 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1405 armv7m_info.core_mode = ARM_MODE_THREAD;
1407 /* contrib/loaders/flash/stm32/stm32l4x.c:write() arguments */
1408 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* stm32l4_work_area ptr , status (out) */
1409 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
1410 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
1411 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (of stm32l4_info->data_width) */
1413 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1414 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
1415 buf_set_u32(reg_params[2].value, 0, 32, address);
1416 buf_set_u32(reg_params[3].value, 0, 32, count);
1418 /* write algo stack pointer */
1419 init_reg_param(®_params[4], "sp", 32, PARAM_OUT);
1420 buf_set_u32(reg_params[4].value, 0, 32, source->address +
1421 offsetof(struct stm32l4_work_area, stack) + LDR_STACK_SIZE);
1423 struct stm32l4_loader_params loader_extra_params;
1425 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_addr,
1426 stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX));
1427 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_cr_addr,
1428 stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX));
1429 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_word_size,
1430 stm32l4_info->data_width);
1431 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_bsy_mask,
1432 stm32l4_info->sr_bsy_mask);
1434 retval = target_write_buffer(target, source->address, sizeof(loader_extra_params),
1435 (uint8_t *) &loader_extra_params);
1436 if (retval != ERROR_OK)
1439 retval = target_run_flash_async_algorithm(target, buffer, count, stm32l4_info->data_width,
1441 ARRAY_SIZE(reg_params), reg_params,
1442 source->address + offsetof(struct stm32l4_work_area, fifo),
1443 source->size - offsetof(struct stm32l4_work_area, fifo),
1444 write_algorithm->address, 0,
1447 if (retval == ERROR_FLASH_OPERATION_FAILED) {
1448 LOG_ERROR("error executing stm32l4 flash write algorithm");
1451 stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &error);
1452 error &= FLASH_ERROR;
1454 if (error & FLASH_WRPERR)
1455 LOG_ERROR("flash memory write protected");
1458 LOG_ERROR("flash write failed = %08" PRIx32, error);
1459 /* Clear but report errors */
1460 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, error);
1461 retval = ERROR_FAIL;
1465 target_free_working_area(target, source);
1466 target_free_working_area(target, write_algorithm);
1468 destroy_reg_param(®_params[0]);
1469 destroy_reg_param(®_params[1]);
1470 destroy_reg_param(®_params[2]);
1471 destroy_reg_param(®_params[3]);
1472 destroy_reg_param(®_params[4]);
1477 /* count is the size divided by stm32l4_info->data_width */
1478 static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer,
1479 uint32_t offset, uint32_t count)
1481 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1482 struct target *target = bank->target;
1483 uint32_t address = bank->base + offset;
1484 int retval = ERROR_OK;
1486 /* wait for BSY bit */
1487 retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
1488 if (retval != ERROR_OK)
1491 /* set PG in FLASH_CR */
1492 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_PG);
1493 if (retval != ERROR_OK)
1497 /* write directly to flash memory */
1498 const uint8_t *src = buffer;
1499 const uint32_t data_width_in_words = stm32l4_info->data_width / 4;
1501 retval = target_write_memory(target, address, 4, data_width_in_words, src);
1502 if (retval != ERROR_OK)
1505 /* wait for BSY bit */
1506 retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
1507 if (retval != ERROR_OK)
1510 src += stm32l4_info->data_width;
1511 address += stm32l4_info->data_width;
1514 /* reset PG in FLASH_CR */
1515 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, 0);
1516 if (retval != ERROR_OK)
1522 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
1523 uint32_t offset, uint32_t count)
1525 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1526 int retval = ERROR_OK, retval2;
1528 if (stm32l4_is_otp(bank) && !stm32l4_otp_is_enabled(bank)) {
1529 LOG_ERROR("OTP memory is disabled for write commands");
1533 if (bank->target->state != TARGET_HALTED) {
1534 LOG_ERROR("Target not halted");
1535 return ERROR_TARGET_NOT_HALTED;
1538 /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
1539 assert(stm32l4_info->data_width % 8 == 0);
1541 /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
1542 * The flash infrastructure ensures it, do just a security check */
1543 assert(offset % stm32l4_info->data_width == 0);
1544 assert(count % stm32l4_info->data_width == 0);
1546 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1547 * data to be written does not go into a gap:
1548 * suppose buffer is fully contained in bank from sector 0 to sector
1549 * num->sectors - 1 and sectors are ordered according to offset
1551 struct flash_sector *head = &bank->sectors[0];
1552 struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
1554 while ((head < tail) && (offset >= (head + 1)->offset)) {
1555 /* buffer does not intersect head nor gap behind head */
1559 while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
1560 /* buffer does not intersect tail nor gap before tail */
1564 LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
1565 offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
1567 /* Now check that there is no gap from head to tail, this should work
1568 * even for multiple or non-symmetric gaps
1570 while (head < tail) {
1571 if (head->offset + head->size != (head + 1)->offset) {
1572 LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
1573 bank->base + head->offset + head->size,
1574 bank->base + (head + 1)->offset - 1);
1575 retval = ERROR_FLASH_DST_OUT_OF_BANK;
1580 if (retval != ERROR_OK)
1583 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1584 /* set all FLASH pages as secure */
1585 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
1586 if (retval != ERROR_OK) {
1587 /* restore all FLASH pages as non-secure */
1588 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1593 retval = stm32l4_unlock_reg(bank);
1594 if (retval != ERROR_OK)
1598 /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1599 * the debug is possible only in non-secure state.
1600 * Thus means the flashloader will run in non-secure mode,
1601 * and the workarea need to be in non-secure RAM */
1602 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
1603 LOG_WARNING("RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1605 /* first try to write using the loader, for better performance */
1606 retval = stm32l4_write_block(bank, buffer, offset,
1607 count / stm32l4_info->data_width);
1609 /* if resources are not available write without a loader */
1610 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1611 LOG_WARNING("falling back to programming without a flash loader (slower)");
1612 retval = stm32l4_write_block_without_loader(bank, buffer, offset,
1613 count / stm32l4_info->data_width);
1617 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
1619 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1620 /* restore all FLASH pages as non-secure */
1621 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
1622 if (retval3 != ERROR_OK)
1626 if (retval != ERROR_OK) {
1627 LOG_ERROR("block write failed");
1633 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
1635 int retval = ERROR_OK;
1636 struct target *target = bank->target;
1638 /* try reading possible IDCODE registers, in the following order */
1639 uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
1641 for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
1642 retval = target_read_u32(target, dbgmcu_idcode[i], id);
1643 if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
1647 /* Workaround for STM32WL5x devices:
1648 * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
1649 * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
1651 struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1653 LOG_ERROR("Flash requires Cortex-M target");
1654 return ERROR_TARGET_INVALID;
1657 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1658 * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
1659 if (cortex_m_get_partno_safe(target) == CORTEX_M0P_PARTNO &&
1660 armv7m->debug_ap && armv7m->debug_ap->ap_num == 1) {
1663 /* UID64 is contains
1664 * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
1665 * - Bits 31:08 : STID (company ID) = 0x0080E1
1666 * - Bits 07:00 : DEVID (device ID) = 0x15
1668 * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
1670 retval = target_read_u32(target, UID64_IDS, &uid64_ids);
1671 if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
1672 /* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
1673 *id = DEVID_STM32WLE_WL5XX;
1678 LOG_ERROR("can't get the device id");
1679 return (retval == ERROR_OK) ? ERROR_FAIL : retval;
1682 static const char *get_stm32l4_rev_str(struct flash_bank *bank)
1684 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1685 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1688 const uint16_t rev_id = stm32l4_info->idcode >> 16;
1689 for (unsigned int i = 0; i < part_info->num_revs; i++) {
1690 if (rev_id == part_info->revs[i].rev)
1691 return part_info->revs[i].str;
1696 static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
1698 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1699 assert(stm32l4_info->part_info);
1700 return stm32l4_is_otp(bank) ? "OTP" :
1701 stm32l4_info->dual_bank_mode ? "Flash dual" :
1705 static int stm32l4_probe(struct flash_bank *bank)
1707 struct target *target = bank->target;
1708 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1709 const struct stm32l4_part_info *part_info;
1710 uint16_t flash_size_kb = 0xffff;
1712 if (!target_was_examined(target)) {
1713 LOG_ERROR("Target not examined yet");
1714 return ERROR_TARGET_NOT_EXAMINED;
1717 struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1719 LOG_ERROR("Flash requires Cortex-M target");
1720 return ERROR_TARGET_INVALID;
1723 stm32l4_info->probed = false;
1725 /* read stm32 device id registers */
1726 int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
1727 if (retval != ERROR_OK)
1730 const uint32_t device_id = stm32l4_info->idcode & 0xFFF;
1732 for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
1733 if (device_id == stm32l4_parts[n].id) {
1734 stm32l4_info->part_info = &stm32l4_parts[n];
1739 if (!stm32l4_info->part_info) {
1740 LOG_WARNING("Cannot identify target as an %s family device.", device_families);
1744 part_info = stm32l4_info->part_info;
1745 const char *rev_str = get_stm32l4_rev_str(bank);
1746 const uint16_t rev_id = stm32l4_info->idcode >> 16;
1748 LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
1749 stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
1751 stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
1752 stm32l4_info->data_width = (part_info->flags & F_QUAD_WORD_PROG) ? 16 : 8;
1753 stm32l4_info->cr_bker_mask = FLASH_BKER;
1754 stm32l4_info->sr_bsy_mask = FLASH_BSY;
1756 /* Set flash write alignment boundaries.
1757 * Ask the flash infrastructure to ensure required alignment */
1758 bank->write_start_alignment = bank->write_end_alignment = stm32l4_info->data_width;
1760 /* Initialize the flash registers layout */
1761 if (part_info->flags & F_HAS_L5_FLASH_REGS)
1762 stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1764 stm32l4_info->flash_regs = stm32l4_flash_regs;
1766 /* read flash option register */
1767 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
1768 if (retval != ERROR_OK)
1771 stm32l4_sync_rdp_tzen(bank);
1773 /* for devices with TrustZone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
1774 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1775 if (part_info->flags & F_HAS_L5_FLASH_REGS) {
1776 stm32l4_info->flash_regs_base |= STM32L5_REGS_SEC_OFFSET;
1777 stm32l4_info->flash_regs = stm32l5_s_flash_regs;
1779 LOG_ERROR("BUG: device supported incomplete");
1780 return ERROR_NOT_IMPLEMENTED;
1784 if (part_info->flags & F_HAS_TZ)
1785 LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1787 stm32l4_info->tzen ? "enabled" : "disabled");
1789 LOG_INFO("RDP level %s (0x%02X)",
1790 stm32l4_info->rdp == RDP_LEVEL_0 ? "0" : stm32l4_info->rdp == RDP_LEVEL_0_5 ? "0.5" : "1",
1793 if (stm32l4_is_otp(bank)) {
1794 bank->size = part_info->otp_size;
1796 LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base);
1798 /* OTP memory is considered as one sector */
1799 free(bank->sectors);
1800 bank->num_sectors = 1;
1801 bank->sectors = alloc_block_array(0, part_info->otp_size, 1);
1803 if (!bank->sectors) {
1804 LOG_ERROR("failed to allocate bank sectors");
1808 stm32l4_info->probed = true;
1810 } else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) {
1811 LOG_ERROR("invalid bank base address");
1815 /* get flash size from target. */
1816 retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
1818 /* failed reading flash size or flash size invalid (early silicon),
1819 * default to max target family */
1820 if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
1821 || flash_size_kb > part_info->max_flash_size_kb) {
1822 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1823 part_info->max_flash_size_kb);
1824 flash_size_kb = part_info->max_flash_size_kb;
1827 /* if the user sets the size manually then ignore the probed value
1828 * this allows us to work around devices that have a invalid flash size register value */
1829 if (stm32l4_info->user_bank_size) {
1830 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1831 flash_size_kb = stm32l4_info->user_bank_size / 1024;
1834 LOG_INFO("flash size = %dkbytes", flash_size_kb);
1836 /* did we assign a flash size? */
1837 assert((flash_size_kb != 0xffff) && flash_size_kb);
1839 const bool is_max_flash_size = flash_size_kb == stm32l4_info->part_info->max_flash_size_kb;
1841 stm32l4_info->bank1_sectors = 0;
1842 stm32l4_info->hole_sectors = 0;
1845 int page_size_kb = 0;
1847 stm32l4_info->dual_bank_mode = false;
1849 switch (device_id) {
1850 case DEVID_STM32L47_L48XX:
1851 case DEVID_STM32L49_L4AXX:
1852 /* if flash size is max (1M) the device is always dual bank
1853 * STM32L47/L48xx: has variants with 512K
1854 * STM32L49/L4Axx: has variants with 512 and 256
1855 * for these variants:
1856 * if DUAL_BANK = 0 -> single bank
1857 * else -> dual bank without gap
1858 * note: the page size is invariant
1861 num_pages = flash_size_kb / page_size_kb;
1862 stm32l4_info->bank1_sectors = num_pages;
1864 /* check DUAL_BANK option bit if the flash is less than 1M */
1865 if (is_max_flash_size || (stm32l4_info->optr & FLASH_L4_DUAL_BANK)) {
1866 stm32l4_info->dual_bank_mode = true;
1867 stm32l4_info->bank1_sectors = num_pages / 2;
1870 case DEVID_STM32L43_L44XX:
1871 case DEVID_STM32G05_G06XX:
1872 case DEVID_STM32G07_G08XX:
1873 case DEVID_STM32L45_L46XX:
1874 case DEVID_STM32L41_L42XX:
1875 case DEVID_STM32G03_G04XX:
1876 case DEVID_STM32G43_G44XX:
1877 case DEVID_STM32G49_G4AXX:
1878 case DEVID_STM32WB1XX:
1879 /* single bank flash */
1881 num_pages = flash_size_kb / page_size_kb;
1882 stm32l4_info->bank1_sectors = num_pages;
1884 case DEVID_STM32G0B_G0CXX:
1885 /* single/dual bank depending on DUAL_BANK option bit */
1887 num_pages = flash_size_kb / page_size_kb;
1888 stm32l4_info->bank1_sectors = num_pages;
1889 stm32l4_info->cr_bker_mask = FLASH_BKER_G0;
1891 /* check DUAL_BANK bit */
1892 if (stm32l4_info->optr & FLASH_G0_DUAL_BANK) {
1893 stm32l4_info->sr_bsy_mask = FLASH_BSY | FLASH_BSY2;
1894 stm32l4_info->dual_bank_mode = true;
1895 stm32l4_info->bank1_sectors = num_pages / 2;
1898 case DEVID_STM32G47_G48XX:
1899 /* STM32G47/8 can be single/dual bank:
1900 * if DUAL_BANK = 0 -> single bank
1901 * else -> dual bank WITH gap
1904 num_pages = flash_size_kb / page_size_kb;
1905 stm32l4_info->bank1_sectors = num_pages;
1906 if (stm32l4_info->optr & FLASH_G4_DUAL_BANK) {
1907 stm32l4_info->dual_bank_mode = true;
1909 num_pages = flash_size_kb / page_size_kb;
1910 stm32l4_info->bank1_sectors = num_pages / 2;
1912 /* for devices with trimmed flash, there is a gap between both banks */
1913 stm32l4_info->hole_sectors =
1914 (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
1917 case DEVID_STM32L4R_L4SXX:
1918 case DEVID_STM32L4P_L4QXX:
1919 /* STM32L4R/S can be single/dual bank:
1920 * if size = 2M check DBANK bit
1921 * if size = 1M check DB1M bit
1922 * STM32L4P/Q can be single/dual bank
1923 * if size = 1M check DBANK bit
1924 * if size = 512K check DB512K bit (same as DB1M bit)
1927 num_pages = flash_size_kb / page_size_kb;
1928 stm32l4_info->bank1_sectors = num_pages;
1929 if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L4R_DBANK)) ||
1930 (!is_max_flash_size && (stm32l4_info->optr & FLASH_LRR_DB1M))) {
1931 stm32l4_info->dual_bank_mode = true;
1933 num_pages = flash_size_kb / page_size_kb;
1934 stm32l4_info->bank1_sectors = num_pages / 2;
1937 case DEVID_STM32L55_L56XX:
1938 /* STM32L55/L56xx can be single/dual bank:
1939 * if size = 512K check DBANK bit
1940 * if size = 256K check DB256K bit
1942 * default page size is 4kb, if DBANK = 1, the page size is 2kb.
1945 page_size_kb = (stm32l4_info->optr & FLASH_L5_DBANK) ? 2 : 4;
1946 num_pages = flash_size_kb / page_size_kb;
1947 stm32l4_info->bank1_sectors = num_pages;
1949 if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DBANK)) ||
1950 (!is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DB256))) {
1951 stm32l4_info->dual_bank_mode = true;
1952 stm32l4_info->bank1_sectors = num_pages / 2;
1955 case DEVID_STM32U57_U58XX:
1956 /* if flash size is max (2M) the device is always dual bank
1957 * otherwise check DUALBANK
1960 num_pages = flash_size_kb / page_size_kb;
1961 stm32l4_info->bank1_sectors = num_pages;
1962 if (is_max_flash_size || (stm32l4_info->optr & FLASH_U5_DUALBANK)) {
1963 stm32l4_info->dual_bank_mode = true;
1964 stm32l4_info->bank1_sectors = num_pages / 2;
1967 case DEVID_STM32WB5XX:
1968 case DEVID_STM32WB3XX:
1969 /* single bank flash */
1971 num_pages = flash_size_kb / page_size_kb;
1972 stm32l4_info->bank1_sectors = num_pages;
1974 case DEVID_STM32WLE_WL5XX:
1975 /* single bank flash */
1977 num_pages = flash_size_kb / page_size_kb;
1978 stm32l4_info->bank1_sectors = num_pages;
1980 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1981 * Using HLA adapters armv7m->debug_ap is null, and checking ap_num triggers a segfault */
1982 if (armv7m->debug_ap && armv7m->debug_ap->ap_num == 1)
1983 stm32l4_info->flash_regs = stm32wl_cpu2_flash_regs;
1986 LOG_ERROR("unsupported device");
1990 LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
1992 const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
1994 if (gap_size_kb != 0) {
1995 LOG_INFO("gap detected from 0x%08x to 0x%08x",
1996 STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
1997 * page_size_kb * 1024,
1998 STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
1999 * page_size_kb + gap_size_kb) * 1024 - 1);
2002 /* number of significant bits in WRPxxR differs per device,
2003 * always right adjusted, on some devices non-implemented
2004 * bits read as '0', on others as '1' ...
2005 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
2008 /* use *max_flash_size* instead of actual size as the trimmed versions
2009 * certainly use the same number of bits
2011 uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
2013 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
2014 stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
2015 assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
2016 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
2018 free(bank->sectors);
2020 bank->size = (flash_size_kb + gap_size_kb) * 1024;
2021 bank->num_sectors = num_pages;
2022 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
2023 if (!bank->sectors) {
2024 LOG_ERROR("failed to allocate bank sectors");
2028 for (unsigned int i = 0; i < bank->num_sectors; i++) {
2029 bank->sectors[i].offset = i * page_size_kb * 1024;
2030 /* in dual bank configuration, if there is a gap between banks
2031 * we fix up the sector offset to consider this gap */
2032 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
2033 bank->sectors[i].offset += gap_size_kb * 1024;
2034 bank->sectors[i].size = page_size_kb * 1024;
2035 bank->sectors[i].is_erased = -1;
2036 bank->sectors[i].is_protected = 1;
2039 stm32l4_info->probed = true;
2043 static int stm32l4_auto_probe(struct flash_bank *bank)
2045 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2046 if (stm32l4_info->probed) {
2049 /* save flash_regs_base */
2050 uint32_t saved_flash_regs_base = stm32l4_info->flash_regs_base;
2052 /* for devices with TrustZone, use NS flash registers to read OPTR */
2053 if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
2054 stm32l4_info->flash_regs_base &= ~STM32L5_REGS_SEC_OFFSET;
2056 /* read flash option register and re-probe if optr value is changed */
2057 int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &optr_cur);
2059 /* restore saved flash_regs_base */
2060 stm32l4_info->flash_regs_base = saved_flash_regs_base;
2062 if (retval != ERROR_OK)
2065 if (stm32l4_info->optr == optr_cur)
2069 return stm32l4_probe(bank);
2072 static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd)
2074 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2075 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
2078 const uint16_t rev_id = stm32l4_info->idcode >> 16;
2079 command_print_sameline(cmd, "%s - Rev %s : 0x%04x", part_info->device_str,
2080 get_stm32l4_rev_str(bank), rev_id);
2081 if (stm32l4_info->probed)
2082 command_print_sameline(cmd, " - %s-bank", get_stm32l4_bank_type_str(bank));
2084 command_print_sameline(cmd, "Cannot identify target as an %s device", device_families);
2090 static int stm32l4_mass_erase(struct flash_bank *bank)
2092 int retval, retval2;
2093 struct target *target = bank->target;
2094 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2096 if (stm32l4_is_otp(bank)) {
2097 LOG_ERROR("cannot erase OTP memory");
2098 return ERROR_FLASH_OPER_UNSUPPORTED;
2101 uint32_t action = FLASH_MER1;
2103 if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
2104 action |= FLASH_MER2;
2106 if (target->state != TARGET_HALTED) {
2107 LOG_ERROR("Target not halted");
2108 return ERROR_TARGET_NOT_HALTED;
2111 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2112 /* set all FLASH pages as secure */
2113 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
2114 if (retval != ERROR_OK) {
2115 /* restore all FLASH pages as non-secure */
2116 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
2121 retval = stm32l4_unlock_reg(bank);
2122 if (retval != ERROR_OK)
2125 /* mass erase flash memory */
2126 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
2127 if (retval != ERROR_OK)
2130 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action);
2131 if (retval != ERROR_OK)
2134 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action | FLASH_STRT);
2135 if (retval != ERROR_OK)
2138 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
2141 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
2143 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2144 /* restore all FLASH pages as non-secure */
2145 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
2146 if (retval3 != ERROR_OK)
2150 if (retval != ERROR_OK)
2156 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
2159 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
2160 return ERROR_COMMAND_SYNTAX_ERROR;
2163 struct flash_bank *bank;
2164 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2165 if (retval != ERROR_OK)
2168 retval = stm32l4_mass_erase(bank);
2169 if (retval == ERROR_OK)
2170 command_print(CMD, "stm32l4x mass erase complete");
2172 command_print(CMD, "stm32l4x mass erase failed");
2177 COMMAND_HANDLER(stm32l4_handle_option_read_command)
2180 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
2181 return ERROR_COMMAND_SYNTAX_ERROR;
2184 struct flash_bank *bank;
2185 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2186 if (retval != ERROR_OK)
2189 uint32_t reg_offset, reg_addr;
2192 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2193 reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
2195 retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
2196 if (retval != ERROR_OK)
2199 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
2204 COMMAND_HANDLER(stm32l4_handle_option_write_command)
2207 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
2208 return ERROR_COMMAND_SYNTAX_ERROR;
2211 struct flash_bank *bank;
2212 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2213 if (retval != ERROR_OK)
2216 uint32_t reg_offset;
2218 uint32_t mask = 0xFFFFFFFF;
2220 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2221 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2224 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
2226 command_print(CMD, "%s Option written.\n"
2227 "INFO: a reset or power cycle is required "
2228 "for the new settings to take effect.", bank->driver->name);
2230 retval = stm32l4_write_option(bank, reg_offset, value, mask);
2234 COMMAND_HANDLER(stm32l4_handle_trustzone_command)
2236 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2237 return ERROR_COMMAND_SYNTAX_ERROR;
2239 struct flash_bank *bank;
2240 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2241 if (retval != ERROR_OK)
2244 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2245 if (!(stm32l4_info->part_info->flags & F_HAS_TZ)) {
2246 LOG_ERROR("This device does not have a TrustZone");
2250 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
2251 if (retval != ERROR_OK)
2254 stm32l4_sync_rdp_tzen(bank);
2256 if (CMD_ARGC == 1) {
2257 /* only display the TZEN value */
2258 LOG_INFO("Global TrustZone Security is %s", stm32l4_info->tzen ? "enabled" : "disabled");
2263 COMMAND_PARSE_ENABLE(CMD_ARGV[1], new_tzen);
2265 if (new_tzen == stm32l4_info->tzen) {
2266 LOG_INFO("The requested TZEN is already programmed");
2271 if (stm32l4_info->rdp != RDP_LEVEL_0) {
2272 LOG_ERROR("TZEN can be set only when RDP level is 0");
2275 retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2276 FLASH_TZEN, FLASH_TZEN);
2278 /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2279 * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2280 if (stm32l4_info->rdp != RDP_LEVEL_1 && stm32l4_info->rdp != RDP_LEVEL_0_5) {
2281 LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2285 retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2286 RDP_LEVEL_0, FLASH_RDP_MASK | FLASH_TZEN);
2289 if (retval != ERROR_OK)
2292 return stm32l4_perform_obl_launch(bank);
2295 COMMAND_HANDLER(stm32l4_handle_option_load_command)
2298 return ERROR_COMMAND_SYNTAX_ERROR;
2300 struct flash_bank *bank;
2301 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2302 if (retval != ERROR_OK)
2305 retval = stm32l4_perform_obl_launch(bank);
2306 if (retval != ERROR_OK) {
2307 command_print(CMD, "stm32l4x option load failed");
2312 command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
2317 COMMAND_HANDLER(stm32l4_handle_lock_command)
2319 struct target *target = NULL;
2322 return ERROR_COMMAND_SYNTAX_ERROR;
2324 struct flash_bank *bank;
2325 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2326 if (retval != ERROR_OK)
2329 if (stm32l4_is_otp(bank)) {
2330 LOG_ERROR("cannot lock/unlock OTP memory");
2331 return ERROR_FLASH_OPER_UNSUPPORTED;
2334 target = bank->target;
2336 if (target->state != TARGET_HALTED) {
2337 LOG_ERROR("Target not halted");
2338 return ERROR_TARGET_NOT_HALTED;
2341 /* set readout protection level 1 by erasing the RDP option byte */
2342 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2343 if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2344 RDP_LEVEL_1, FLASH_RDP_MASK) != ERROR_OK) {
2345 command_print(CMD, "%s failed to lock device", bank->driver->name);
2352 COMMAND_HANDLER(stm32l4_handle_unlock_command)
2354 struct target *target = NULL;
2357 return ERROR_COMMAND_SYNTAX_ERROR;
2359 struct flash_bank *bank;
2360 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2361 if (retval != ERROR_OK)
2364 if (stm32l4_is_otp(bank)) {
2365 LOG_ERROR("cannot lock/unlock OTP memory");
2366 return ERROR_FLASH_OPER_UNSUPPORTED;
2369 target = bank->target;
2371 if (target->state != TARGET_HALTED) {
2372 LOG_ERROR("Target not halted");
2373 return ERROR_TARGET_NOT_HALTED;
2376 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2377 if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2378 RDP_LEVEL_0, FLASH_RDP_MASK) != ERROR_OK) {
2379 command_print(CMD, "%s failed to unlock device", bank->driver->name);
2386 COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
2388 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2389 return ERROR_COMMAND_SYNTAX_ERROR;
2391 struct flash_bank *bank;
2392 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2393 if (retval != ERROR_OK)
2396 if (stm32l4_is_otp(bank)) {
2397 LOG_ERROR("OTP memory does not have write protection areas");
2398 return ERROR_FLASH_OPER_UNSUPPORTED;
2401 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2402 enum stm32_bank_id dev_bank_id = STM32_ALL_BANKS;
2403 if (CMD_ARGC == 2) {
2404 if (strcmp(CMD_ARGV[1], "bank1") == 0)
2405 dev_bank_id = STM32_BANK1;
2406 else if (strcmp(CMD_ARGV[1], "bank2") == 0)
2407 dev_bank_id = STM32_BANK2;
2409 return ERROR_COMMAND_ARGUMENT_INVALID;
2412 if (dev_bank_id == STM32_BANK2) {
2413 if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
2414 LOG_ERROR("this device has no second bank");
2416 } else if (!stm32l4_info->dual_bank_mode) {
2417 LOG_ERROR("this device is configured in single bank mode");
2423 unsigned int n_wrp, i;
2424 struct stm32l4_wrp wrpxy[4];
2426 ret = stm32l4_get_all_wrpxy(bank, dev_bank_id, wrpxy, &n_wrp);
2427 if (ret != ERROR_OK)
2430 /* use bitmap and range helpers to better describe protected areas */
2431 DECLARE_BITMAP(pages, bank->num_sectors);
2432 bitmap_zero(pages, bank->num_sectors);
2434 for (i = 0; i < n_wrp; i++) {
2435 if (wrpxy[i].used) {
2436 for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
2441 /* we have at most 'n_wrp' WRP areas */
2442 struct range ranges[n_wrp];
2443 unsigned int ranges_count = 0;
2445 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
2447 if (ranges_count > 0) {
2448 /* pretty-print the protected ranges */
2449 char *ranges_str = range_print_alloc(ranges, ranges_count);
2450 command_print(CMD, "protected areas: %s", ranges_str);
2453 command_print(CMD, "no protected areas");
2458 COMMAND_HANDLER(stm32l4_handle_otp_command)
2461 return ERROR_COMMAND_SYNTAX_ERROR;
2463 struct flash_bank *bank;
2464 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2465 if (retval != ERROR_OK)
2468 if (!stm32l4_is_otp(bank)) {
2469 command_print(CMD, "the specified bank is not an OTP memory");
2472 if (strcmp(CMD_ARGV[1], "enable") == 0)
2473 stm32l4_otp_enable(bank, true);
2474 else if (strcmp(CMD_ARGV[1], "disable") == 0)
2475 stm32l4_otp_enable(bank, false);
2476 else if (strcmp(CMD_ARGV[1], "show") == 0)
2477 command_print(CMD, "OTP memory bank #%d is %s for write commands.",
2478 bank->bank_number, stm32l4_otp_is_enabled(bank) ? "enabled" : "disabled");
2480 return ERROR_COMMAND_SYNTAX_ERROR;
2485 static const struct command_registration stm32l4_exec_command_handlers[] = {
2488 .handler = stm32l4_handle_lock_command,
2489 .mode = COMMAND_EXEC,
2491 .help = "Lock entire flash device.",
2495 .handler = stm32l4_handle_unlock_command,
2496 .mode = COMMAND_EXEC,
2498 .help = "Unlock entire protected flash device.",
2501 .name = "mass_erase",
2502 .handler = stm32l4_handle_mass_erase_command,
2503 .mode = COMMAND_EXEC,
2505 .help = "Erase entire flash device.",
2508 .name = "option_read",
2509 .handler = stm32l4_handle_option_read_command,
2510 .mode = COMMAND_EXEC,
2511 .usage = "bank_id reg_offset",
2512 .help = "Read & Display device option bytes.",
2515 .name = "option_write",
2516 .handler = stm32l4_handle_option_write_command,
2517 .mode = COMMAND_EXEC,
2518 .usage = "bank_id reg_offset value mask",
2519 .help = "Write device option bit fields with provided value.",
2522 .name = "trustzone",
2523 .handler = stm32l4_handle_trustzone_command,
2524 .mode = COMMAND_EXEC,
2525 .usage = "<bank_id> [enable|disable]",
2526 .help = "Configure TrustZone security",
2530 .handler = stm32l4_handle_wrp_info_command,
2531 .mode = COMMAND_EXEC,
2532 .usage = "bank_id [bank1|bank2]",
2533 .help = "list the protected areas using WRP",
2536 .name = "option_load",
2537 .handler = stm32l4_handle_option_load_command,
2538 .mode = COMMAND_EXEC,
2540 .help = "Force re-load of device options (will cause device reset).",
2544 .handler = stm32l4_handle_otp_command,
2545 .mode = COMMAND_EXEC,
2546 .usage = "<bank_id> <enable|disable|show>",
2547 .help = "OTP (One Time Programmable) memory write enable/disable",
2549 COMMAND_REGISTRATION_DONE
2552 static const struct command_registration stm32l4_command_handlers[] = {
2555 .mode = COMMAND_ANY,
2556 .help = "stm32l4x flash command group",
2558 .chain = stm32l4_exec_command_handlers,
2560 COMMAND_REGISTRATION_DONE
2563 const struct flash_driver stm32l4x_flash = {
2565 .commands = stm32l4_command_handlers,
2566 .flash_bank_command = stm32l4_flash_bank_command,
2567 .erase = stm32l4_erase,
2568 .protect = stm32l4_protect,
2569 .write = stm32l4_write,
2570 .read = default_flash_read,
2571 .probe = stm32l4_probe,
2572 .auto_probe = stm32l4_auto_probe,
2573 .erase_check = default_flash_blank_check,
2574 .protect_check = stm32l4_protect_check,
2575 .info = get_stm32l4_info,
2576 .free_driver_priv = default_flash_free_driver_priv,