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   1 /***************************************************************************
   2  *   Copyright (C) 2015 by Uwe Bonnes                                      *
   3  *   bon@elektron.ikp.physik.tu-darmstadt.de                               *
   4  *                                                                         *
   5  *   Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics           *
   6  *   tarek.bouchkati@gmail.com                                             *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  20  ***************************************************************************/
  21
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "imp.h"
  27 #include <helper/binarybuffer.h>
  28 #include <target/algorithm.h>
  29 #include <target/armv7m.h>
  30 #include "bits.h"
  31
  32 /* STM32L4xxx series for reference.
  33  *
  34  * RM0351 (STM32L4x5/STM32L4x6)
  35  * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
  36  *
  37  * RM0394 (STM32L43x/44x/45x/46x)
  38  * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
  39  *
  40  * RM0432 (STM32L4R/4Sxx)
  41  * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
  42  *
  43  * STM32L476RG Datasheet (for erase timing)
  44  * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
  45  *
  46  * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
  47  * an option byte is available to map all sectors to the first bank.
  48  * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
  49  * handlers do!
  50  *
  51  * RM0394 devices have a single bank only.
  52  *
  53  * RM0432 devices have single and dual bank operating modes.
  54  * The FLASH size is 1Mbyte or 2Mbyte.
  55  * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
  56  *
  57  * Bank mode is controlled by two different bits in option bytes register.
  58  * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
  59  * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
  60  *
  61  */
  62
  63 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
  64
  65 #define FLASH_ERASE_TIMEOUT 250
  66
  67 /* Flash registers offsets */
  68 #define STM32_FLASH_ACR     0x00
  69 #define STM32_FLASH_KEYR    0x08
  70 #define STM32_FLASH_OPTKEYR 0x0c
  71 #define STM32_FLASH_SR      0x10
  72 #define STM32_FLASH_CR      0x14
  73 #define STM32_FLASH_OPTR    0x20
  74 #define STM32_FLASH_WRP1AR  0x2c
  75 #define STM32_FLASH_WRP1BR  0x30
  76 #define STM32_FLASH_WRP2AR  0x4c
  77 #define STM32_FLASH_WRP2BR  0x50
  78
  79 /* FLASH_CR register bits */
  80 #define FLASH_PG        (1 << 0)
  81 #define FLASH_PER       (1 << 1)
  82 #define FLASH_MER1      (1 << 2)
  83 #define FLASH_PAGE_SHIFT      3
  84 #define FLASH_CR_BKER   (1 << 11)
  85 #define FLASH_MER2      (1 << 15)
  86 #define FLASH_STRT      (1 << 16)
  87 #define FLASH_OPTSTRT   (1 << 17)
  88 #define FLASH_EOPIE     (1 << 24)
  89 #define FLASH_ERRIE     (1 << 25)
  90 #define FLASH_OBLLAUNCH (1 << 27)
  91 #define FLASH_OPTLOCK   (1 << 30)
  92 #define FLASH_LOCK      (1 << 31)
  93
  94 /* FLASH_SR register bits */
  95 #define FLASH_BSY      (1 << 16)
  96 /* Fast programming not used => related errors not used*/
  97 #define FLASH_PGSERR   (1 << 7) /* Programming sequence error */
  98 #define FLASH_SIZERR   (1 << 6) /* Size error */
  99 #define FLASH_PGAERR   (1 << 5) /* Programming alignment error */
 100 #define FLASH_WRPERR   (1 << 4) /* Write protection error */
 101 #define FLASH_PROGERR  (1 << 3) /* Programming error */
 102 #define FLASH_OPERR    (1 << 1) /* Operation error */
 103 #define FLASH_EOP      (1 << 0) /* End of operation */
 104 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
 105
 106 /* register unlock keys */
 107 #define KEY1           0x45670123
 108 #define KEY2           0xCDEF89AB
 109
 110 /* option register unlock key */
 111 #define OPTKEY1        0x08192A3B
 112 #define OPTKEY2        0x4C5D6E7F
 113
 114 #define RDP_LEVEL_0        0xAA
 115 #define RDP_LEVEL_1        0xBB
 116 #define RDP_LEVEL_2        0xCC
 117
 118
 119 /* other registers */
 120 #define DBGMCU_IDCODE   0xE0042000
 121
 122
 123 struct stm32l4_rev {
 124         const uint16_t rev;
 125         const char *str;
 126 };
 127
 128 struct stm32l4_part_info {
 129         uint16_t id;
 130         const char *device_str;
 131         const struct stm32l4_rev *revs;
 132         const size_t num_revs;
 133         const uint16_t max_flash_size_kb;
 134         const bool has_dual_bank;
 135         const uint32_t flash_regs_base;
 136         const uint32_t fsize_addr;
 137 };
 138
 139 struct stm32l4_flash_bank {
 140         int probed;
 141         uint32_t idcode;
 142         int bank1_sectors;
 143         bool dual_bank_mode;
 144         int hole_sectors;
 145         const struct stm32l4_part_info *part_info;
 146 };
 147
 148 static const struct stm32l4_rev stm32_415_revs[] = {
 149         { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
 150 };
 151
 152 static const struct stm32l4_rev stm32_435_revs[] = {
 153         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
 154 };
 155
 156 static const struct stm32l4_rev stm32_461_revs[] = {
 157         { 0x1000, "A" }, { 0x2000, "B" },
 158 };
 159
 160 static const struct stm32l4_rev stm32_462_revs[] = {
 161                 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
 162 };
 163
 164 static const struct stm32l4_rev stm32_464_revs[] = {
 165         { 0x1000, "A" },
 166 };
 167
 168 static const struct stm32l4_rev stm32_470_revs[] = {
 169         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
 170 };
 171
 172 static const struct stm32l4_part_info stm32l4_parts[] = {
 173         {
 174           .id                    = 0x415,
 175           .revs                  = stm32_415_revs,
 176           .num_revs              = ARRAY_SIZE(stm32_415_revs),
 177           .device_str            = "STM32L47/L48xx",
 178           .max_flash_size_kb     = 1024,
 179           .has_dual_bank         = true,
 180           .flash_regs_base       = 0x40022000,
 181           .fsize_addr            = 0x1FFF75E0,
 182         },
 183         {
 184           .id                    = 0x435,
 185           .revs                  = stm32_435_revs,
 186           .num_revs              = ARRAY_SIZE(stm32_435_revs),
 187           .device_str            = "STM32L43/L44xx",
 188           .max_flash_size_kb     = 256,
 189           .has_dual_bank         = false,
 190           .flash_regs_base       = 0x40022000,
 191           .fsize_addr            = 0x1FFF75E0,
 192         },
 193         {
 194           .id                    = 0x461,
 195           .revs                  = stm32_461_revs,
 196           .num_revs              = ARRAY_SIZE(stm32_461_revs),
 197           .device_str            = "STM32L49/L4Axx",
 198           .max_flash_size_kb     = 1024,
 199           .has_dual_bank         = true,
 200           .flash_regs_base       = 0x40022000,
 201           .fsize_addr            = 0x1FFF75E0,
 202         },
 203         {
 204           .id                    = 0x462,
 205           .revs                  = stm32_462_revs,
 206           .num_revs              = ARRAY_SIZE(stm32_462_revs),
 207           .device_str            = "STM32L45/L46xx",
 208           .max_flash_size_kb     = 512,
 209           .has_dual_bank         = false,
 210           .flash_regs_base       = 0x40022000,
 211           .fsize_addr            = 0x1FFF75E0,
 212         },
 213         {
 214           .id                    = 0x464,
 215           .revs                  = stm32_464_revs,
 216           .num_revs              = ARRAY_SIZE(stm32_464_revs),
 217           .device_str            = "STM32L41/L42xx",
 218           .max_flash_size_kb     = 128,
 219           .has_dual_bank         = false,
 220           .flash_regs_base       = 0x40022000,
 221           .fsize_addr            = 0x1FFF75E0,
 222         },
 223         {
 224           .id                    = 0x470,
 225           .revs                  = stm32_470_revs,
 226           .num_revs              = ARRAY_SIZE(stm32_470_revs),
 227           .device_str            = "STM32L4R/L4Sxx",
 228           .max_flash_size_kb     = 2048,
 229           .has_dual_bank         = true,
 230           .flash_regs_base       = 0x40022000,
 231           .fsize_addr            = 0x1FFF75E0,
 232         },
 233 };
 234
 235 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
 236 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
 237 {
 238         struct stm32l4_flash_bank *stm32l4_info;
 239
 240         if (CMD_ARGC < 6)
 241                 return ERROR_COMMAND_SYNTAX_ERROR;
 242
 243         stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
 244         if (!stm32l4_info)
 245                 return ERROR_FAIL; /* Checkme: What better error to use?*/
 246         bank->driver_priv = stm32l4_info;
 247
 248         stm32l4_info->probed = 0;
 249
 250         return ERROR_OK;
 251 }
 252
 253 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
 254 {
 255         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 256         return stm32l4_info->part_info->flash_regs_base + reg_offset;
 257 }
 258
 259 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
 260 {
 261         return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
 262 }
 263
 264 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
 265 {
 266         return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
 267 }
 268
 269 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
 270 {
 271         uint32_t status;
 272         int retval = ERROR_OK;
 273
 274         /* wait for busy to clear */
 275         for (;;) {
 276                 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_SR, &status);
 277                 if (retval != ERROR_OK)
 278                         return retval;
 279                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 280                 if ((status & FLASH_BSY) == 0)
 281                         break;
 282                 if (timeout-- <= 0) {
 283                         LOG_ERROR("timed out waiting for flash");
 284                         return ERROR_FAIL;
 285                 }
 286                 alive_sleep(1);
 287         }
 288
 289
 290         if (status & FLASH_WRPERR) {
 291                 LOG_ERROR("stm32x device protected");
 292                 retval = ERROR_FAIL;
 293         }
 294
 295         /* Clear but report errors */
 296         if (status & FLASH_ERROR) {
 297                 if (retval == ERROR_OK)
 298                         retval = ERROR_FAIL;
 299                 /* If this operation fails, we ignore it and report the original
 300                  * retval
 301                  */
 302                 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, status & FLASH_ERROR);
 303         }
 304
 305         return retval;
 306 }
 307
 308 static int stm32l4_unlock_reg(struct flash_bank *bank)
 309 {
 310         uint32_t ctrl;
 311
 312         /* first check if not already unlocked
 313          * otherwise writing on STM32_FLASH_KEYR will fail
 314          */
 315         int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
 316         if (retval != ERROR_OK)
 317                 return retval;
 318
 319         if ((ctrl & FLASH_LOCK) == 0)
 320                 return ERROR_OK;
 321
 322         /* unlock flash registers */
 323         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY1);
 324         if (retval != ERROR_OK)
 325                 return retval;
 326
 327         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY2);
 328         if (retval != ERROR_OK)
 329                 return retval;
 330
 331         retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
 332         if (retval != ERROR_OK)
 333                 return retval;
 334
 335         if (ctrl & FLASH_LOCK) {
 336                 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
 337                 return ERROR_TARGET_FAILURE;
 338         }
 339
 340         return ERROR_OK;
 341 }
 342
 343 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
 344 {
 345         uint32_t ctrl;
 346
 347         int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
 348         if (retval != ERROR_OK)
 349                 return retval;
 350
 351         if ((ctrl & FLASH_OPTLOCK) == 0)
 352                 return ERROR_OK;
 353
 354         /* unlock option registers */
 355         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY1);
 356         if (retval != ERROR_OK)
 357                 return retval;
 358
 359         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY2);
 360         if (retval != ERROR_OK)
 361                 return retval;
 362
 363         retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
 364         if (retval != ERROR_OK)
 365                 return retval;
 366
 367         if (ctrl & FLASH_OPTLOCK) {
 368                 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
 369                 return ERROR_TARGET_FAILURE;
 370         }
 371
 372         return ERROR_OK;
 373 }
 374
 375 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
 376 {
 377         uint32_t optiondata;
 378
 379         int retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
 380         if (retval != ERROR_OK)
 381                 return retval;
 382
 383         retval = stm32l4_unlock_reg(bank);
 384         if (retval != ERROR_OK)
 385                 return retval;
 386
 387         retval = stm32l4_unlock_option_reg(bank);
 388         if (retval != ERROR_OK)
 389                 return retval;
 390
 391         optiondata = (optiondata & ~mask) | (value & mask);
 392
 393         retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
 394         if (retval != ERROR_OK)
 395                 return retval;
 396
 397         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OPTSTRT);
 398         if (retval != ERROR_OK)
 399                 return retval;
 400
 401         retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 402         if (retval != ERROR_OK)
 403                 return retval;
 404
 405         return retval;
 406 }
 407
 408 static int stm32l4_protect_check(struct flash_bank *bank)
 409 {
 410         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 411
 412         uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
 413         stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar);
 414         stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br);
 415         stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
 416         stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
 417
 418         const uint8_t wrp1a_start = wrp1ar & 0xFF;
 419         const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
 420         const uint8_t wrp1b_start = wrp1br & 0xFF;
 421         const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
 422         const uint8_t wrp2a_start = wrp2ar & 0xFF;
 423         const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
 424         const uint8_t wrp2b_start = wrp2br & 0xFF;
 425         const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
 426
 427         for (int i = 0; i < bank->num_sectors; i++) {
 428                 if (i < stm32l4_info->bank1_sectors) {
 429                         if (((i >= wrp1a_start) &&
 430                                  (i <= wrp1a_end)) ||
 431                                 ((i >= wrp1b_start) &&
 432                                  (i <= wrp1b_end)))
 433                                 bank->sectors[i].is_protected = 1;
 434                         else
 435                                 bank->sectors[i].is_protected = 0;
 436                 } else {
 437                         uint8_t snb;
 438                         snb = i - stm32l4_info->bank1_sectors;
 439                         if (((snb >= wrp2a_start) &&
 440                                  (snb <= wrp2a_end)) ||
 441                                 ((snb >= wrp2b_start) &&
 442                                  (snb <= wrp2b_end)))
 443                                 bank->sectors[i].is_protected = 1;
 444                         else
 445                                 bank->sectors[i].is_protected = 0;
 446                 }
 447         }
 448         return ERROR_OK;
 449 }
 450
 451 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
 452 {
 453         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 454         int i;
 455         int retval;
 456
 457         assert(first < bank->num_sectors);
 458         assert(last < bank->num_sectors);
 459
 460         if (bank->target->state != TARGET_HALTED) {
 461                 LOG_ERROR("Target not halted");
 462                 return ERROR_TARGET_NOT_HALTED;
 463         }
 464
 465         retval = stm32l4_unlock_reg(bank);
 466         if (retval != ERROR_OK)
 467                 return retval;
 468
 469         /*
 470         Sector Erase
 471         To erase a sector, follow the procedure below:
 472         1. Check that no Flash memory operation is ongoing by
 473        checking the BSY bit in the FLASH_SR register
 474         2. Set the PER bit and select the page and bank
 475            you wish to erase in the FLASH_CR register
 476         3. Set the STRT bit in the FLASH_CR register
 477         4. Wait for the BSY bit to be cleared
 478          */
 479
 480         for (i = first; i <= last; i++) {
 481                 uint32_t erase_flags;
 482                 erase_flags = FLASH_PER | FLASH_STRT;
 483
 484                 if (i >= stm32l4_info->bank1_sectors) {
 485                         uint8_t snb;
 486                         snb = i - stm32l4_info->bank1_sectors;
 487                         erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
 488                 } else
 489                         erase_flags |= i << FLASH_PAGE_SHIFT;
 490                 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, erase_flags);
 491                 if (retval != ERROR_OK)
 492                         return retval;
 493
 494                 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 495                 if (retval != ERROR_OK)
 496                         return retval;
 497
 498                 bank->sectors[i].is_erased = 1;
 499         }
 500
 501         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
 502         if (retval != ERROR_OK)
 503                 return retval;
 504
 505         return ERROR_OK;
 506 }
 507
 508 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
 509 {
 510         struct target *target = bank->target;
 511         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 512
 513         if (target->state != TARGET_HALTED) {
 514                 LOG_ERROR("Target not halted");
 515                 return ERROR_TARGET_NOT_HALTED;
 516         }
 517
 518         int ret = ERROR_OK;
 519         /* Bank 2 */
 520         uint32_t reg_value = 0xFF; /* Default to bank un-protected */
 521         if (last >= stm32l4_info->bank1_sectors) {
 522                 if (set == 1) {
 523                         uint8_t begin = first > stm32l4_info->bank1_sectors ? first : 0x00;
 524                         reg_value = ((last & 0xFF) << 16) | begin;
 525                 }
 526
 527                 ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
 528         }
 529         /* Bank 1 */
 530         reg_value = 0xFF; /* Default to bank un-protected */
 531         if (first < stm32l4_info->bank1_sectors) {
 532                 if (set == 1) {
 533                         uint8_t end = last >= stm32l4_info->bank1_sectors ? 0xFF : last;
 534                         reg_value = (end << 16) | (first & 0xFF);
 535                 }
 536
 537                 ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
 538         }
 539
 540         return ret;
 541 }
 542
 543 /* Count is in halfwords */
 544 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
 545                 uint32_t offset, uint32_t count)
 546 {
 547         struct target *target = bank->target;
 548         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 549         uint32_t buffer_size = 16384;
 550         struct working_area *write_algorithm;
 551         struct working_area *source;
 552         uint32_t address = bank->base + offset;
 553         struct reg_param reg_params[5];
 554         struct armv7m_algorithm armv7m_info;
 555         int retval = ERROR_OK;
 556
 557         static const uint8_t stm32l4_flash_write_code[] = {
 558 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
 559         };
 560
 561         if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
 562                         &write_algorithm) != ERROR_OK) {
 563                 LOG_WARNING("no working area available, can't do block memory writes");
 564                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 565         }
 566
 567         retval = target_write_buffer(target, write_algorithm->address,
 568                         sizeof(stm32l4_flash_write_code),
 569                         stm32l4_flash_write_code);
 570         if (retval != ERROR_OK) {
 571                 target_free_working_area(target, write_algorithm);
 572                 return retval;
 573         }
 574
 575         /* memory buffer */
 576         while (target_alloc_working_area_try(target, buffer_size, &source) !=
 577                    ERROR_OK) {
 578                 buffer_size /= 2;
 579                 if (buffer_size <= 256) {
 580                         /* we already allocated the writing code, but failed to get a
 581                          * buffer, free the algorithm */
 582                         target_free_working_area(target, write_algorithm);
 583
 584                         LOG_WARNING("large enough working area not available, can't do block memory writes");
 585                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 586                 }
 587         }
 588
 589         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 590         armv7m_info.core_mode = ARM_MODE_THREAD;
 591
 592         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
 593         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* buffer end */
 594         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* target address */
 595         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* count (double word-64bit) */
 596         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);    /* flash base */
 597
 598         buf_set_u32(reg_params[0].value, 0, 32, source->address);
 599         buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
 600         buf_set_u32(reg_params[2].value, 0, 32, address);
 601         buf_set_u32(reg_params[3].value, 0, 32, count / 4);
 602         buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base);
 603
 604         retval = target_run_flash_async_algorithm(target, buffer, count, 2,
 605                         0, NULL,
 606                         5, reg_params,
 607                         source->address, source->size,
 608                         write_algorithm->address, 0,
 609                         &armv7m_info);
 610
 611         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 612                 LOG_ERROR("error executing stm32l4 flash write algorithm");
 613
 614                 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
 615
 616                 if (error & FLASH_WRPERR)
 617                         LOG_ERROR("flash memory write protected");
 618
 619                 if (error != 0) {
 620                         LOG_ERROR("flash write failed = %08" PRIx32, error);
 621                         /* Clear but report errors */
 622                         stm32l4_write_flash_reg(bank, STM32_FLASH_SR, error);
 623                         retval = ERROR_FAIL;
 624                 }
 625         }
 626
 627         target_free_working_area(target, source);
 628         target_free_working_area(target, write_algorithm);
 629
 630         destroy_reg_param(&reg_params[0]);
 631         destroy_reg_param(&reg_params[1]);
 632         destroy_reg_param(&reg_params[2]);
 633         destroy_reg_param(&reg_params[3]);
 634         destroy_reg_param(&reg_params[4]);
 635
 636         return retval;
 637 }
 638
 639 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
 640                 uint32_t offset, uint32_t count)
 641 {
 642         int retval;
 643
 644         if (bank->target->state != TARGET_HALTED) {
 645                 LOG_ERROR("Target not halted");
 646                 return ERROR_TARGET_NOT_HALTED;
 647         }
 648
 649         if (offset & 0x7) {
 650                 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment",
 651                                         offset);
 652                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 653         }
 654
 655         if (count & 0x7) {
 656                 LOG_WARNING("Padding %d bytes to keep 8-byte write size",
 657                                         count & 7);
 658                 count = (count + 7) & ~7;
 659                 /* This pads the write chunk with random bytes by overrunning the
 660                  * write buffer. Padding with the erased pattern 0xff is purely
 661                  * cosmetical, as 8-byte flash words are ECC secured and the first
 662                  * write will program the ECC bits. A second write would need
 663                  * to reprogramm these ECC bits.
 664                  * But this can only be done after erase!
 665                  */
 666         }
 667
 668         retval = stm32l4_unlock_reg(bank);
 669         if (retval != ERROR_OK)
 670                 return retval;
 671
 672         /* Only full double words (8-byte) can be programmed*/
 673         retval = stm32l4_write_block(bank, buffer, offset, count / 2);
 674         if (retval != ERROR_OK) {
 675                 LOG_WARNING("block write failed");
 676                 return retval;
 677         }
 678
 679         LOG_WARNING("block write succeeded");
 680         return stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
 681 }
 682
 683 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
 684 {
 685         int retval = target_read_u32(bank->target, DBGMCU_IDCODE, id);
 686         if (retval != ERROR_OK)
 687                 return retval;
 688
 689         return retval;
 690 }
 691
 692 static int stm32l4_probe(struct flash_bank *bank)
 693 {
 694         struct target *target = bank->target;
 695         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 696         const struct stm32l4_part_info *part_info;
 697         int i;
 698         uint16_t flash_size_in_kb = 0xffff;
 699         uint32_t device_id;
 700         uint32_t options;
 701
 702         stm32l4_info->probed = 0;
 703
 704         /* read stm32 device id register */
 705         int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
 706         if (retval != ERROR_OK)
 707                 return retval;
 708
 709         device_id = stm32l4_info->idcode & 0xFFF;
 710
 711         for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
 712                 if (device_id == stm32l4_parts[n].id)
 713                         stm32l4_info->part_info = &stm32l4_parts[n];
 714         }
 715
 716         if (!stm32l4_info->part_info) {
 717                 LOG_WARNING("Cannot identify target as an STM32L4 family device.");
 718                 return ERROR_FAIL;
 719         }
 720
 721         part_info = stm32l4_info->part_info;
 722
 723         char device_info[1024];
 724         retval = bank->driver->info(bank, device_info, sizeof(device_info));
 725         if (retval != ERROR_OK)
 726                 return retval;
 727
 728         LOG_INFO("device idcode = 0x%08" PRIx32 " (%s)", stm32l4_info->idcode, device_info);
 729
 730         /* get flash size from target. */
 731         retval = target_read_u16(target, part_info->fsize_addr, &flash_size_in_kb);
 732
 733         /* failed reading flash size or flash size invalid (early silicon),
 734          * default to max target family */
 735         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0
 736                         || flash_size_in_kb > part_info->max_flash_size_kb) {
 737                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 738                         part_info->max_flash_size_kb);
 739                 flash_size_in_kb = part_info->max_flash_size_kb;
 740         }
 741
 742         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 743
 744         /* did we assign a flash size? */
 745         assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
 746
 747         /* read flash option register */
 748         retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options);
 749         if (retval != ERROR_OK)
 750                 return retval;
 751
 752         stm32l4_info->bank1_sectors = 0;
 753         stm32l4_info->hole_sectors = 0;
 754
 755         int num_pages = 0;
 756         int page_size = 0;
 757
 758         stm32l4_info->dual_bank_mode = false;
 759
 760         switch (device_id) {
 761         case 0x415:
 762         case 0x461:
 763                 /* if flash size is max (1M) the device is always dual bank
 764                  * 0x415: has variants with 512K
 765                  * 0x461: has variants with 512 and 256
 766                  * for these variants:
 767                  *   if DUAL_BANK = 0 -> single bank
 768                  *   else -> dual bank without gap
 769                  * note: the page size is invariant
 770                  */
 771                 page_size = 2048;
 772                 num_pages = flash_size_in_kb / 2;
 773                 stm32l4_info->bank1_sectors = num_pages;
 774
 775                 /* check DUAL_BANK bit[21] if the flash is less than 1M */
 776                 if (flash_size_in_kb == 1024 || (options & BIT(21))) {
 777                         stm32l4_info->dual_bank_mode = true;
 778                         stm32l4_info->bank1_sectors = num_pages / 2;
 779                 }
 780                 break;
 781         case 0x435:
 782         case 0x462:
 783         case 0x464:
 784                 /* single bank flash */
 785                 page_size = 2048;
 786                 num_pages = flash_size_in_kb / 2;
 787                 stm32l4_info->bank1_sectors = num_pages;
 788                 break;
 789         case 0x470:
 790                 /* STM32L4R/S can be single/dual bank:
 791                  *   if size = 2M check DBANK bit(22)
 792                  *   if size = 1M check DB1M bit(21)
 793                  * in single bank configuration the page size is 8K
 794                  * else (dual bank) the page size is 4K without gap between banks
 795                  */
 796                 page_size = 8192;
 797                 num_pages = flash_size_in_kb / 8;
 798                 stm32l4_info->bank1_sectors = num_pages;
 799                 if ((flash_size_in_kb == 2048 && (options & BIT(22))) ||
 800                         (flash_size_in_kb == 1024 && (options & BIT(21)))) {
 801                         stm32l4_info->dual_bank_mode = true;
 802                         page_size = 4096;
 803                         num_pages = flash_size_in_kb / 4;
 804                         stm32l4_info->bank1_sectors = num_pages / 2;
 805                 }
 806                 break;
 807         default:
 808                 LOG_ERROR("unsupported device");
 809                 return ERROR_FAIL;
 810         }
 811
 812         LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
 813
 814         const int gap_size = stm32l4_info->hole_sectors * page_size;
 815
 816         if (stm32l4_info->dual_bank_mode & gap_size) {
 817                 LOG_INFO("gap detected starting from %0x08" PRIx32 " to %0x08" PRIx32,
 818                                 0x8000000 + stm32l4_info->bank1_sectors * page_size,
 819                                 0x8000000 + stm32l4_info->bank1_sectors * page_size + gap_size);
 820         }
 821
 822         if (bank->sectors) {
 823                 free(bank->sectors);
 824                 bank->sectors = NULL;
 825         }
 826
 827         bank->size = flash_size_in_kb * 1024 + gap_size;
 828         bank->base = 0x08000000;
 829         bank->num_sectors = num_pages;
 830         bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 831         if (bank->sectors == NULL) {
 832                 LOG_ERROR("failed to allocate bank sectors");
 833                 return ERROR_FAIL;
 834         }
 835
 836         for (i = 0; i < bank->num_sectors; i++) {
 837                 bank->sectors[i].offset = i * page_size;
 838                 /* in dual bank configuration, if there is a gap between banks
 839                  * we fix up the sector offset to consider this gap */
 840                 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
 841                         bank->sectors[i].offset += gap_size;
 842                 bank->sectors[i].size = page_size;
 843                 bank->sectors[i].is_erased = -1;
 844                 bank->sectors[i].is_protected = 1;
 845         }
 846
 847         stm32l4_info->probed = 1;
 848         return ERROR_OK;
 849 }
 850
 851 static int stm32l4_auto_probe(struct flash_bank *bank)
 852 {
 853         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 854         if (stm32l4_info->probed)
 855                 return ERROR_OK;
 856
 857         return stm32l4_probe(bank);
 858 }
 859
 860 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
 861 {
 862         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 863         const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
 864
 865         if (part_info) {
 866                 const char *rev_str = NULL;
 867                 uint16_t rev_id = stm32l4_info->idcode >> 16;
 868                 for (unsigned int i = 0; i < part_info->num_revs; i++) {
 869                         if (rev_id == part_info->revs[i].rev) {
 870                                 rev_str = part_info->revs[i].str;
 871
 872                                 if (rev_str != NULL) {
 873                                         snprintf(buf, buf_size, "%s - Rev: %s",
 874                                                         part_info->device_str, rev_str);
 875                                         return ERROR_OK;
 876                                 }
 877                         }
 878                 }
 879
 880                 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)",
 881                                 part_info->device_str, rev_id);
 882                 return ERROR_OK;
 883         } else {
 884                 snprintf(buf, buf_size, "Cannot identify target as a STM32L4x device");
 885                 return ERROR_FAIL;
 886         }
 887
 888         return ERROR_OK;
 889 }
 890
 891 static int stm32l4_mass_erase(struct flash_bank *bank)
 892 {
 893         int retval;
 894         struct target *target = bank->target;
 895         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 896
 897         uint32_t action = FLASH_MER1;
 898
 899         if (stm32l4_info->part_info->has_dual_bank)
 900                 action |= FLASH_MER2;
 901
 902         if (target->state != TARGET_HALTED) {
 903                 LOG_ERROR("Target not halted");
 904                 return ERROR_TARGET_NOT_HALTED;
 905         }
 906
 907         retval = stm32l4_unlock_reg(bank);
 908         if (retval != ERROR_OK)
 909                 return retval;
 910
 911         /* mass erase flash memory */
 912         retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
 913         if (retval != ERROR_OK)
 914                 return retval;
 915
 916         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action);
 917         if (retval != ERROR_OK)
 918                 return retval;
 919         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action | FLASH_STRT);
 920         if (retval != ERROR_OK)
 921                 return retval;
 922
 923         retval = stm32l4_wait_status_busy(bank,  FLASH_ERASE_TIMEOUT);
 924         if (retval != ERROR_OK)
 925                 return retval;
 926
 927         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
 928         if (retval != ERROR_OK)
 929                 return retval;
 930
 931         return ERROR_OK;
 932 }
 933
 934 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
 935 {
 936         int i;
 937
 938         if (CMD_ARGC < 1) {
 939                 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
 940                 return ERROR_COMMAND_SYNTAX_ERROR;
 941         }
 942
 943         struct flash_bank *bank;
 944         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 945         if (ERROR_OK != retval)
 946                 return retval;
 947
 948         retval = stm32l4_mass_erase(bank);
 949         if (retval == ERROR_OK) {
 950                 /* set all sectors as erased */
 951                 for (i = 0; i < bank->num_sectors; i++)
 952                         bank->sectors[i].is_erased = 1;
 953
 954                 command_print(CMD, "stm32l4x mass erase complete");
 955         } else {
 956                 command_print(CMD, "stm32l4x mass erase failed");
 957         }
 958
 959         return retval;
 960 }
 961
 962 COMMAND_HANDLER(stm32l4_handle_option_read_command)
 963 {
 964         if (CMD_ARGC < 2) {
 965                 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
 966                 return ERROR_COMMAND_SYNTAX_ERROR;
 967         }
 968
 969         struct flash_bank *bank;
 970         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 971         if (ERROR_OK != retval)
 972                 return retval;
 973
 974         uint32_t reg_offset, reg_addr;
 975         uint32_t value = 0;
 976
 977         reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
 978         reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
 979
 980         retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
 981         if (ERROR_OK != retval)
 982                 return retval;
 983
 984         command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
 985
 986         return retval;
 987 }
 988
 989 COMMAND_HANDLER(stm32l4_handle_option_write_command)
 990 {
 991         if (CMD_ARGC < 3) {
 992                 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
 993                 return ERROR_COMMAND_SYNTAX_ERROR;
 994         }
 995
 996         struct flash_bank *bank;
 997         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 998         if (ERROR_OK != retval)
 999                 return retval;
1000
1001         uint32_t reg_offset;
1002         uint32_t value = 0;
1003         uint32_t mask = 0xFFFFFFFF;
1004
1005         reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
1006         value = strtoul(CMD_ARGV[2], NULL, 16);
1007         if (CMD_ARGC > 3)
1008                 mask = strtoul(CMD_ARGV[3], NULL, 16);
1009
1010         command_print(CMD, "%s Option written.\n"
1011                                 "INFO: a reset or power cycle is required "
1012                                 "for the new settings to take effect.", bank->driver->name);
1013
1014         retval = stm32l4_write_option(bank, reg_offset, value, mask);
1015         return retval;
1016 }
1017
1018 COMMAND_HANDLER(stm32l4_handle_option_load_command)
1019 {
1020         if (CMD_ARGC < 1)
1021                 return ERROR_COMMAND_SYNTAX_ERROR;
1022
1023         struct flash_bank *bank;
1024         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1025         if (ERROR_OK != retval)
1026                 return retval;
1027
1028         retval = stm32l4_unlock_reg(bank);
1029         if (ERROR_OK != retval)
1030                 return retval;
1031
1032         retval = stm32l4_unlock_option_reg(bank);
1033         if (ERROR_OK != retval)
1034                 return retval;
1035
1036         /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
1037         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBLLAUNCH);
1038
1039         command_print(CMD, "stm32l4x option load (POR) completed.");
1040         return retval;
1041 }
1042
1043 COMMAND_HANDLER(stm32l4_handle_lock_command)
1044 {
1045         struct target *target = NULL;
1046
1047         if (CMD_ARGC < 1)
1048                 return ERROR_COMMAND_SYNTAX_ERROR;
1049
1050         struct flash_bank *bank;
1051         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1052         if (ERROR_OK != retval)
1053                 return retval;
1054
1055         target = bank->target;
1056
1057         if (target->state != TARGET_HALTED) {
1058                 LOG_ERROR("Target not halted");
1059                 return ERROR_TARGET_NOT_HALTED;
1060         }
1061
1062         /* set readout protection level 1 by erasing the RDP option byte */
1063         if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
1064                 command_print(CMD, "%s failed to lock device", bank->driver->name);
1065                 return ERROR_OK;
1066         }
1067
1068         return ERROR_OK;
1069 }
1070
1071 COMMAND_HANDLER(stm32l4_handle_unlock_command)
1072 {
1073         struct target *target = NULL;
1074
1075         if (CMD_ARGC < 1)
1076                 return ERROR_COMMAND_SYNTAX_ERROR;
1077
1078         struct flash_bank *bank;
1079         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1080         if (ERROR_OK != retval)
1081                 return retval;
1082
1083         target = bank->target;
1084
1085         if (target->state != TARGET_HALTED) {
1086                 LOG_ERROR("Target not halted");
1087                 return ERROR_TARGET_NOT_HALTED;
1088         }
1089
1090         if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
1091                 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1092                 return ERROR_OK;
1093         }
1094
1095         return ERROR_OK;
1096 }
1097
1098 static const struct command_registration stm32l4_exec_command_handlers[] = {
1099         {
1100                 .name = "lock",
1101                 .handler = stm32l4_handle_lock_command,
1102                 .mode = COMMAND_EXEC,
1103                 .usage = "bank_id",
1104                 .help = "Lock entire flash device.",
1105         },
1106         {
1107                 .name = "unlock",
1108                 .handler = stm32l4_handle_unlock_command,
1109                 .mode = COMMAND_EXEC,
1110                 .usage = "bank_id",
1111                 .help = "Unlock entire protected flash device.",
1112         },
1113         {
1114                 .name = "mass_erase",
1115                 .handler = stm32l4_handle_mass_erase_command,
1116                 .mode = COMMAND_EXEC,
1117                 .usage = "bank_id",
1118                 .help = "Erase entire flash device.",
1119         },
1120         {
1121                 .name = "option_read",
1122                 .handler = stm32l4_handle_option_read_command,
1123                 .mode = COMMAND_EXEC,
1124                 .usage = "bank_id reg_offset",
1125                 .help = "Read & Display device option bytes.",
1126         },
1127         {
1128                 .name = "option_write",
1129                 .handler = stm32l4_handle_option_write_command,
1130                 .mode = COMMAND_EXEC,
1131                 .usage = "bank_id reg_offset value mask",
1132                 .help = "Write device option bit fields with provided value.",
1133         },
1134         {
1135                 .name = "option_load",
1136                 .handler = stm32l4_handle_option_load_command,
1137                 .mode = COMMAND_EXEC,
1138                 .usage = "bank_id",
1139                 .help = "Force re-load of device options (will cause device reset).",
1140         },
1141         COMMAND_REGISTRATION_DONE
1142 };
1143
1144 static const struct command_registration stm32l4_command_handlers[] = {
1145         {
1146                 .name = "stm32l4x",
1147                 .mode = COMMAND_ANY,
1148                 .help = "stm32l4x flash command group",
1149                 .usage = "",
1150                 .chain = stm32l4_exec_command_handlers,
1151         },
1152         COMMAND_REGISTRATION_DONE
1153 };
1154
1155 const struct flash_driver stm32l4x_flash = {
1156         .name = "stm32l4x",
1157         .commands = stm32l4_command_handlers,
1158         .flash_bank_command = stm32l4_flash_bank_command,
1159         .erase = stm32l4_erase,
1160         .protect = stm32l4_protect,
1161         .write = stm32l4_write,
1162         .read = default_flash_read,
1163         .probe = stm32l4_probe,
1164         .auto_probe = stm32l4_auto_probe,
1165         .erase_check = default_flash_blank_check,
1166         .protect_check = stm32l4_protect_check,
1167         .info = get_stm32l4_info,
1168         .free_driver_priv = default_flash_free_driver_priv,
1169 };