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   1 /***************************************************************************
   2  *   Copyright (C) 2015 by Uwe Bonnes                                      *
   3  *   bon@elektron.ikp.physik.tu-darmstadt.de                               *
   4  *                                                                         *
   5  *   Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics           *
   6  *   tarek.bouchkati@gmail.com                                             *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  20  ***************************************************************************/
  21
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "imp.h"
  27 #include <helper/align.h>
  28 #include <helper/binarybuffer.h>
  29 #include <target/algorithm.h>
  30 #include <target/armv7m.h>
  31 #include "bits.h"
  32 #include "stm32l4x.h"
  33
  34 /* STM32L4xxx series for reference.
  35  *
  36  * RM0351 (STM32L4x5/STM32L4x6)
  37  * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
  38  *
  39  * RM0394 (STM32L43x/44x/45x/46x)
  40  * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
  41  *
  42  * RM0432 (STM32L4R/4Sxx)
  43  * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
  44  *
  45  * STM32L476RG Datasheet (for erase timing)
  46  * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
  47  *
  48  * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
  49  * an option byte is available to map all sectors to the first bank.
  50  * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
  51  * handlers do!
  52  *
  53  * RM0394 devices have a single bank only.
  54  *
  55  * RM0432 devices have single and dual bank operating modes.
  56  *  - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
  57  *  - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
  58  * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
  59  *
  60  * Bank mode is controlled by two different bits in option bytes register.
  61  *  - for STM32L4R/Sxx
  62  *    In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
  63  *    In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
  64  *  - for STM32L4P5/Q5x
  65  *    In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
  66  *    In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
  67  *
  68  */
  69
  70 /* STM32WBxxx series for reference.
  71  *
  72  * RM0434 (STM32WB55)
  73  * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
  74  *
  75  * RM0471 (STM32WB50)
  76  * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
  77  */
  78
  79 /* STM32WLxxx series for reference.
  80  *
  81  * RM0461 (STM32WLEx)
  82  * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
  83  */
  84
  85 /* STM32G0xxx series for reference.
  86  *
  87  * RM0444 (STM32G0x1)
  88  * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
  89  *
  90  * RM0454 (STM32G0x0)
  91  * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
  92  */
  93
  94 /* STM32G4xxx series for reference.
  95  *
  96  * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
  97  * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
  98  *
  99  * Cat. 2 devices have single bank only, page size is 2kByte.
 100  *
 101  * Cat. 3 devices have single and dual bank operating modes,
 102  * Page size is 2kByte (dual mode) or 4kByte (single mode).
 103  *
 104  * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
 105  * Both banks are treated as a single OpenOCD bank.
 106  *
 107  * Cat. 4 devices have single bank only, page size is 2kByte.
 108  */
 109
 110 /* STM32L5xxx series for reference.
 111  *
 112  * RM0428 (STM32L552xx/STM32L562xx)
 113  * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
 114  */
 115
 116 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
 117
 118 #define FLASH_ERASE_TIMEOUT 250
 119
 120
 121 /* relevant STM32L4 flags ****************************************************/
 122 #define F_NONE              0
 123 /* this flag indicates if the device flash is with dual bank architecture */
 124 #define F_HAS_DUAL_BANK     BIT(0)
 125 /* this flags is used for dual bank devices only, it indicates if the
 126  * 4 WRPxx are usable if the device is configured in single-bank mode */
 127 #define F_USE_ALL_WRPXX     BIT(1)
 128 /* this flag indicates if the device embeds a TrustZone security feature */
 129 #define F_HAS_TZ            BIT(2)
 130 /* end of STM32L4 flags ******************************************************/
 131
 132
 133 enum stm32l4_flash_reg_index {
 134         STM32_FLASH_ACR_INDEX,
 135         STM32_FLASH_KEYR_INDEX,
 136         STM32_FLASH_OPTKEYR_INDEX,
 137         STM32_FLASH_SR_INDEX,
 138         STM32_FLASH_CR_INDEX,
 139         STM32_FLASH_OPTR_INDEX,
 140         STM32_FLASH_WRP1AR_INDEX,
 141         STM32_FLASH_WRP1BR_INDEX,
 142         STM32_FLASH_WRP2AR_INDEX,
 143         STM32_FLASH_WRP2BR_INDEX,
 144         STM32_FLASH_REG_INDEX_NUM,
 145 };
 146
 147 enum stm32l4_rdp {
 148         RDP_LEVEL_0   = 0xAA,
 149         RDP_LEVEL_0_5 = 0x55, /* for devices with TrustZone enabled */
 150         RDP_LEVEL_1   = 0x00,
 151         RDP_LEVEL_2   = 0xCC
 152 };
 153
 154 static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
 155         [STM32_FLASH_ACR_INDEX]      = 0x000,
 156         [STM32_FLASH_KEYR_INDEX]     = 0x008,
 157         [STM32_FLASH_OPTKEYR_INDEX]  = 0x00C,
 158         [STM32_FLASH_SR_INDEX]       = 0x010,
 159         [STM32_FLASH_CR_INDEX]       = 0x014,
 160         [STM32_FLASH_OPTR_INDEX]     = 0x020,
 161         [STM32_FLASH_WRP1AR_INDEX]   = 0x02C,
 162         [STM32_FLASH_WRP1BR_INDEX]   = 0x030,
 163         [STM32_FLASH_WRP2AR_INDEX]   = 0x04C,
 164         [STM32_FLASH_WRP2BR_INDEX]   = 0x050,
 165 };
 166
 167 static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
 168         [STM32_FLASH_ACR_INDEX]      = 0x000,
 169         [STM32_FLASH_KEYR_INDEX]     = 0x008,
 170         [STM32_FLASH_OPTKEYR_INDEX]  = 0x010,
 171         [STM32_FLASH_SR_INDEX]       = 0x020,
 172         [STM32_FLASH_CR_INDEX]       = 0x028,
 173         [STM32_FLASH_OPTR_INDEX]     = 0x040,
 174         [STM32_FLASH_WRP1AR_INDEX]   = 0x058,
 175         [STM32_FLASH_WRP1BR_INDEX]   = 0x05C,
 176         [STM32_FLASH_WRP2AR_INDEX]   = 0x068,
 177         [STM32_FLASH_WRP2BR_INDEX]   = 0x06C,
 178 };
 179
 180 struct stm32l4_rev {
 181         const uint16_t rev;
 182         const char *str;
 183 };
 184
 185 struct stm32l4_part_info {
 186         uint16_t id;
 187         const char *device_str;
 188         const struct stm32l4_rev *revs;
 189         const size_t num_revs;
 190         const uint16_t max_flash_size_kb;
 191         const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
 192         const uint32_t flash_regs_base;
 193         const uint32_t *default_flash_regs;
 194         const uint32_t fsize_addr;
 195         const uint32_t otp_base;
 196         const uint32_t otp_size;
 197 };
 198
 199 struct stm32l4_flash_bank {
 200         bool probed;
 201         uint32_t idcode;
 202         unsigned int bank1_sectors;
 203         bool dual_bank_mode;
 204         int hole_sectors;
 205         uint32_t user_bank_size;
 206         uint32_t wrpxxr_mask;
 207         const struct stm32l4_part_info *part_info;
 208         const uint32_t *flash_regs;
 209         bool otp_enabled;
 210         enum stm32l4_rdp rdp;
 211         bool tzen;
 212 };
 213
 214 enum stm32_bank_id {
 215         STM32_BANK1,
 216         STM32_BANK2,
 217         STM32_ALL_BANKS
 218 };
 219
 220 struct stm32l4_wrp {
 221         enum stm32l4_flash_reg_index reg_idx;
 222         uint32_t value;
 223         bool used;
 224         int first;
 225         int last;
 226         int offset;
 227 };
 228
 229 /* human readable list of families this drivers supports (sorted alphabetically) */
 230 static const char *device_families = "STM32G0/G4/L4/L4+/L5/WB/WL";
 231
 232 static const struct stm32l4_rev stm32_415_revs[] = {
 233         { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
 234 };
 235
 236 static const struct stm32l4_rev stm32_435_revs[] = {
 237         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
 238 };
 239
 240 static const struct stm32l4_rev stm32_460_revs[] = {
 241         { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
 242 };
 243
 244 static const struct stm32l4_rev stm32_461_revs[] = {
 245         { 0x1000, "A" }, { 0x2000, "B" },
 246 };
 247
 248 static const struct stm32l4_rev stm32_462_revs[] = {
 249         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
 250 };
 251
 252 static const struct stm32l4_rev stm32_464_revs[] = {
 253         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
 254 };
 255
 256 static const struct stm32l4_rev stm32_466_revs[] = {
 257         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
 258 };
 259
 260 static const struct stm32l4_rev stm32_468_revs[] = {
 261         { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
 262 };
 263
 264 static const struct stm32l4_rev stm32_469_revs[] = {
 265         { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
 266 };
 267
 268 static const struct stm32l4_rev stm32_470_revs[] = {
 269         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
 270 };
 271
 272 static const struct stm32l4_rev stm32_471_revs[] = {
 273         { 0x1001, "Z" },
 274 };
 275
 276 static const struct stm32l4_rev stm32_472_revs[] = {
 277         { 0x1000, "A" }, { 0x2000, "B" },
 278 };
 279
 280 static const struct stm32l4_rev stm32_479_revs[] = {
 281         { 0x1000, "A" },
 282 };
 283
 284 static const struct stm32l4_rev stm32_495_revs[] = {
 285         { 0x2001, "2.1" },
 286 };
 287
 288 static const struct stm32l4_rev stm32_496_revs[] = {
 289         { 0x1000, "A" },
 290 };
 291
 292 static const struct stm32l4_rev stm32_497_revs[] = {
 293         { 0x1000, "1.0" },
 294 };
 295
 296 static const struct stm32l4_part_info stm32l4_parts[] = {
 297         {
 298           .id                    = 0x415,
 299           .revs                  = stm32_415_revs,
 300           .num_revs              = ARRAY_SIZE(stm32_415_revs),
 301           .device_str            = "STM32L47/L48xx",
 302           .max_flash_size_kb     = 1024,
 303           .flags                 = F_HAS_DUAL_BANK,
 304           .flash_regs_base       = 0x40022000,
 305           .default_flash_regs    = stm32l4_flash_regs,
 306           .fsize_addr            = 0x1FFF75E0,
 307           .otp_base              = 0x1FFF7000,
 308           .otp_size              = 1024,
 309         },
 310         {
 311           .id                    = 0x435,
 312           .revs                  = stm32_435_revs,
 313           .num_revs              = ARRAY_SIZE(stm32_435_revs),
 314           .device_str            = "STM32L43/L44xx",
 315           .max_flash_size_kb     = 256,
 316           .flags                 = F_NONE,
 317           .flash_regs_base       = 0x40022000,
 318           .default_flash_regs    = stm32l4_flash_regs,
 319           .fsize_addr            = 0x1FFF75E0,
 320           .otp_base              = 0x1FFF7000,
 321           .otp_size              = 1024,
 322         },
 323         {
 324           .id                    = 0x460,
 325           .revs                  = stm32_460_revs,
 326           .num_revs              = ARRAY_SIZE(stm32_460_revs),
 327           .device_str            = "STM32G07/G08xx",
 328           .max_flash_size_kb     = 128,
 329           .flags                 = F_NONE,
 330           .flash_regs_base       = 0x40022000,
 331           .default_flash_regs    = stm32l4_flash_regs,
 332           .fsize_addr            = 0x1FFF75E0,
 333           .otp_base              = 0x1FFF7000,
 334           .otp_size              = 1024,
 335         },
 336         {
 337           .id                    = 0x461,
 338           .revs                  = stm32_461_revs,
 339           .num_revs              = ARRAY_SIZE(stm32_461_revs),
 340           .device_str            = "STM32L49/L4Axx",
 341           .max_flash_size_kb     = 1024,
 342           .flags                 = F_HAS_DUAL_BANK,
 343           .flash_regs_base       = 0x40022000,
 344           .default_flash_regs    = stm32l4_flash_regs,
 345           .fsize_addr            = 0x1FFF75E0,
 346           .otp_base              = 0x1FFF7000,
 347           .otp_size              = 1024,
 348         },
 349         {
 350           .id                    = 0x462,
 351           .revs                  = stm32_462_revs,
 352           .num_revs              = ARRAY_SIZE(stm32_462_revs),
 353           .device_str            = "STM32L45/L46xx",
 354           .max_flash_size_kb     = 512,
 355           .flags                 = F_NONE,
 356           .flash_regs_base       = 0x40022000,
 357           .default_flash_regs    = stm32l4_flash_regs,
 358           .fsize_addr            = 0x1FFF75E0,
 359           .otp_base              = 0x1FFF7000,
 360           .otp_size              = 1024,
 361         },
 362         {
 363           .id                    = 0x464,
 364           .revs                  = stm32_464_revs,
 365           .num_revs              = ARRAY_SIZE(stm32_464_revs),
 366           .device_str            = "STM32L41/L42xx",
 367           .max_flash_size_kb     = 128,
 368           .flags                 = F_NONE,
 369           .flash_regs_base       = 0x40022000,
 370           .default_flash_regs    = stm32l4_flash_regs,
 371           .fsize_addr            = 0x1FFF75E0,
 372           .otp_base              = 0x1FFF7000,
 373           .otp_size              = 1024,
 374         },
 375         {
 376           .id                    = 0x466,
 377           .revs                  = stm32_466_revs,
 378           .num_revs              = ARRAY_SIZE(stm32_466_revs),
 379           .device_str            = "STM32G03/G04xx",
 380           .max_flash_size_kb     = 64,
 381           .flags                 = F_NONE,
 382           .flash_regs_base       = 0x40022000,
 383           .default_flash_regs    = stm32l4_flash_regs,
 384           .fsize_addr            = 0x1FFF75E0,
 385           .otp_base              = 0x1FFF7000,
 386           .otp_size              = 1024,
 387         },
 388         {
 389           .id                    = 0x468,
 390           .revs                  = stm32_468_revs,
 391           .num_revs              = ARRAY_SIZE(stm32_468_revs),
 392           .device_str            = "STM32G43/G44xx",
 393           .max_flash_size_kb     = 128,
 394           .flags                 = F_NONE,
 395           .flash_regs_base       = 0x40022000,
 396           .default_flash_regs    = stm32l4_flash_regs,
 397           .fsize_addr            = 0x1FFF75E0,
 398           .otp_base              = 0x1FFF7000,
 399           .otp_size              = 1024,
 400         },
 401         {
 402           .id                    = 0x469,
 403           .revs                  = stm32_469_revs,
 404           .num_revs              = ARRAY_SIZE(stm32_469_revs),
 405           .device_str            = "STM32G47/G48xx",
 406           .max_flash_size_kb     = 512,
 407           .flags                 = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
 408           .flash_regs_base       = 0x40022000,
 409           .default_flash_regs    = stm32l4_flash_regs,
 410           .fsize_addr            = 0x1FFF75E0,
 411           .otp_base              = 0x1FFF7000,
 412           .otp_size              = 1024,
 413         },
 414         {
 415           .id                    = 0x470,
 416           .revs                  = stm32_470_revs,
 417           .num_revs              = ARRAY_SIZE(stm32_470_revs),
 418           .device_str            = "STM32L4R/L4Sxx",
 419           .max_flash_size_kb     = 2048,
 420           .flags                 = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
 421           .flash_regs_base       = 0x40022000,
 422           .default_flash_regs    = stm32l4_flash_regs,
 423           .fsize_addr            = 0x1FFF75E0,
 424           .otp_base              = 0x1FFF7000,
 425           .otp_size              = 1024,
 426         },
 427         {
 428           .id                    = 0x471,
 429           .revs                  = stm32_471_revs,
 430           .num_revs              = ARRAY_SIZE(stm32_471_revs),
 431           .device_str            = "STM32L4P5/L4Q5x",
 432           .max_flash_size_kb     = 1024,
 433           .flags                 = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
 434           .flash_regs_base       = 0x40022000,
 435           .default_flash_regs    = stm32l4_flash_regs,
 436           .fsize_addr            = 0x1FFF75E0,
 437           .otp_base              = 0x1FFF7000,
 438           .otp_size              = 1024,
 439         },
 440         {
 441           .id                    = 0x472,
 442           .revs                  = stm32_472_revs,
 443           .num_revs              = ARRAY_SIZE(stm32_472_revs),
 444           .device_str            = "STM32L55/L56xx",
 445           .max_flash_size_kb     = 512,
 446           .flags                 = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ,
 447           .flash_regs_base       = 0x40022000,
 448           .default_flash_regs    = stm32l5_ns_flash_regs,
 449           .fsize_addr            = 0x0BFA05E0,
 450           .otp_base              = 0x0BFA0000,
 451           .otp_size              = 512,
 452         },
 453         {
 454           .id                    = 0x479,
 455           .revs                  = stm32_479_revs,
 456           .num_revs              = ARRAY_SIZE(stm32_479_revs),
 457           .device_str            = "STM32G49/G4Axx",
 458           .max_flash_size_kb     = 512,
 459           .flags                 = F_NONE,
 460           .flash_regs_base       = 0x40022000,
 461           .default_flash_regs    = stm32l4_flash_regs,
 462           .fsize_addr            = 0x1FFF75E0,
 463           .otp_base              = 0x1FFF7000,
 464           .otp_size              = 1024,
 465         },
 466         {
 467           .id                    = 0x495,
 468           .revs                  = stm32_495_revs,
 469           .num_revs              = ARRAY_SIZE(stm32_495_revs),
 470           .device_str            = "STM32WB5x",
 471           .max_flash_size_kb     = 1024,
 472           .flags                 = F_NONE,
 473           .flash_regs_base       = 0x58004000,
 474           .default_flash_regs    = stm32l4_flash_regs,
 475           .fsize_addr            = 0x1FFF75E0,
 476           .otp_base              = 0x1FFF7000,
 477           .otp_size              = 1024,
 478         },
 479         {
 480           .id                    = 0x496,
 481           .revs                  = stm32_496_revs,
 482           .num_revs              = ARRAY_SIZE(stm32_496_revs),
 483           .device_str            = "STM32WB3x",
 484           .max_flash_size_kb     = 512,
 485           .flags                 = F_NONE,
 486           .flash_regs_base       = 0x58004000,
 487           .default_flash_regs    = stm32l4_flash_regs,
 488           .fsize_addr            = 0x1FFF75E0,
 489           .otp_base              = 0x1FFF7000,
 490           .otp_size              = 1024,
 491         },
 492         {
 493           .id                    = 0x497,
 494           .revs                  = stm32_497_revs,
 495           .num_revs              = ARRAY_SIZE(stm32_497_revs),
 496           .device_str            = "STM32WLEx",
 497           .max_flash_size_kb     = 256,
 498           .flags                 = F_NONE,
 499           .flash_regs_base       = 0x58004000,
 500           .default_flash_regs    = stm32l4_flash_regs,
 501           .fsize_addr            = 0x1FFF75E0,
 502           .otp_base              = 0x1FFF7000,
 503           .otp_size              = 1024,
 504         },
 505 };
 506
 507 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
 508 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
 509 {
 510         struct stm32l4_flash_bank *stm32l4_info;
 511
 512         if (CMD_ARGC < 6)
 513                 return ERROR_COMMAND_SYNTAX_ERROR;
 514
 515         /* fix-up bank base address: 0 is used for normal flash memory */
 516         if (bank->base == 0)
 517                 bank->base = STM32_FLASH_BANK_BASE;
 518
 519         stm32l4_info = calloc(1, sizeof(struct stm32l4_flash_bank));
 520         if (!stm32l4_info)
 521                 return ERROR_FAIL; /* Checkme: What better error to use?*/
 522         bank->driver_priv = stm32l4_info;
 523
 524         /* The flash write must be aligned to a double word (8-bytes) boundary.
 525          * Ask the flash infrastructure to ensure required alignment */
 526         bank->write_start_alignment = bank->write_end_alignment = 8;
 527
 528         stm32l4_info->probed = false;
 529         stm32l4_info->otp_enabled = false;
 530         stm32l4_info->user_bank_size = bank->size;
 531
 532         return ERROR_OK;
 533 }
 534
 535 /* bitmap helper extension */
 536 struct range {
 537         unsigned int start;
 538         unsigned int end;
 539 };
 540
 541 static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits,
 542                 struct range *ranges, unsigned int *ranges_count) {
 543         *ranges_count = 0;
 544         bool last_bit = 0, cur_bit;
 545         for (unsigned int i = 0; i < nbits; i++) {
 546                 cur_bit = test_bit(i, bitmap);
 547
 548                 if (cur_bit && !last_bit) {
 549                         (*ranges_count)++;
 550                         ranges[*ranges_count - 1].start = i;
 551                         ranges[*ranges_count - 1].end = i;
 552                 } else if (cur_bit && last_bit) {
 553                         /* update (increment) the end this range */
 554                         ranges[*ranges_count - 1].end = i;
 555                 }
 556
 557                 last_bit = cur_bit;
 558         }
 559 }
 560
 561 static inline int range_print_one(struct range *range, char *str)
 562 {
 563         if (range->start == range->end)
 564                 return sprintf(str, "[%d]", range->start);
 565
 566         return sprintf(str, "[%d,%d]", range->start, range->end);
 567 }
 568
 569 static char *range_print_alloc(struct range *ranges, unsigned int ranges_count)
 570 {
 571         /* each range will be printed like the following: [start,end]
 572          * start and end, both are unsigned int, an unsigned int takes 10 characters max
 573          * plus 3 characters for '[', ',' and ']'
 574          * thus means each range can take maximum 23 character
 575          * after each range we add a ' ' as separator and finally we need the '\0'
 576          * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
 577         char *str = calloc(1, ranges_count * (24 * sizeof(char)) + 1);
 578         char *ptr = str;
 579
 580         for (unsigned int i = 0; i < ranges_count; i++) {
 581                 ptr += range_print_one(&(ranges[i]), ptr);
 582
 583                 if (i < ranges_count - 1)
 584                         *(ptr++) = ' ';
 585         }
 586
 587         return str;
 588 }
 589
 590 /* end of bitmap helper extension */
 591
 592 static inline bool stm32l4_is_otp(struct flash_bank *bank)
 593 {
 594         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 595         return bank->base == stm32l4_info->part_info->otp_base;
 596 }
 597
 598 static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
 599 {
 600         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 601
 602         if (!stm32l4_is_otp(bank))
 603                 return ERROR_FAIL;
 604
 605         char *op_str = enable ? "enabled" : "disabled";
 606
 607         LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
 608                         bank->bank_number,
 609                         stm32l4_info->otp_enabled == enable ? "already " : "",
 610                         op_str);
 611
 612         stm32l4_info->otp_enabled = enable;
 613
 614         return ERROR_OK;
 615 }
 616
 617 static inline bool stm32l4_otp_is_enabled(struct flash_bank *bank)
 618 {
 619         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 620         return stm32l4_info->otp_enabled;
 621 }
 622
 623 static void stm32l4_sync_rdp_tzen(struct flash_bank *bank, uint32_t optr_value)
 624 {
 625         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 626
 627         bool tzen = false;
 628
 629         if (stm32l4_info->part_info->flags & F_HAS_TZ)
 630                 tzen = (optr_value & FLASH_TZEN) != 0;
 631
 632         uint32_t rdp = optr_value & FLASH_RDP_MASK;
 633
 634         /* for devices without TrustZone:
 635          *   RDP level 0 and 2 values are to 0xAA and 0xCC
 636          *   Any other value corresponds to RDP level 1
 637          * for devices with TrusZone:
 638          *   RDP level 0 and 2 values are 0xAA and 0xCC
 639          *   RDP level 0.5 value is 0x55 only if TZEN = 1
 640          *   Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
 641          */
 642
 643         if (rdp != RDP_LEVEL_0 && rdp != RDP_LEVEL_2) {
 644                 if (!tzen || (tzen && rdp != RDP_LEVEL_0_5))
 645                         rdp = RDP_LEVEL_1;
 646         }
 647
 648         stm32l4_info->tzen = tzen;
 649         stm32l4_info->rdp = rdp;
 650 }
 651
 652 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
 653 {
 654         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 655         return stm32l4_info->part_info->flash_regs_base + reg_offset;
 656 }
 657
 658 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
 659         enum stm32l4_flash_reg_index reg_index)
 660 {
 661         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 662         return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]);
 663 }
 664
 665 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
 666 {
 667         return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
 668 }
 669
 670 static inline int stm32l4_read_flash_reg_by_index(struct flash_bank *bank,
 671         enum stm32l4_flash_reg_index reg_index, uint32_t *value)
 672 {
 673         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 674         return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
 675 }
 676
 677 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
 678 {
 679         return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
 680 }
 681
 682 static inline int stm32l4_write_flash_reg_by_index(struct flash_bank *bank,
 683         enum stm32l4_flash_reg_index reg_index, uint32_t value)
 684 {
 685         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 686         return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
 687 }
 688
 689 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
 690 {
 691         uint32_t status;
 692         int retval = ERROR_OK;
 693
 694         /* wait for busy to clear */
 695         for (;;) {
 696                 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &status);
 697                 if (retval != ERROR_OK)
 698                         return retval;
 699                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 700                 if ((status & FLASH_BSY) == 0)
 701                         break;
 702                 if (timeout-- <= 0) {
 703                         LOG_ERROR("timed out waiting for flash");
 704                         return ERROR_FAIL;
 705                 }
 706                 alive_sleep(1);
 707         }
 708
 709         if (status & FLASH_WRPERR) {
 710                 LOG_ERROR("stm32x device protected");
 711                 retval = ERROR_FAIL;
 712         }
 713
 714         /* Clear but report errors */
 715         if (status & FLASH_ERROR) {
 716                 if (retval == ERROR_OK)
 717                         retval = ERROR_FAIL;
 718                 /* If this operation fails, we ignore it and report the original
 719                  * retval
 720                  */
 721                 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status & FLASH_ERROR);
 722         }
 723
 724         return retval;
 725 }
 726
 727 static int stm32l4_unlock_reg(struct flash_bank *bank)
 728 {
 729         uint32_t ctrl;
 730
 731         /* first check if not already unlocked
 732          * otherwise writing on STM32_FLASH_KEYR will fail
 733          */
 734         int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
 735         if (retval != ERROR_OK)
 736                 return retval;
 737
 738         if ((ctrl & FLASH_LOCK) == 0)
 739                 return ERROR_OK;
 740
 741         /* unlock flash registers */
 742         retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY1);
 743         if (retval != ERROR_OK)
 744                 return retval;
 745
 746         retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY2);
 747         if (retval != ERROR_OK)
 748                 return retval;
 749
 750         retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
 751         if (retval != ERROR_OK)
 752                 return retval;
 753
 754         if (ctrl & FLASH_LOCK) {
 755                 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
 756                 return ERROR_TARGET_FAILURE;
 757         }
 758
 759         return ERROR_OK;
 760 }
 761
 762 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
 763 {
 764         uint32_t ctrl;
 765
 766         int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
 767         if (retval != ERROR_OK)
 768                 return retval;
 769
 770         if ((ctrl & FLASH_OPTLOCK) == 0)
 771                 return ERROR_OK;
 772
 773         /* unlock option registers */
 774         retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY1);
 775         if (retval != ERROR_OK)
 776                 return retval;
 777
 778         retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY2);
 779         if (retval != ERROR_OK)
 780                 return retval;
 781
 782         retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
 783         if (retval != ERROR_OK)
 784                 return retval;
 785
 786         if (ctrl & FLASH_OPTLOCK) {
 787                 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
 788                 return ERROR_TARGET_FAILURE;
 789         }
 790
 791         return ERROR_OK;
 792 }
 793
 794 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
 795         uint32_t value, uint32_t mask)
 796 {
 797         uint32_t optiondata;
 798         int retval, retval2;
 799
 800         retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
 801         if (retval != ERROR_OK)
 802                 return retval;
 803
 804         retval = stm32l4_unlock_reg(bank);
 805         if (retval != ERROR_OK)
 806                 goto err_lock;
 807
 808         retval = stm32l4_unlock_option_reg(bank);
 809         if (retval != ERROR_OK)
 810                 goto err_lock;
 811
 812         optiondata = (optiondata & ~mask) | (value & mask);
 813
 814         retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
 815         if (retval != ERROR_OK)
 816                 goto err_lock;
 817
 818         retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OPTSTRT);
 819         if (retval != ERROR_OK)
 820                 goto err_lock;
 821
 822         retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 823
 824 err_lock:
 825         retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK);
 826
 827         if (retval != ERROR_OK)
 828                 return retval;
 829
 830         return retval2;
 831 }
 832
 833 static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy,
 834                 enum stm32l4_flash_reg_index reg_idx, int offset)
 835 {
 836         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 837         int ret;
 838
 839         wrpxy->reg_idx = reg_idx;
 840         wrpxy->offset = offset;
 841
 842         ret = stm32l4_read_flash_reg_by_index(bank, wrpxy->reg_idx , &wrpxy->value);
 843         if (ret != ERROR_OK)
 844                 return ret;
 845
 846         wrpxy->first = (wrpxy->value & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
 847         wrpxy->last = ((wrpxy->value >> 16) & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
 848         wrpxy->used = wrpxy->first <= wrpxy->last;
 849
 850         return ERROR_OK;
 851 }
 852
 853 static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id,
 854                 struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
 855 {
 856         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 857         int ret;
 858
 859         *n_wrp = 0;
 860
 861         /* for single bank devices there is 2 WRP regions.
 862          * for dual bank devices there is 2 WRP regions per bank,
 863          *   if configured as single bank only 2 WRP are usable
 864          *   except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
 865          * note: this should be revised, if a device will have the SWAP banks option
 866          */
 867
 868         int wrp2y_sectors_offset = -1; /* -1 : unused */
 869
 870         /* if bank_id is BANK1 or ALL_BANKS */
 871         if (dev_bank_id != STM32_BANK2) {
 872                 /* get FLASH_WRP1AR */
 873                 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1AR_INDEX, 0);
 874                 if (ret != ERROR_OK)
 875                         return ret;
 876
 877                 /* get WRP1BR */
 878                 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1BR_INDEX, 0);
 879                 if (ret != ERROR_OK)
 880                         return ret;
 881
 882                 /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
 883                 if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
 884                         wrp2y_sectors_offset = 0;
 885         }
 886
 887         /* if bank_id is BANK2 or ALL_BANKS */
 888         if (dev_bank_id != STM32_BANK1 && stm32l4_info->dual_bank_mode)
 889                 wrp2y_sectors_offset = stm32l4_info->bank1_sectors;
 890
 891         if (wrp2y_sectors_offset > -1) {
 892                 /* get WRP2AR */
 893                 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2AR_INDEX, wrp2y_sectors_offset);
 894                 if (ret != ERROR_OK)
 895                         return ret;
 896
 897                 /* get WRP2BR */
 898                 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2BR_INDEX, wrp2y_sectors_offset);
 899                 if (ret != ERROR_OK)
 900                         return ret;
 901         }
 902
 903         return ERROR_OK;
 904 }
 905
 906 static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
 907 {
 908         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 909
 910         int wrp_start = wrpxy->first - wrpxy->offset;
 911         int wrp_end = wrpxy->last - wrpxy->offset;
 912
 913         uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
 914
 915         return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
 916 }
 917
 918 static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
 919 {
 920         int ret;
 921
 922         for (unsigned int i = 0; i < n_wrp; i++) {
 923                 ret = stm32l4_write_one_wrpxy(bank, &wrpxy[i]);
 924                 if (ret != ERROR_OK)
 925                         return ret;
 926         }
 927
 928         return ERROR_OK;
 929 }
 930
 931 static int stm32l4_protect_check(struct flash_bank *bank)
 932 {
 933         unsigned int n_wrp;
 934         struct stm32l4_wrp wrpxy[4];
 935
 936         int ret = stm32l4_get_all_wrpxy(bank, STM32_ALL_BANKS, wrpxy, &n_wrp);
 937         if (ret != ERROR_OK)
 938                 return ret;
 939
 940         /* initialize all sectors as unprotected */
 941         for (unsigned int i = 0; i < bank->num_sectors; i++)
 942                 bank->sectors[i].is_protected = 0;
 943
 944         /* now check WRPxy and mark the protected sectors */
 945         for (unsigned int i = 0; i < n_wrp; i++) {
 946                 if (wrpxy[i].used) {
 947                         for (int s = wrpxy[i].first; s <= wrpxy[i].last; s++)
 948                                 bank->sectors[s].is_protected = 1;
 949                 }
 950         }
 951
 952         return ERROR_OK;
 953 }
 954
 955 static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
 956                 unsigned int last)
 957 {
 958         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 959         int retval, retval2;
 960
 961         assert((first <= last) && (last < bank->num_sectors));
 962
 963         if (stm32l4_is_otp(bank)) {
 964                 LOG_ERROR("cannot erase OTP memory");
 965                 return ERROR_FLASH_OPER_UNSUPPORTED;
 966         }
 967
 968         if (bank->target->state != TARGET_HALTED) {
 969                 LOG_ERROR("Target not halted");
 970                 return ERROR_TARGET_NOT_HALTED;
 971         }
 972
 973         retval = stm32l4_unlock_reg(bank);
 974         if (retval != ERROR_OK)
 975                 goto err_lock;
 976
 977         /*
 978         Sector Erase
 979         To erase a sector, follow the procedure below:
 980         1. Check that no Flash memory operation is ongoing by
 981            checking the BSY bit in the FLASH_SR register
 982         2. Set the PER bit and select the page and bank
 983            you wish to erase in the FLASH_CR register
 984         3. Set the STRT bit in the FLASH_CR register
 985         4. Wait for the BSY bit to be cleared
 986          */
 987
 988         for (unsigned int i = first; i <= last; i++) {
 989                 uint32_t erase_flags;
 990                 erase_flags = FLASH_PER | FLASH_STRT;
 991
 992                 if (i >= stm32l4_info->bank1_sectors) {
 993                         uint8_t snb;
 994                         snb = i - stm32l4_info->bank1_sectors;
 995                         erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
 996                 } else
 997                         erase_flags |= i << FLASH_PAGE_SHIFT;
 998                 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, erase_flags);
 999                 if (retval != ERROR_OK)
1000                         break;
1001
1002                 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1003                 if (retval != ERROR_OK)
1004                         break;
1005         }
1006
1007 err_lock:
1008         retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
1009
1010         if (retval != ERROR_OK)
1011                 return retval;
1012
1013         return retval2;
1014 }
1015
1016 static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
1017 {
1018         struct target *target = bank->target;
1019         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1020         int ret = ERROR_OK;
1021         unsigned int i;
1022
1023         if (stm32l4_is_otp(bank)) {
1024                 LOG_ERROR("cannot protect/unprotect OTP memory");
1025                 return ERROR_FLASH_OPER_UNSUPPORTED;
1026         }
1027
1028         if (target->state != TARGET_HALTED) {
1029                 LOG_ERROR("Target not halted");
1030                 return ERROR_TARGET_NOT_HALTED;
1031         }
1032
1033         /* the requested sectors could be located into bank1 and/or bank2 */
1034         bool use_bank2 = false;
1035         if (last >= stm32l4_info->bank1_sectors) {
1036                 if (first < stm32l4_info->bank1_sectors) {
1037                         /* the requested sectors for (un)protection are shared between
1038                          * bank 1 and 2, then split the operation */
1039
1040                         /*  1- deal with bank 1 sectors */
1041                         LOG_DEBUG("The requested sectors for %s are shared between bank 1 and 2",
1042                                         set ? "protection" : "unprotection");
1043                         ret = stm32l4_protect(bank, set, first, stm32l4_info->bank1_sectors - 1);
1044                         if (ret != ERROR_OK)
1045                                 return ret;
1046
1047                         /*  2- then continue with bank 2 sectors */
1048                         first = stm32l4_info->bank1_sectors;
1049                 }
1050
1051                 use_bank2 = true;
1052         }
1053
1054         /* refresh the sectors' protection */
1055         ret = stm32l4_protect_check(bank);
1056         if (ret != ERROR_OK)
1057                 return ret;
1058
1059         /* check if the desired protection is already configured */
1060         for (i = first; i <= last; i++) {
1061                 if (bank->sectors[i].is_protected != set)
1062                         break;
1063                 else if (i == last) {
1064                         LOG_INFO("The specified sectors are already %s", set ? "protected" : "unprotected");
1065                         return ERROR_OK;
1066                 }
1067         }
1068
1069         /* all sectors from first to last (or part of them) could have different
1070          * protection other than the requested */
1071         unsigned int n_wrp;
1072         struct stm32l4_wrp wrpxy[4];
1073
1074         ret = stm32l4_get_all_wrpxy(bank, use_bank2 ? STM32_BANK2 : STM32_BANK1, wrpxy, &n_wrp);
1075         if (ret != ERROR_OK)
1076                 return ret;
1077
1078         /* use bitmap and range helpers to optimize the WRP usage */
1079         DECLARE_BITMAP(pages, bank->num_sectors);
1080         bitmap_zero(pages, bank->num_sectors);
1081
1082         for (i = 0; i < n_wrp; i++) {
1083                 if (wrpxy[i].used) {
1084                         for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
1085                                 set_bit(p, pages);
1086                 }
1087         }
1088
1089         /* we have at most 'n_wrp' WRP areas
1090          * add one range if the user is trying to protect a fifth range */
1091         struct range ranges[n_wrp + 1];
1092         unsigned int ranges_count = 0;
1093
1094         bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1095
1096         /* pretty-print the currently protected ranges */
1097         if (ranges_count > 0) {
1098                 char *ranges_str = range_print_alloc(ranges, ranges_count);
1099                 LOG_DEBUG("current protected areas: %s", ranges_str);
1100                 free(ranges_str);
1101         } else
1102                 LOG_DEBUG("current protected areas: none");
1103
1104         if (set) { /* flash protect */
1105                 for (i = first; i <= last; i++)
1106                         set_bit(i, pages);
1107         } else { /* flash unprotect */
1108                 for (i = first; i <= last; i++)
1109                         clear_bit(i, pages);
1110         }
1111
1112         /* check the ranges_count after the user request */
1113         bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1114
1115         /* pretty-print the requested areas for protection */
1116         if (ranges_count > 0) {
1117                 char *ranges_str = range_print_alloc(ranges, ranges_count);
1118                 LOG_DEBUG("requested areas for protection: %s", ranges_str);
1119                 free(ranges_str);
1120         } else
1121                 LOG_DEBUG("requested areas for protection: none");
1122
1123         if (ranges_count > n_wrp) {
1124                 LOG_ERROR("cannot set the requested protection "
1125                                 "(only %u write protection areas are available)" , n_wrp);
1126                 return ERROR_FAIL;
1127         }
1128
1129         /* re-init all WRPxy as disabled (first > last)*/
1130         for (i = 0; i < n_wrp; i++) {
1131                 wrpxy[i].first = wrpxy[i].offset + 1;
1132                 wrpxy[i].last = wrpxy[i].offset;
1133         }
1134
1135         /* then configure WRPxy areas */
1136         for (i = 0; i < ranges_count; i++) {
1137                 wrpxy[i].first = ranges[i].start;
1138                 wrpxy[i].last = ranges[i].end;
1139         }
1140
1141         /* finally write WRPxy registers */
1142         return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp);
1143 }
1144
1145 /* Count is in double-words */
1146 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
1147         uint32_t offset, uint32_t count)
1148 {
1149         struct target *target = bank->target;
1150         uint32_t buffer_size;
1151         struct working_area *write_algorithm;
1152         struct working_area *source;
1153         uint32_t address = bank->base + offset;
1154         struct reg_param reg_params[6];
1155         struct armv7m_algorithm armv7m_info;
1156         int retval = ERROR_OK;
1157
1158         static const uint8_t stm32l4_flash_write_code[] = {
1159 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1160         };
1161
1162         if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
1163                         &write_algorithm) != ERROR_OK) {
1164                 LOG_WARNING("no working area available, can't do block memory writes");
1165                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1166         }
1167
1168         retval = target_write_buffer(target, write_algorithm->address,
1169                         sizeof(stm32l4_flash_write_code),
1170                         stm32l4_flash_write_code);
1171         if (retval != ERROR_OK) {
1172                 target_free_working_area(target, write_algorithm);
1173                 return retval;
1174         }
1175
1176         /* memory buffer, size *must* be multiple of dword plus one dword for rp and one for wp */
1177         buffer_size = target_get_working_area_avail(target) & ~(2 * sizeof(uint32_t) - 1);
1178         if (buffer_size < 256) {
1179                 LOG_WARNING("large enough working area not available, can't do block memory writes");
1180                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1181         } else if (buffer_size > 16384) {
1182                 /* probably won't benefit from more than 16k ... */
1183                 buffer_size = 16384;
1184         }
1185
1186         if (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
1187                 LOG_ERROR("allocating working area failed");
1188                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1189         }
1190
1191         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1192         armv7m_info.core_mode = ARM_MODE_THREAD;
1193
1194         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
1195         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* buffer end */
1196         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* target address */
1197         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* count (double word-64bit) */
1198         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);    /* flash status register */
1199         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);    /* flash control register */
1200
1201         buf_set_u32(reg_params[0].value, 0, 32, source->address);
1202         buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
1203         buf_set_u32(reg_params[2].value, 0, 32, address);
1204         buf_set_u32(reg_params[3].value, 0, 32, count);
1205         buf_set_u32(reg_params[4].value, 0, 32, stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX));
1206         buf_set_u32(reg_params[5].value, 0, 32, stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX));
1207
1208         retval = target_run_flash_async_algorithm(target, buffer, count, 8,
1209                         0, NULL,
1210                         ARRAY_SIZE(reg_params), reg_params,
1211                         source->address, source->size,
1212                         write_algorithm->address, 0,
1213                         &armv7m_info);
1214
1215         if (retval == ERROR_FLASH_OPERATION_FAILED) {
1216                 LOG_ERROR("error executing stm32l4 flash write algorithm");
1217
1218                 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
1219
1220                 if (error & FLASH_WRPERR)
1221                         LOG_ERROR("flash memory write protected");
1222
1223                 if (error != 0) {
1224                         LOG_ERROR("flash write failed = %08" PRIx32, error);
1225                         /* Clear but report errors */
1226                         stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, error);
1227                         retval = ERROR_FAIL;
1228                 }
1229         }
1230
1231         target_free_working_area(target, source);
1232         target_free_working_area(target, write_algorithm);
1233
1234         destroy_reg_param(&reg_params[0]);
1235         destroy_reg_param(&reg_params[1]);
1236         destroy_reg_param(&reg_params[2]);
1237         destroy_reg_param(&reg_params[3]);
1238         destroy_reg_param(&reg_params[4]);
1239         destroy_reg_param(&reg_params[5]);
1240
1241         return retval;
1242 }
1243
1244 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
1245         uint32_t offset, uint32_t count)
1246 {
1247         int retval = ERROR_OK, retval2;
1248
1249         if (stm32l4_is_otp(bank) && !stm32l4_otp_is_enabled(bank)) {
1250                 LOG_ERROR("OTP memory is disabled for write commands");
1251                 return ERROR_FAIL;
1252         }
1253
1254         if (bank->target->state != TARGET_HALTED) {
1255                 LOG_ERROR("Target not halted");
1256                 return ERROR_TARGET_NOT_HALTED;
1257         }
1258
1259         /* The flash write must be aligned to a double word (8-bytes) boundary.
1260          * The flash infrastructure ensures it, do just a security check */
1261         assert(offset % 8 == 0);
1262         assert(count % 8 == 0);
1263
1264         /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1265          * data to be written does not go into a gap:
1266          * suppose buffer is fully contained in bank from sector 0 to sector
1267          * num->sectors - 1 and sectors are ordered according to offset
1268          */
1269         struct flash_sector *head = &bank->sectors[0];
1270         struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
1271
1272         while ((head < tail) && (offset >= (head + 1)->offset)) {
1273                 /* buffer does not intersect head nor gap behind head */
1274                 head++;
1275         }
1276
1277         while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
1278                 /* buffer does not intersect tail nor gap before tail */
1279                 --tail;
1280         }
1281
1282         LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
1283                 offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
1284
1285         /* Now check that there is no gap from head to tail, this should work
1286          * even for multiple or non-symmetric gaps
1287          */
1288         while (head < tail) {
1289                 if (head->offset + head->size != (head + 1)->offset) {
1290                         LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
1291                                 bank->base + head->offset + head->size,
1292                                 bank->base + (head + 1)->offset - 1);
1293                         retval = ERROR_FLASH_DST_OUT_OF_BANK;
1294                 }
1295                 head++;
1296         }
1297
1298         if (retval != ERROR_OK)
1299                 return retval;
1300
1301         retval = stm32l4_unlock_reg(bank);
1302         if (retval != ERROR_OK)
1303                 goto err_lock;
1304
1305         retval = stm32l4_write_block(bank, buffer, offset, count / 8);
1306
1307 err_lock:
1308         retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
1309
1310         if (retval != ERROR_OK) {
1311                 LOG_ERROR("block write failed");
1312                 return retval;
1313         }
1314         return retval2;
1315 }
1316
1317 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
1318 {
1319         int retval;
1320
1321         /* try reading possible IDCODE registers, in the following order */
1322         uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
1323
1324         for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
1325                 retval = target_read_u32(bank->target, dbgmcu_idcode[i], id);
1326                 if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
1327                         return ERROR_OK;
1328         }
1329
1330         LOG_ERROR("can't get the device id");
1331         return (retval == ERROR_OK) ? ERROR_FAIL : retval;
1332 }
1333
1334 static const char *get_stm32l4_rev_str(struct flash_bank *bank)
1335 {
1336         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1337         const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1338         assert(part_info);
1339
1340         const uint16_t rev_id = stm32l4_info->idcode >> 16;
1341         for (unsigned int i = 0; i < part_info->num_revs; i++) {
1342                 if (rev_id == part_info->revs[i].rev)
1343                         return part_info->revs[i].str;
1344         }
1345         return "'unknown'";
1346 }
1347
1348 static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
1349 {
1350         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1351         assert(stm32l4_info->part_info);
1352         return stm32l4_is_otp(bank) ? "OTP" :
1353                         stm32l4_info->dual_bank_mode ? "Flash dual" :
1354                         "Flash single";
1355 }
1356
1357 static int stm32l4_probe(struct flash_bank *bank)
1358 {
1359         struct target *target = bank->target;
1360         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1361         const struct stm32l4_part_info *part_info;
1362         uint16_t flash_size_kb = 0xffff;
1363         uint32_t options;
1364
1365         stm32l4_info->probed = false;
1366
1367         /* read stm32 device id registers */
1368         int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
1369         if (retval != ERROR_OK)
1370                 return retval;
1371
1372         const uint32_t device_id = stm32l4_info->idcode & 0xFFF;
1373
1374         for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
1375                 if (device_id == stm32l4_parts[n].id) {
1376                         stm32l4_info->part_info = &stm32l4_parts[n];
1377                         break;
1378                 }
1379         }
1380
1381         if (!stm32l4_info->part_info) {
1382                 LOG_WARNING("Cannot identify target as an %s family device.", device_families);
1383                 return ERROR_FAIL;
1384         }
1385
1386         part_info = stm32l4_info->part_info;
1387         const char *rev_str = get_stm32l4_rev_str(bank);
1388         const uint16_t rev_id = stm32l4_info->idcode >> 16;
1389
1390         LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
1391                         stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
1392
1393         stm32l4_info->flash_regs = stm32l4_info->part_info->default_flash_regs;
1394
1395         /* read flash option register */
1396         retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &options);
1397         if (retval != ERROR_OK)
1398                 return retval;
1399
1400         stm32l4_sync_rdp_tzen(bank, options);
1401
1402         if (part_info->flags & F_HAS_TZ)
1403                 LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1404                                 stm32l4_info->tzen,
1405                                 stm32l4_info->tzen ? "enabled" : "disabled");
1406
1407         LOG_INFO("RDP level %s (0x%02X)",
1408                         stm32l4_info->rdp == RDP_LEVEL_0 ? "0" : stm32l4_info->rdp == RDP_LEVEL_0_5 ? "0.5" : "1",
1409                         stm32l4_info->rdp);
1410
1411         if (stm32l4_is_otp(bank)) {
1412                 bank->size = part_info->otp_size;
1413
1414                 LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base);
1415
1416                 /* OTP memory is considered as one sector */
1417                 free(bank->sectors);
1418                 bank->num_sectors = 1;
1419                 bank->sectors = alloc_block_array(0, part_info->otp_size, 1);
1420
1421                 if (!bank->sectors) {
1422                         LOG_ERROR("failed to allocate bank sectors");
1423                         return ERROR_FAIL;
1424                 }
1425
1426                 stm32l4_info->probed = true;
1427                 return ERROR_OK;
1428         } else if (bank->base != STM32_FLASH_BANK_BASE) {
1429                 LOG_ERROR("invalid bank base address");
1430                 return ERROR_FAIL;
1431         }
1432
1433         /* get flash size from target. */
1434         retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
1435
1436         /* failed reading flash size or flash size invalid (early silicon),
1437          * default to max target family */
1438         if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
1439                         || flash_size_kb > part_info->max_flash_size_kb) {
1440                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1441                         part_info->max_flash_size_kb);
1442                 flash_size_kb = part_info->max_flash_size_kb;
1443         }
1444
1445         /* if the user sets the size manually then ignore the probed value
1446          * this allows us to work around devices that have a invalid flash size register value */
1447         if (stm32l4_info->user_bank_size) {
1448                 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1449                 flash_size_kb = stm32l4_info->user_bank_size / 1024;
1450         }
1451
1452         LOG_INFO("flash size = %dkbytes", flash_size_kb);
1453
1454         /* did we assign a flash size? */
1455         assert((flash_size_kb != 0xffff) && flash_size_kb);
1456
1457         stm32l4_info->bank1_sectors = 0;
1458         stm32l4_info->hole_sectors = 0;
1459
1460         int num_pages = 0;
1461         int page_size_kb = 0;
1462
1463         stm32l4_info->dual_bank_mode = false;
1464         bool use_dbank_bit = false;
1465
1466         switch (device_id) {
1467         case 0x415: /* STM32L47/L48xx */
1468         case 0x461: /* STM32L49/L4Axx */
1469                 /* if flash size is max (1M) the device is always dual bank
1470                  * 0x415: has variants with 512K
1471                  * 0x461: has variants with 512 and 256
1472                  * for these variants:
1473                  *   if DUAL_BANK = 0 -> single bank
1474                  *   else -> dual bank without gap
1475                  * note: the page size is invariant
1476                  */
1477                 page_size_kb = 2;
1478                 num_pages = flash_size_kb / page_size_kb;
1479                 stm32l4_info->bank1_sectors = num_pages;
1480
1481                 /* check DUAL_BANK bit[21] if the flash is less than 1M */
1482                 if (flash_size_kb == 1024 || (options & BIT(21))) {
1483                         stm32l4_info->dual_bank_mode = true;
1484                         stm32l4_info->bank1_sectors = num_pages / 2;
1485                 }
1486                 break;
1487         case 0x435: /* STM32L43/L44xx */
1488         case 0x460: /* STM32G07/G08xx */
1489         case 0x462: /* STM32L45/L46xx */
1490         case 0x464: /* STM32L41/L42xx */
1491         case 0x466: /* STM32G03/G04xx */
1492         case 0x468: /* STM32G43/G44xx */
1493         case 0x479: /* STM32G49/G4Axx */
1494         case 0x497: /* STM32WLEx */
1495                 /* single bank flash */
1496                 page_size_kb = 2;
1497                 num_pages = flash_size_kb / page_size_kb;
1498                 stm32l4_info->bank1_sectors = num_pages;
1499                 break;
1500         case 0x469: /* STM32G47/G48xx */
1501                 /* STM32G47/8 can be single/dual bank:
1502                  *   if DUAL_BANK = 0 -> single bank
1503                  *   else -> dual bank WITH gap
1504                  */
1505                 page_size_kb = 4;
1506                 num_pages = flash_size_kb / page_size_kb;
1507                 stm32l4_info->bank1_sectors = num_pages;
1508                 if (options & BIT(22)) {
1509                         stm32l4_info->dual_bank_mode = true;
1510                         page_size_kb = 2;
1511                         num_pages = flash_size_kb / page_size_kb;
1512                         stm32l4_info->bank1_sectors = num_pages / 2;
1513
1514                         /* for devices with trimmed flash, there is a gap between both banks */
1515                         stm32l4_info->hole_sectors =
1516                                 (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
1517                 }
1518                 break;
1519         case 0x470: /* STM32L4R/L4Sxx */
1520         case 0x471: /* STM32L4P5/L4Q5x */
1521                 /* STM32L4R/S can be single/dual bank:
1522                  *   if size = 2M check DBANK bit(22)
1523                  *   if size = 1M check DB1M bit(21)
1524                  * STM32L4P/Q can be single/dual bank
1525                  *   if size = 1M check DBANK bit(22)
1526                  *   if size = 512K check DB512K bit(21)
1527                  */
1528                 page_size_kb = 8;
1529                 num_pages = flash_size_kb / page_size_kb;
1530                 stm32l4_info->bank1_sectors = num_pages;
1531                 use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb;
1532                 if ((use_dbank_bit && (options & BIT(22))) ||
1533                         (!use_dbank_bit && (options & BIT(21)))) {
1534                         stm32l4_info->dual_bank_mode = true;
1535                         page_size_kb = 4;
1536                         num_pages = flash_size_kb / page_size_kb;
1537                         stm32l4_info->bank1_sectors = num_pages / 2;
1538                 }
1539                 break;
1540         case 0x472: /* STM32L55/L56xx */
1541                 /* STM32L55/L56xx can be single/dual bank:
1542                  *   if size = 512K check DBANK bit(22)
1543                  *   if size = 256K check DB256K bit(21)
1544                  */
1545                 page_size_kb = 4;
1546                 num_pages = flash_size_kb / page_size_kb;
1547                 stm32l4_info->bank1_sectors = num_pages;
1548                 use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb;
1549                 if ((use_dbank_bit && (options & BIT(22))) ||
1550                         (!use_dbank_bit && (options & BIT(21)))) {
1551                         stm32l4_info->dual_bank_mode = true;
1552                         page_size_kb = 2;
1553                         num_pages = flash_size_kb / page_size_kb;
1554                         stm32l4_info->bank1_sectors = num_pages / 2;
1555                 }
1556                 break;
1557         case 0x495: /* STM32WB5x */
1558         case 0x496: /* STM32WB3x */
1559                 /* single bank flash */
1560                 page_size_kb = 4;
1561                 num_pages = flash_size_kb / page_size_kb;
1562                 stm32l4_info->bank1_sectors = num_pages;
1563                 break;
1564         default:
1565                 LOG_ERROR("unsupported device");
1566                 return ERROR_FAIL;
1567         }
1568
1569         LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
1570
1571         const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
1572
1573         if (gap_size_kb != 0) {
1574                 LOG_INFO("gap detected from 0x%08x to 0x%08x",
1575                         STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
1576                                 * page_size_kb * 1024,
1577                         STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
1578                                 * page_size_kb + gap_size_kb) * 1024 - 1);
1579         }
1580
1581         /* number of significant bits in WRPxxR differs per device,
1582          * always right adjusted, on some devices non-implemented
1583          * bits read as '0', on others as '1' ...
1584          * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
1585          */
1586
1587         /* use *max_flash_size* instead of actual size as the trimmed versions
1588          * certainly use the same number of bits
1589          * max_flash_size is always power of two, so max_pages too
1590          */
1591         uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
1592         assert(IS_PWR_OF_2(max_pages));
1593
1594         /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
1595         stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
1596         assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
1597         LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
1598
1599         free(bank->sectors);
1600
1601         bank->size = (flash_size_kb + gap_size_kb) * 1024;
1602         bank->num_sectors = num_pages;
1603         bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
1604         if (!bank->sectors) {
1605                 LOG_ERROR("failed to allocate bank sectors");
1606                 return ERROR_FAIL;
1607         }
1608
1609         for (unsigned int i = 0; i < bank->num_sectors; i++) {
1610                 bank->sectors[i].offset = i * page_size_kb * 1024;
1611                 /* in dual bank configuration, if there is a gap between banks
1612                  * we fix up the sector offset to consider this gap */
1613                 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
1614                         bank->sectors[i].offset += gap_size_kb * 1024;
1615                 bank->sectors[i].size = page_size_kb * 1024;
1616                 bank->sectors[i].is_erased = -1;
1617                 bank->sectors[i].is_protected = 1;
1618         }
1619
1620         stm32l4_info->probed = true;
1621         return ERROR_OK;
1622 }
1623
1624 static int stm32l4_auto_probe(struct flash_bank *bank)
1625 {
1626         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1627         if (stm32l4_info->probed)
1628                 return ERROR_OK;
1629
1630         return stm32l4_probe(bank);
1631 }
1632
1633 static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd)
1634 {
1635         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1636         const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1637
1638         if (part_info) {
1639                 const uint16_t rev_id = stm32l4_info->idcode >> 16;
1640                 command_print_sameline(cmd, "%s - Rev %s : 0x%04x", part_info->device_str,
1641                                 get_stm32l4_rev_str(bank), rev_id);
1642                 if (stm32l4_info->probed)
1643                         command_print_sameline(cmd, " - %s-bank", get_stm32l4_bank_type_str(bank));
1644         } else {
1645                 command_print_sameline(cmd, "Cannot identify target as an %s device", device_families);
1646         }
1647
1648         return ERROR_OK;
1649 }
1650
1651 static int stm32l4_mass_erase(struct flash_bank *bank)
1652 {
1653         int retval, retval2;
1654         struct target *target = bank->target;
1655         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1656
1657         if (stm32l4_is_otp(bank)) {
1658                 LOG_ERROR("cannot erase OTP memory");
1659                 return ERROR_FLASH_OPER_UNSUPPORTED;
1660         }
1661
1662         uint32_t action = FLASH_MER1;
1663
1664         if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
1665                 action |= FLASH_MER2;
1666
1667         if (target->state != TARGET_HALTED) {
1668                 LOG_ERROR("Target not halted");
1669                 return ERROR_TARGET_NOT_HALTED;
1670         }
1671
1672         retval = stm32l4_unlock_reg(bank);
1673         if (retval != ERROR_OK)
1674                 goto err_lock;
1675
1676         /* mass erase flash memory */
1677         retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
1678         if (retval != ERROR_OK)
1679                 goto err_lock;
1680
1681         retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action);
1682         if (retval != ERROR_OK)
1683                 goto err_lock;
1684
1685         retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action | FLASH_STRT);
1686         if (retval != ERROR_OK)
1687                 goto err_lock;
1688
1689         retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1690
1691 err_lock:
1692         retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
1693
1694         if (retval != ERROR_OK)
1695                 return retval;
1696
1697         return retval2;
1698 }
1699
1700 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
1701 {
1702         if (CMD_ARGC < 1) {
1703                 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
1704                 return ERROR_COMMAND_SYNTAX_ERROR;
1705         }
1706
1707         struct flash_bank *bank;
1708         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1709         if (retval != ERROR_OK)
1710                 return retval;
1711
1712         retval = stm32l4_mass_erase(bank);
1713         if (retval == ERROR_OK)
1714                 command_print(CMD, "stm32l4x mass erase complete");
1715         else
1716                 command_print(CMD, "stm32l4x mass erase failed");
1717
1718         return retval;
1719 }
1720
1721 COMMAND_HANDLER(stm32l4_handle_option_read_command)
1722 {
1723         if (CMD_ARGC < 2) {
1724                 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
1725                 return ERROR_COMMAND_SYNTAX_ERROR;
1726         }
1727
1728         struct flash_bank *bank;
1729         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1730         if (retval != ERROR_OK)
1731                 return retval;
1732
1733         uint32_t reg_offset, reg_addr;
1734         uint32_t value = 0;
1735
1736         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1737         reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
1738
1739         retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
1740         if (retval != ERROR_OK)
1741                 return retval;
1742
1743         command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
1744
1745         return retval;
1746 }
1747
1748 COMMAND_HANDLER(stm32l4_handle_option_write_command)
1749 {
1750         if (CMD_ARGC < 3) {
1751                 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
1752                 return ERROR_COMMAND_SYNTAX_ERROR;
1753         }
1754
1755         struct flash_bank *bank;
1756         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1757         if (retval != ERROR_OK)
1758                 return retval;
1759
1760         uint32_t reg_offset;
1761         uint32_t value = 0;
1762         uint32_t mask = 0xFFFFFFFF;
1763
1764         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1765         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1766
1767         if (CMD_ARGC > 3)
1768                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
1769
1770         command_print(CMD, "%s Option written.\n"
1771                                 "INFO: a reset or power cycle is required "
1772                                 "for the new settings to take effect.", bank->driver->name);
1773
1774         retval = stm32l4_write_option(bank, reg_offset, value, mask);
1775         return retval;
1776 }
1777
1778 COMMAND_HANDLER(stm32l4_handle_option_load_command)
1779 {
1780         if (CMD_ARGC != 1)
1781                 return ERROR_COMMAND_SYNTAX_ERROR;
1782
1783         struct flash_bank *bank;
1784         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1785         if (retval != ERROR_OK)
1786                 return retval;
1787
1788         retval = stm32l4_unlock_reg(bank);
1789         if (retval != ERROR_OK)
1790                 return retval;
1791
1792         retval = stm32l4_unlock_option_reg(bank);
1793         if (retval != ERROR_OK)
1794                 return retval;
1795
1796         /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
1797          * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
1798          * "Note: If the read protection is set while the debugger is still
1799          * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
1800          */
1801         retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH);
1802
1803         command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
1804
1805         /* Need to re-probe after change */
1806         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1807         stm32l4_info->probed = false;
1808
1809         return retval;
1810 }
1811
1812 COMMAND_HANDLER(stm32l4_handle_lock_command)
1813 {
1814         struct target *target = NULL;
1815
1816         if (CMD_ARGC < 1)
1817                 return ERROR_COMMAND_SYNTAX_ERROR;
1818
1819         struct flash_bank *bank;
1820         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1821         if (retval != ERROR_OK)
1822                 return retval;
1823
1824         if (stm32l4_is_otp(bank)) {
1825                 LOG_ERROR("cannot lock/unlock OTP memory");
1826                 return ERROR_FLASH_OPER_UNSUPPORTED;
1827         }
1828
1829         target = bank->target;
1830
1831         if (target->state != TARGET_HALTED) {
1832                 LOG_ERROR("Target not halted");
1833                 return ERROR_TARGET_NOT_HALTED;
1834         }
1835
1836         /* set readout protection level 1 by erasing the RDP option byte */
1837         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1838         if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
1839                         RDP_LEVEL_1, FLASH_RDP_MASK) != ERROR_OK) {
1840                 command_print(CMD, "%s failed to lock device", bank->driver->name);
1841                 return ERROR_OK;
1842         }
1843
1844         return ERROR_OK;
1845 }
1846
1847 COMMAND_HANDLER(stm32l4_handle_unlock_command)
1848 {
1849         struct target *target = NULL;
1850
1851         if (CMD_ARGC < 1)
1852                 return ERROR_COMMAND_SYNTAX_ERROR;
1853
1854         struct flash_bank *bank;
1855         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1856         if (retval != ERROR_OK)
1857                 return retval;
1858
1859         if (stm32l4_is_otp(bank)) {
1860                 LOG_ERROR("cannot lock/unlock OTP memory");
1861                 return ERROR_FLASH_OPER_UNSUPPORTED;
1862         }
1863
1864         target = bank->target;
1865
1866         if (target->state != TARGET_HALTED) {
1867                 LOG_ERROR("Target not halted");
1868                 return ERROR_TARGET_NOT_HALTED;
1869         }
1870
1871         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1872         if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
1873                         RDP_LEVEL_0, FLASH_RDP_MASK) != ERROR_OK) {
1874                 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1875                 return ERROR_OK;
1876         }
1877
1878         return ERROR_OK;
1879 }
1880
1881 COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
1882 {
1883         if (CMD_ARGC < 1 || CMD_ARGC > 2)
1884                 return ERROR_COMMAND_SYNTAX_ERROR;
1885
1886         struct flash_bank *bank;
1887         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1888         if (retval != ERROR_OK)
1889                 return retval;
1890
1891         if (stm32l4_is_otp(bank)) {
1892                 LOG_ERROR("OTP memory does not have write protection areas");
1893                 return ERROR_FLASH_OPER_UNSUPPORTED;
1894         }
1895
1896         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1897         enum stm32_bank_id dev_bank_id = STM32_ALL_BANKS;
1898         if (CMD_ARGC == 2) {
1899                 if (strcmp(CMD_ARGV[1], "bank1") == 0)
1900                         dev_bank_id = STM32_BANK1;
1901                 else if (strcmp(CMD_ARGV[1], "bank2") == 0)
1902                         dev_bank_id = STM32_BANK2;
1903                 else
1904                         return ERROR_COMMAND_ARGUMENT_INVALID;
1905         }
1906
1907         if (dev_bank_id == STM32_BANK2) {
1908                 if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
1909                         LOG_ERROR("this device has no second bank");
1910                         return ERROR_FAIL;
1911                 } else if (!stm32l4_info->dual_bank_mode) {
1912                         LOG_ERROR("this device is configured in single bank mode");
1913                         return ERROR_FAIL;
1914                 }
1915         }
1916
1917         int ret;
1918         unsigned int n_wrp, i;
1919         struct stm32l4_wrp wrpxy[4];
1920
1921         ret = stm32l4_get_all_wrpxy(bank, dev_bank_id, wrpxy, &n_wrp);
1922         if (ret != ERROR_OK)
1923                 return ret;
1924
1925         /* use bitmap and range helpers to better describe protected areas */
1926         DECLARE_BITMAP(pages, bank->num_sectors);
1927         bitmap_zero(pages, bank->num_sectors);
1928
1929         for (i = 0; i < n_wrp; i++) {
1930                 if (wrpxy[i].used) {
1931                         for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
1932                                 set_bit(p, pages);
1933                 }
1934         }
1935
1936         /* we have at most 'n_wrp' WRP areas */
1937         struct range ranges[n_wrp];
1938         unsigned int ranges_count = 0;
1939
1940         bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1941
1942         if (ranges_count > 0) {
1943                 /* pretty-print the protected ranges */
1944                 char *ranges_str = range_print_alloc(ranges, ranges_count);
1945                 command_print(CMD, "protected areas: %s", ranges_str);
1946                 free(ranges_str);
1947         } else
1948                 command_print(CMD, "no protected areas");
1949
1950         return ERROR_OK;
1951 }
1952
1953 COMMAND_HANDLER(stm32l4_handle_otp_command)
1954 {
1955         if (CMD_ARGC < 2)
1956                 return ERROR_COMMAND_SYNTAX_ERROR;
1957
1958         struct flash_bank *bank;
1959         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1960         if (retval != ERROR_OK)
1961                 return retval;
1962
1963         if (!stm32l4_is_otp(bank)) {
1964                 command_print(CMD, "the specified bank is not an OTP memory");
1965                 return ERROR_FAIL;
1966         }
1967         if (strcmp(CMD_ARGV[1], "enable") == 0)
1968                 stm32l4_otp_enable(bank, true);
1969         else if (strcmp(CMD_ARGV[1], "disable") == 0)
1970                 stm32l4_otp_enable(bank, false);
1971         else if (strcmp(CMD_ARGV[1], "show") == 0)
1972                 command_print(CMD, "OTP memory bank #%d is %s for write commands.",
1973                                 bank->bank_number, stm32l4_otp_is_enabled(bank) ? "enabled" : "disabled");
1974         else
1975                 return ERROR_COMMAND_SYNTAX_ERROR;
1976
1977         return ERROR_OK;
1978 }
1979
1980 static const struct command_registration stm32l4_exec_command_handlers[] = {
1981         {
1982                 .name = "lock",
1983                 .handler = stm32l4_handle_lock_command,
1984                 .mode = COMMAND_EXEC,
1985                 .usage = "bank_id",
1986                 .help = "Lock entire flash device.",
1987         },
1988         {
1989                 .name = "unlock",
1990                 .handler = stm32l4_handle_unlock_command,
1991                 .mode = COMMAND_EXEC,
1992                 .usage = "bank_id",
1993                 .help = "Unlock entire protected flash device.",
1994         },
1995         {
1996                 .name = "mass_erase",
1997                 .handler = stm32l4_handle_mass_erase_command,
1998                 .mode = COMMAND_EXEC,
1999                 .usage = "bank_id",
2000                 .help = "Erase entire flash device.",
2001         },
2002         {
2003                 .name = "option_read",
2004                 .handler = stm32l4_handle_option_read_command,
2005                 .mode = COMMAND_EXEC,
2006                 .usage = "bank_id reg_offset",
2007                 .help = "Read & Display device option bytes.",
2008         },
2009         {
2010                 .name = "option_write",
2011                 .handler = stm32l4_handle_option_write_command,
2012                 .mode = COMMAND_EXEC,
2013                 .usage = "bank_id reg_offset value mask",
2014                 .help = "Write device option bit fields with provided value.",
2015         },
2016         {
2017                 .name = "wrp_info",
2018                 .handler = stm32l4_handle_wrp_info_command,
2019                 .mode = COMMAND_EXEC,
2020                 .usage = "bank_id [bank1|bank2]",
2021                 .help = "list the protected areas using WRP",
2022         },
2023         {
2024                 .name = "option_load",
2025                 .handler = stm32l4_handle_option_load_command,
2026                 .mode = COMMAND_EXEC,
2027                 .usage = "bank_id",
2028                 .help = "Force re-load of device options (will cause device reset).",
2029         },
2030         {
2031                 .name = "otp",
2032                 .handler = stm32l4_handle_otp_command,
2033                 .mode = COMMAND_EXEC,
2034                 .usage = "<bank_id> <enable|disable|show>",
2035                 .help = "OTP (One Time Programmable) memory write enable/disable",
2036         },
2037         COMMAND_REGISTRATION_DONE
2038 };
2039
2040 static const struct command_registration stm32l4_command_handlers[] = {
2041         {
2042                 .name = "stm32l4x",
2043                 .mode = COMMAND_ANY,
2044                 .help = "stm32l4x flash command group",
2045                 .usage = "",
2046                 .chain = stm32l4_exec_command_handlers,
2047         },
2048         COMMAND_REGISTRATION_DONE
2049 };
2050
2051 const struct flash_driver stm32l4x_flash = {
2052         .name = "stm32l4x",
2053         .commands = stm32l4_command_handlers,
2054         .flash_bank_command = stm32l4_flash_bank_command,
2055         .erase = stm32l4_erase,
2056         .protect = stm32l4_protect,
2057         .write = stm32l4_write,
2058         .read = default_flash_read,
2059         .probe = stm32l4_probe,
2060         .auto_probe = stm32l4_auto_probe,
2061         .erase_check = default_flash_blank_check,
2062         .protect_check = stm32l4_protect_check,
2063         .info = get_stm32l4_info,
2064         .free_driver_priv = default_flash_free_driver_priv,
2065 };