1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
24 #include <helper/binarybuffer.h>
25 #include <target/algorithm.h>
26 #include <target/armv7m.h>
28 /* STM32L4xxx series for reference.
31 * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/reference_manual/DM00083560.pdf
33 * STM32L476RG Datasheet (for erase timing)
34 * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00108832.pdf
37 * The device has normally two banks, but on 512 and 256 kiB devices an
38 * option byte is available to map all sectors to the first bank.
39 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
44 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
46 #define FLASH_ERASE_TIMEOUT 250
48 #define STM32_FLASH_BASE 0x40022000
49 #define STM32_FLASH_ACR 0x40022000
50 #define STM32_FLASH_KEYR 0x40022008
51 #define STM32_FLASH_OPTKEYR 0x4002200c
52 #define STM32_FLASH_SR 0x40022010
53 #define STM32_FLASH_CR 0x40022014
54 #define STM32_FLASH_OPTR 0x40022020
55 #define STM32_FLASH_WRP1AR 0x4002202c
56 #define STM32_FLASH_WRP2AR 0x40022030
57 #define STM32_FLASH_WRP1BR 0x4002204c
58 #define STM32_FLASH_WRP2BR 0x40022050
60 /* FLASH_CR register bits */
62 #define FLASH_PG (1 << 0)
63 #define FLASH_PER (1 << 1)
64 #define FLASH_MER1 (1 << 2)
65 #define FLASH_PAGE_SHIFT 3
66 #define FLASH_CR_BKER (1 << 11)
67 #define FLASH_MER2 (1 << 15)
68 #define FLASH_STRT (1 << 16)
69 #define FLASH_EOPIE (1 << 24)
70 #define FLASH_ERRIE (1 << 25)
71 #define FLASH_OPTLOCK (1 << 30)
72 #define FLASH_LOCK (1 << 31)
74 /* FLASH_SR register bits */
76 #define FLASH_BSY (1 << 16)
77 /* Fast programming not used => related errors not used*/
78 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
79 #define FLASH_SIZERR (1 << 6) /* Size error */
80 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
81 #define FLASH_WRPERR (1 << 4) /* Write protection error */
82 #define FLASH_PROGERR (1 << 3) /* Programming error */
83 #define FLASH_OPERR (1 << 1) /* Operation error */
84 #define FLASH_EOP (1 << 0) /* End of operation */
86 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
88 /* STM32_FLASH_OBR bit definitions (reading) */
90 #define OPT_DUALBANK 21 /* dual flash bank only */
92 /* register unlock keys */
94 #define KEY1 0x45670123
95 #define KEY2 0xCDEF89AB
97 /* option register unlock key */
98 #define OPTKEY1 0x08192A3B
99 #define OPTKEY2 0x4C5D6E7F
102 /* other registers */
103 #define DBGMCU_IDCODE 0xE0042000
104 #define FLASH_SIZE_REG 0x1FFF75E0
106 struct stm32l4_options {
108 uint16_t bank_b_start;
109 uint8_t user_options;
118 /* Fixme: Handle PCROP */
121 struct stm32l4_flash_bank {
122 struct stm32l4_options option_bytes;
126 /* flash bank stm32l4x <base> <size> 0 0 <target#>
128 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
130 struct stm32l4_flash_bank *stm32l4_info;
133 return ERROR_COMMAND_SYNTAX_ERROR;
135 stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
137 return ERROR_FAIL; /* Checkme: What better error to use?*/
138 bank->driver_priv = stm32l4_info;
140 stm32l4_info->probed = 0;
145 static inline int stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg)
150 static inline int stm32l4_get_flash_status(struct flash_bank *bank, uint32_t *status)
152 struct target *target = bank->target;
153 return target_read_u32(
154 target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR), status);
157 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
159 struct target *target = bank->target;
161 int retval = ERROR_OK;
163 /* wait for busy to clear */
165 retval = stm32l4_get_flash_status(bank, &status);
166 if (retval != ERROR_OK)
168 LOG_DEBUG("status: 0x%" PRIx32 "", status);
169 if ((status & FLASH_BSY) == 0)
171 if (timeout-- <= 0) {
172 LOG_ERROR("timed out waiting for flash");
179 if (status & FLASH_WRPERR) {
180 LOG_ERROR("stm32x device protected");
184 /* Clear but report errors */
185 if (status & FLASH_ERROR) {
186 /* If this operation fails, we ignore it and report the original
189 target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR),
190 status & FLASH_ERROR);
195 static int stm32l4_unlock_reg(struct target *target)
199 /* first check if not already unlocked
200 * otherwise writing on STM32_FLASH_KEYR will fail
202 int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
203 if (retval != ERROR_OK)
206 if ((ctrl & FLASH_LOCK) == 0)
209 /* unlock flash registers */
210 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
211 if (retval != ERROR_OK)
214 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
215 if (retval != ERROR_OK)
218 retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
219 if (retval != ERROR_OK)
222 if (ctrl & FLASH_LOCK) {
223 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
224 return ERROR_TARGET_FAILURE;
230 static int stm32l4_unlock_option_reg(struct target *target)
234 int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
235 if (retval != ERROR_OK)
238 if ((ctrl & FLASH_OPTLOCK) == 0)
241 /* unlock option registers */
242 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY1);
243 if (retval != ERROR_OK)
246 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY2);
247 if (retval != ERROR_OK)
250 retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
251 if (retval != ERROR_OK)
254 if (ctrl & FLASH_OPTLOCK) {
255 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
256 return ERROR_TARGET_FAILURE;
262 static int stm32l4_read_options(struct flash_bank *bank)
265 struct stm32l4_flash_bank *stm32l4_info = NULL;
266 struct target *target = bank->target;
268 stm32l4_info = bank->driver_priv;
270 /* read current option bytes */
271 int retval = target_read_u32(target, STM32_FLASH_OPTR, &optiondata);
272 if (retval != ERROR_OK)
275 stm32l4_info->option_bytes.user_options = (optiondata >> 8) & 0x3ffff;
276 stm32l4_info->option_bytes.RDP = optiondata & 0xff;
278 retval = target_read_u32(target, STM32_FLASH_WRP1AR, &optiondata);
279 if (retval != ERROR_OK)
281 stm32l4_info->option_bytes.wpr1a_start = optiondata & 0xff;
282 stm32l4_info->option_bytes.wpr1a_end = (optiondata >> 16) & 0xff;
284 retval = target_read_u32(target, STM32_FLASH_WRP2AR, &optiondata);
285 if (retval != ERROR_OK)
287 stm32l4_info->option_bytes.wpr2a_start = optiondata & 0xff;
288 stm32l4_info->option_bytes.wpr2a_end = (optiondata >> 16) & 0xff;
290 retval = target_read_u32(target, STM32_FLASH_WRP1BR, &optiondata);
291 if (retval != ERROR_OK)
293 stm32l4_info->option_bytes.wpr1b_start = optiondata & 0xff;
294 stm32l4_info->option_bytes.wpr1b_end = (optiondata >> 16) & 0xff;
296 retval = target_read_u32(target, STM32_FLASH_WRP2BR, &optiondata);
297 if (retval != ERROR_OK)
299 stm32l4_info->option_bytes.wpr2b_start = optiondata & 0xff;
300 stm32l4_info->option_bytes.wpr2b_end = (optiondata >> 16) & 0xff;
302 if (stm32l4_info->option_bytes.RDP != 0xAA)
303 LOG_INFO("Device Security Bit Set");
308 static int stm32l4_write_options(struct flash_bank *bank)
310 struct stm32l4_flash_bank *stm32l4_info = NULL;
311 struct target *target = bank->target;
314 stm32l4_info = bank->driver_priv;
319 int retval = stm32l4_unlock_option_reg(target);
320 if (retval != ERROR_OK)
322 /* FIXME: Implement Option writing!*/
326 static int stm32l4_protect_check(struct flash_bank *bank)
328 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
330 /* read write protection settings */
331 int retval = stm32l4_read_options(bank);
332 if (retval != ERROR_OK) {
333 LOG_DEBUG("unable to read option bytes");
337 for (int i = 0; i < bank->num_sectors; i++) {
338 if (i < stm32l4_info->option_bytes.bank_b_start) {
339 if (((i >= stm32l4_info->option_bytes.wpr1a_start) &&
340 (i <= stm32l4_info->option_bytes.wpr1a_end)) ||
341 ((i >= stm32l4_info->option_bytes.wpr2a_start) &&
342 (i <= stm32l4_info->option_bytes.wpr2a_end)))
343 bank->sectors[i].is_protected = 1;
345 bank->sectors[i].is_protected = 0;
348 snb = i - stm32l4_info->option_bytes.bank_b_start + 256;
349 if (((snb >= stm32l4_info->option_bytes.wpr1b_start) &&
350 (snb <= stm32l4_info->option_bytes.wpr1b_end)) ||
351 ((snb >= stm32l4_info->option_bytes.wpr2b_start) &&
352 (snb <= stm32l4_info->option_bytes.wpr2b_end)))
353 bank->sectors[i].is_protected = 1;
355 bank->sectors[i].is_protected = 0;
361 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
363 struct target *target = bank->target;
366 assert(first < bank->num_sectors);
367 assert(last < bank->num_sectors);
369 if (bank->target->state != TARGET_HALTED) {
370 LOG_ERROR("Target not halted");
371 return ERROR_TARGET_NOT_HALTED;
375 retval = stm32l4_unlock_reg(target);
376 if (retval != ERROR_OK)
381 To erase a sector, follow the procedure below:
382 1. Check that no Flash memory operation is ongoing by
383 checking the BSY bit in the FLASH_SR register
384 2. Set the PER bit and select the page and bank
385 you wish to erase in the FLASH_CR register
386 3. Set the STRT bit in the FLASH_CR register
387 4. Wait for the BSY bit to be cleared
389 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
391 for (i = first; i <= last; i++) {
392 uint32_t erase_flags;
393 erase_flags = FLASH_PER | FLASH_STRT;
395 if (i >= stm32l4_info->option_bytes.bank_b_start) {
397 snb = (i - stm32l4_info->option_bytes.bank_b_start) + 256;
398 erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
400 erase_flags |= i << FLASH_PAGE_SHIFT;
401 retval = target_write_u32(target,
402 stm32l4_get_flash_reg(bank, STM32_FLASH_CR), erase_flags);
403 if (retval != ERROR_OK)
406 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
407 if (retval != ERROR_OK)
410 bank->sectors[i].is_erased = 1;
413 retval = target_write_u32(
414 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
415 if (retval != ERROR_OK)
421 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
423 struct target *target = bank->target;
424 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
426 if (target->state != TARGET_HALTED) {
427 LOG_ERROR("Target not halted");
428 return ERROR_TARGET_NOT_HALTED;
431 /* read protection settings */
432 int retval = stm32l4_read_options(bank);
433 if (retval != ERROR_OK) {
434 LOG_DEBUG("unable to read option bytes");
439 /* FIXME: Write First and last in a valid WRPxx_start/end combo*/
440 retval = stm32l4_write_options(bank);
441 if (retval != ERROR_OK)
447 /* Count is in halfwords */
448 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
449 uint32_t offset, uint32_t count)
451 struct target *target = bank->target;
452 uint32_t buffer_size = 16384;
453 struct working_area *write_algorithm;
454 struct working_area *source;
455 uint32_t address = bank->base + offset;
456 struct reg_param reg_params[5];
457 struct armv7m_algorithm armv7m_info;
458 int retval = ERROR_OK;
460 /* See contrib/loaders/flash/stm32l4x.S for source and
461 * hints how to generate the data!
464 static const uint8_t stm32l4_flash_write_code[] = {
465 0xd0, 0xf8, 0x00, 0x80, 0xb8, 0xf1, 0x00, 0x0f, 0x21, 0xd0, 0x45, 0x68,
466 0xb8, 0xeb, 0x05, 0x06, 0x44, 0xbf, 0x76, 0x18, 0x36, 0x1a, 0x08, 0x2e,
467 0xf2, 0xd3, 0xdf, 0xf8, 0x36, 0x60, 0x66, 0x61, 0xf5, 0xe8, 0x02, 0x67,
468 0xe2, 0xe8, 0x02, 0x67, 0xbf, 0xf3, 0x4f, 0x8f, 0x26, 0x69, 0x16, 0xf4,
469 0x80, 0x3f, 0xfb, 0xd1, 0x16, 0xf0, 0xfa, 0x0f, 0x07, 0xd1, 0x8d, 0x42,
470 0x28, 0xbf, 0x00, 0xf1, 0x08, 0x05, 0x45, 0x60, 0x01, 0x3b, 0x13, 0xb1,
471 0xda, 0xe7, 0x00, 0x21, 0x41, 0x60, 0x30, 0x46, 0x00, 0xbe, 0x01, 0x00,
475 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
476 &write_algorithm) != ERROR_OK) {
477 LOG_WARNING("no working area available, can't do block memory writes");
478 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
481 retval = target_write_buffer(target, write_algorithm->address,
482 sizeof(stm32l4_flash_write_code),
483 stm32l4_flash_write_code);
484 if (retval != ERROR_OK)
488 while (target_alloc_working_area_try(target, buffer_size, &source) !=
491 if (buffer_size <= 256) {
492 /* we already allocated the writing code, but failed to get a
493 * buffer, free the algorithm */
494 target_free_working_area(target, write_algorithm);
496 LOG_WARNING("no large enough working area available, can't do block memory writes");
497 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
501 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
502 armv7m_info.core_mode = ARM_MODE_THREAD;
504 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
505 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
506 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
507 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
508 init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash base */
510 buf_set_u32(reg_params[0].value, 0, 32, source->address);
511 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
512 buf_set_u32(reg_params[2].value, 0, 32, address);
513 buf_set_u32(reg_params[3].value, 0, 32, count / 4);
514 buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
516 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
519 source->address, source->size,
520 write_algorithm->address, 0,
523 if (retval == ERROR_FLASH_OPERATION_FAILED) {
524 LOG_ERROR("error executing stm32l4 flash write algorithm");
526 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
528 if (error & FLASH_WRPERR)
529 LOG_ERROR("flash memory write protected");
532 LOG_ERROR("flash write failed = %08" PRIx32, error);
533 /* Clear but report errors */
534 target_write_u32(target, STM32_FLASH_SR, error);
539 target_free_working_area(target, source);
540 target_free_working_area(target, write_algorithm);
542 destroy_reg_param(®_params[0]);
543 destroy_reg_param(®_params[1]);
544 destroy_reg_param(®_params[2]);
545 destroy_reg_param(®_params[3]);
546 destroy_reg_param(®_params[4]);
551 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
552 uint32_t offset, uint32_t count)
554 struct target *target = bank->target;
557 if (bank->target->state != TARGET_HALTED) {
558 LOG_ERROR("Target not halted");
559 return ERROR_TARGET_NOT_HALTED;
563 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment",
565 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
569 LOG_WARNING("Padding %d bytes to keep 8-byte write size",
571 count = (count + 7) & ~7;
572 /* This pads the write chunk with random bytes by overrunning the
573 * write buffer. Padding with the erased pattern 0xff is purely
574 * cosmetical, as 8-byte flash words are ECC secured and the first
575 * write will program the ECC bits. A second write would need
576 * to reprogramm these ECC bits.
577 * But this can only be done after erase!
581 retval = stm32l4_unlock_reg(target);
582 if (retval != ERROR_OK)
585 /* Only full double words (8-byte) can be programmed*/
586 retval = stm32l4_write_block(bank, buffer, offset, count / 2);
587 if (retval != ERROR_OK) {
588 LOG_WARNING("block write failed");
592 LOG_WARNING("block write succeeded");
593 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
596 static int stm32l4_probe(struct flash_bank *bank)
598 struct target *target = bank->target;
599 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
601 uint16_t flash_size_in_kb = 0xffff;
602 uint16_t max_flash_size_in_kb;
605 uint32_t base_address = 0x08000000;
607 stm32l4_info->probed = 0;
609 /* read stm32 device id register */
610 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
611 if (retval != ERROR_OK)
613 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
615 /* set max flash size depending on family */
616 switch (device_id & 0xfff) {
618 max_flash_size_in_kb = 1024;
621 max_flash_size_in_kb = 256;
624 LOG_WARNING("Cannot identify target as a STM32L4 family.");
628 /* get flash size from target. */
629 retval = target_read_u16(target, FLASH_SIZE_REG, &flash_size_in_kb);
631 /* failed reading flash size or flash size invalid (early silicon),
632 * default to max target family */
633 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
634 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
635 max_flash_size_in_kb);
636 flash_size_in_kb = max_flash_size_in_kb;
639 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
641 /* did we assign flash size? */
642 assert(flash_size_in_kb != 0xffff);
644 /* get options to for DUAL BANK. */
645 retval = target_read_u32(target, STM32_FLASH_OPTR, &options);
647 /* only devices with < 1024 kiB may be set to single bank dual banks */
648 if ((flash_size_in_kb == 1024) || !(options & OPT_DUALBANK))
649 stm32l4_info->option_bytes.bank_b_start = 256;
651 stm32l4_info->option_bytes.bank_b_start = flash_size_in_kb << 9;
653 /* did we assign flash size? */
654 assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
656 /* calculate numbers of pages */
657 int num_pages = flash_size_in_kb / 2;
659 /* check that calculation result makes sense */
660 assert(num_pages > 0);
664 bank->sectors = NULL;
667 bank->base = base_address;
668 bank->size = num_pages * (1 << 11);
669 bank->num_sectors = num_pages;
670 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
672 return ERROR_FAIL; /* Checkme: What better error to use?*/
674 for (i = 0; i < num_pages; i++) {
675 bank->sectors[i].offset = i << 11;
676 bank->sectors[i].size = 1 << 11;
677 bank->sectors[i].is_erased = -1;
678 bank->sectors[i].is_protected = 1;
681 stm32l4_info->probed = 1;
686 static int stm32l4_auto_probe(struct flash_bank *bank)
688 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
689 if (stm32l4_info->probed)
691 return stm32l4_probe(bank);
694 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
696 struct target *target = bank->target;
697 uint32_t dbgmcu_idcode;
699 /* read stm32 device id register */
700 int retval = target_read_u32(target, DBGMCU_IDCODE, &dbgmcu_idcode);
701 if (retval != ERROR_OK)
704 uint16_t device_id = dbgmcu_idcode & 0xfff;
705 uint8_t rev_id = dbgmcu_idcode >> 28;
706 uint8_t rev_minor = 0;
709 for (i = 16; i < 28; i++) {
710 if (dbgmcu_idcode & (1 << i))
716 const char *device_str;
720 device_str = "STM32L4xx";
724 device_str = "STM32L43x";
728 snprintf(buf, buf_size, "Cannot identify target as a STM32L4\n");
732 snprintf(buf, buf_size, "%s - Rev: %1d.%02d",
733 device_str, rev_id, rev_minor);
738 COMMAND_HANDLER(stm32l4_handle_lock_command)
740 struct target *target = NULL;
741 struct stm32l4_flash_bank *stm32l4_info = NULL;
744 return ERROR_COMMAND_SYNTAX_ERROR;
746 struct flash_bank *bank;
747 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
748 if (ERROR_OK != retval)
751 stm32l4_info = bank->driver_priv;
752 target = bank->target;
754 if (target->state != TARGET_HALTED) {
755 LOG_ERROR("Target not halted");
756 return ERROR_TARGET_NOT_HALTED;
759 if (stm32l4_read_options(bank) != ERROR_OK) {
760 command_print(CMD_CTX, "%s failed to read options",
765 /* set readout protection */
766 stm32l4_info->option_bytes.RDP = 0;
768 if (stm32l4_write_options(bank) != ERROR_OK) {
769 command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
773 command_print(CMD_CTX, "%s locked", bank->driver->name);
778 COMMAND_HANDLER(stm32l4_handle_unlock_command)
780 struct target *target = NULL;
781 struct stm32l4_flash_bank *stm32l4_info = NULL;
784 return ERROR_COMMAND_SYNTAX_ERROR;
786 struct flash_bank *bank;
787 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
788 if (ERROR_OK != retval)
791 stm32l4_info = bank->driver_priv;
792 target = bank->target;
794 if (target->state != TARGET_HALTED) {
795 LOG_ERROR("Target not halted");
796 return ERROR_TARGET_NOT_HALTED;
799 if (stm32l4_read_options(bank) != ERROR_OK) {
800 command_print(CMD_CTX, "%s failed to read options", bank->driver->name);
804 /* clear readout protection and complementary option bytes
805 * this will also force a device unlock if set */
806 stm32l4_info->option_bytes.RDP = 0xAA;
808 if (stm32l4_write_options(bank) != ERROR_OK) {
809 command_print(CMD_CTX, "%s failed to unlock device",
814 command_print(CMD_CTX, "%s unlocked.\n"
815 "INFO: a reset or power cycle is required "
816 "for the new settings to take effect.", bank->driver->name);
821 static int stm32l4_mass_erase(struct flash_bank *bank, uint32_t action)
824 struct target *target = bank->target;
826 if (target->state != TARGET_HALTED) {
827 LOG_ERROR("Target not halted");
828 return ERROR_TARGET_NOT_HALTED;
831 retval = stm32l4_unlock_reg(target);
832 if (retval != ERROR_OK)
835 /* mass erase flash memory */
836 retval = target_write_u32(
837 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), action);
838 if (retval != ERROR_OK)
840 retval = target_write_u32(
841 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR),
842 action | FLASH_STRT);
843 if (retval != ERROR_OK)
846 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
847 if (retval != ERROR_OK)
850 retval = target_write_u32(
851 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
852 if (retval != ERROR_OK)
858 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
864 command_print(CMD_CTX, "stm32x mass_erase <STM32L4 bank>");
865 return ERROR_COMMAND_SYNTAX_ERROR;
868 struct flash_bank *bank;
869 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
870 if (ERROR_OK != retval)
873 action = FLASH_MER1 | FLASH_MER2;
874 retval = stm32l4_mass_erase(bank, action);
875 if (retval == ERROR_OK) {
876 /* set all sectors as erased */
877 for (i = 0; i < bank->num_sectors; i++)
878 bank->sectors[i].is_erased = 1;
880 command_print(CMD_CTX, "stm32x mass erase complete");
882 command_print(CMD_CTX, "stm32x mass erase failed");
888 static const struct command_registration stm32l4_exec_command_handlers[] = {
891 .handler = stm32l4_handle_lock_command,
892 .mode = COMMAND_EXEC,
894 .help = "Lock entire flash device.",
898 .handler = stm32l4_handle_unlock_command,
899 .mode = COMMAND_EXEC,
901 .help = "Unlock entire protected flash device.",
904 .name = "mass_erase",
905 .handler = stm32l4_handle_mass_erase_command,
906 .mode = COMMAND_EXEC,
908 .help = "Erase entire flash device.",
910 COMMAND_REGISTRATION_DONE
913 static const struct command_registration stm32l4_command_handlers[] = {
917 .help = "stm32l4x flash command group",
919 .chain = stm32l4_exec_command_handlers,
921 COMMAND_REGISTRATION_DONE
924 struct flash_driver stm32l4x_flash = {
926 .commands = stm32l4_command_handlers,
927 .flash_bank_command = stm32l4_flash_bank_command,
928 .erase = stm32l4_erase,
929 .protect = stm32l4_protect,
930 .write = stm32l4_write,
931 .read = default_flash_read,
932 .probe = stm32l4_probe,
933 .auto_probe = stm32l4_auto_probe,
934 .erase_check = default_flash_blank_check,
935 .protect_check = stm32l4_protect_check,
936 .info = get_stm32l4_info,