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   1 /***************************************************************************
   2  *   Copyright (C) 2015 by Uwe Bonnes                                      *
   3  *   bon@elektron.ikp.physik.tu-darmstadt.de                               *
   4  *                                                                         *
   5  *   Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics           *
   6  *   tarek.bouchkati@gmail.com                                             *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  20  ***************************************************************************/
  21
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "imp.h"
  27 #include <helper/binarybuffer.h>
  28 #include <target/algorithm.h>
  29 #include <target/armv7m.h>
  30 #include "bits.h"
  31 #include "stm32l4x.h"
  32
  33 /* STM32L4xxx series for reference.
  34  *
  35  * RM0351 (STM32L4x5/STM32L4x6)
  36  * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
  37  *
  38  * RM0394 (STM32L43x/44x/45x/46x)
  39  * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
  40  *
  41  * RM0432 (STM32L4R/4Sxx)
  42  * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
  43  *
  44  * STM32L476RG Datasheet (for erase timing)
  45  * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
  46  *
  47  * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
  48  * an option byte is available to map all sectors to the first bank.
  49  * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
  50  * handlers do!
  51  *
  52  * RM0394 devices have a single bank only.
  53  *
  54  * RM0432 devices have single and dual bank operating modes.
  55  *  - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
  56  *  - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
  57  * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
  58  *
  59  * Bank mode is controlled by two different bits in option bytes register.
  60  *  - for STM32L4R/Sxx
  61  *    In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
  62  *    In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
  63  *  - for STM32L4P5/Q5x
  64  *    In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
  65  *    In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
  66  *
  67  */
  68
  69 /* STM32WBxxx series for reference.
  70  *
  71  * RM0434 (STM32WB55)
  72  * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
  73  *
  74  * RM0471 (STM32WB50)
  75  * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
  76  */
  77
  78 /* STM32WLxxx series for reference.
  79  *
  80  * RM0461 (STM32WLEx)
  81  * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
  82  */
  83
  84 /*
  85  * STM32G0xxx series for reference.
  86  *
  87  * RM0444 (STM32G0x1)
  88  * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
  89  *
  90  * RM0454 (STM32G0x0)
  91  * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
  92  */
  93
  94 /*
  95  * STM32G4xxx series for reference.
  96  *
  97  * RM0440 (STM32G43x/44x/47x/48x)
  98  * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
  99  *
 100  * Cat. 2 devices have single bank only, page size is 2kByte.
 101  *
 102  * Cat. 3 devices have single and dual bank operating modes,
 103  * Page size is 2kByte (dual mode) or 4kByte (single mode).
 104  *
 105  * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
 106  * Both banks are treated as a single OpenOCD bank.
 107  */
 108
 109 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
 110
 111 #define FLASH_ERASE_TIMEOUT 250
 112
 113 struct stm32l4_rev {
 114         const uint16_t rev;
 115         const char *str;
 116 };
 117
 118 struct stm32l4_part_info {
 119         uint16_t id;
 120         const char *device_str;
 121         const struct stm32l4_rev *revs;
 122         const size_t num_revs;
 123         const uint16_t max_flash_size_kb;
 124         const bool has_dual_bank;
 125         const uint32_t flash_regs_base;
 126         const uint32_t fsize_addr;
 127 };
 128
 129 struct stm32l4_flash_bank {
 130         bool probed;
 131         uint32_t idcode;
 132         int bank1_sectors;
 133         bool dual_bank_mode;
 134         int hole_sectors;
 135         uint32_t user_bank_size;
 136         uint32_t wrpxxr_mask;
 137         const struct stm32l4_part_info *part_info;
 138 };
 139
 140 /* human readable list of families this drivers supports */
 141 static const char *device_families = "STM32L4/L4+/WB/WL/G4/G0";
 142
 143 static const struct stm32l4_rev stm32_415_revs[] = {
 144         { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
 145 };
 146
 147 static const struct stm32l4_rev stm32_435_revs[] = {
 148         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
 149 };
 150
 151 static const struct stm32l4_rev stm32_460_revs[] = {
 152         { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
 153 };
 154
 155 static const struct stm32l4_rev stm32_461_revs[] = {
 156         { 0x1000, "A" }, { 0x2000, "B" },
 157 };
 158
 159 static const struct stm32l4_rev stm32_462_revs[] = {
 160         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
 161 };
 162
 163 static const struct stm32l4_rev stm32_464_revs[] = {
 164         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
 165 };
 166
 167 static const struct stm32l4_rev stm32_466_revs[] = {
 168         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
 169 };
 170
 171 static const struct stm32l4_rev stm32_468_revs[] = {
 172         { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
 173 };
 174
 175 static const struct stm32l4_rev stm32_469_revs[] = {
 176         { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
 177 };
 178
 179 static const struct stm32l4_rev stm32_470_revs[] = {
 180         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
 181 };
 182
 183 static const struct stm32l4_rev stm32_471_revs[] = {
 184         { 0x1000, "1" },
 185 };
 186
 187 static const struct stm32l4_rev stm32_495_revs[] = {
 188         { 0x2001, "2.1" },
 189 };
 190
 191 static const struct stm32l4_rev stm32_497_revs[] = {
 192         { 0x1000, "1.0" },
 193 };
 194
 195 static const struct stm32l4_part_info stm32l4_parts[] = {
 196         {
 197           .id                    = 0x415,
 198           .revs                  = stm32_415_revs,
 199           .num_revs              = ARRAY_SIZE(stm32_415_revs),
 200           .device_str            = "STM32L47/L48xx",
 201           .max_flash_size_kb     = 1024,
 202           .has_dual_bank         = true,
 203           .flash_regs_base       = 0x40022000,
 204           .fsize_addr            = 0x1FFF75E0,
 205         },
 206         {
 207           .id                    = 0x435,
 208           .revs                  = stm32_435_revs,
 209           .num_revs              = ARRAY_SIZE(stm32_435_revs),
 210           .device_str            = "STM32L43/L44xx",
 211           .max_flash_size_kb     = 256,
 212           .has_dual_bank         = false,
 213           .flash_regs_base       = 0x40022000,
 214           .fsize_addr            = 0x1FFF75E0,
 215         },
 216         {
 217           .id                    = 0x460,
 218           .revs                  = stm32_460_revs,
 219           .num_revs              = ARRAY_SIZE(stm32_460_revs),
 220           .device_str            = "STM32G07/G08xx",
 221           .max_flash_size_kb     = 128,
 222           .has_dual_bank         = false,
 223           .flash_regs_base       = 0x40022000,
 224           .fsize_addr            = 0x1FFF75E0,
 225         },
 226         {
 227           .id                    = 0x461,
 228           .revs                  = stm32_461_revs,
 229           .num_revs              = ARRAY_SIZE(stm32_461_revs),
 230           .device_str            = "STM32L49/L4Axx",
 231           .max_flash_size_kb     = 1024,
 232           .has_dual_bank         = true,
 233           .flash_regs_base       = 0x40022000,
 234           .fsize_addr            = 0x1FFF75E0,
 235         },
 236         {
 237           .id                    = 0x462,
 238           .revs                  = stm32_462_revs,
 239           .num_revs              = ARRAY_SIZE(stm32_462_revs),
 240           .device_str            = "STM32L45/L46xx",
 241           .max_flash_size_kb     = 512,
 242           .has_dual_bank         = false,
 243           .flash_regs_base       = 0x40022000,
 244           .fsize_addr            = 0x1FFF75E0,
 245         },
 246         {
 247           .id                    = 0x464,
 248           .revs                  = stm32_464_revs,
 249           .num_revs              = ARRAY_SIZE(stm32_464_revs),
 250           .device_str            = "STM32L41/L42xx",
 251           .max_flash_size_kb     = 128,
 252           .has_dual_bank         = false,
 253           .flash_regs_base       = 0x40022000,
 254           .fsize_addr            = 0x1FFF75E0,
 255         },
 256         {
 257           .id                    = 0x466,
 258           .revs                  = stm32_466_revs,
 259           .num_revs              = ARRAY_SIZE(stm32_466_revs),
 260           .device_str            = "STM32G03/G04xx",
 261           .max_flash_size_kb     = 64,
 262           .has_dual_bank         = false,
 263           .flash_regs_base       = 0x40022000,
 264           .fsize_addr            = 0x1FFF75E0,
 265         },
 266         {
 267           .id                    = 0x468,
 268           .revs                  = stm32_468_revs,
 269           .num_revs              = ARRAY_SIZE(stm32_468_revs),
 270           .device_str            = "STM32G43/G44xx",
 271           .max_flash_size_kb     = 128,
 272           .has_dual_bank         = false,
 273           .flash_regs_base       = 0x40022000,
 274           .fsize_addr            = 0x1FFF75E0,
 275         },
 276         {
 277           .id                    = 0x469,
 278           .revs                  = stm32_469_revs,
 279           .num_revs              = ARRAY_SIZE(stm32_469_revs),
 280           .device_str            = "STM32G47/G48xx",
 281           .max_flash_size_kb     = 512,
 282           .has_dual_bank         = true,
 283           .flash_regs_base       = 0x40022000,
 284           .fsize_addr            = 0x1FFF75E0,
 285         },
 286         {
 287           .id                    = 0x470,
 288           .revs                  = stm32_470_revs,
 289           .num_revs              = ARRAY_SIZE(stm32_470_revs),
 290           .device_str            = "STM32L4R/L4Sxx",
 291           .max_flash_size_kb     = 2048,
 292           .has_dual_bank         = true,
 293           .flash_regs_base       = 0x40022000,
 294           .fsize_addr            = 0x1FFF75E0,
 295         },
 296         {
 297           .id                    = 0x471,
 298           .revs                  = stm32_471_revs,
 299           .num_revs              = ARRAY_SIZE(stm32_471_revs),
 300           .device_str            = "STM32L4P5/L4Q5x",
 301           .max_flash_size_kb     = 1024,
 302           .has_dual_bank         = true,
 303           .flash_regs_base       = 0x40022000,
 304           .fsize_addr            = 0x1FFF75E0,
 305         },
 306         {
 307           .id                    = 0x495,
 308           .revs                  = stm32_495_revs,
 309           .num_revs              = ARRAY_SIZE(stm32_495_revs),
 310           .device_str            = "STM32WB5x",
 311           .max_flash_size_kb     = 1024,
 312           .has_dual_bank         = false,
 313           .flash_regs_base       = 0x58004000,
 314           .fsize_addr            = 0x1FFF75E0,
 315         },
 316         {
 317           .id                    = 0x497,
 318           .revs                  = stm32_497_revs,
 319           .num_revs              = ARRAY_SIZE(stm32_497_revs),
 320           .device_str            = "STM32WLEx",
 321           .max_flash_size_kb     = 256,
 322           .has_dual_bank         = false,
 323           .flash_regs_base       = 0x58004000,
 324           .fsize_addr            = 0x1FFF75E0,
 325         },
 326 };
 327
 328 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
 329 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
 330 {
 331         struct stm32l4_flash_bank *stm32l4_info;
 332
 333         if (CMD_ARGC < 6)
 334                 return ERROR_COMMAND_SYNTAX_ERROR;
 335
 336         stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
 337         if (!stm32l4_info)
 338                 return ERROR_FAIL; /* Checkme: What better error to use?*/
 339         bank->driver_priv = stm32l4_info;
 340
 341         /* The flash write must be aligned to a double word (8-bytes) boundary.
 342          * Ask the flash infrastructure to ensure required alignment */
 343         bank->write_start_alignment = bank->write_end_alignment = 8;
 344
 345         stm32l4_info->probed = false;
 346         stm32l4_info->user_bank_size = bank->size;
 347
 348         return ERROR_OK;
 349 }
 350
 351 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
 352 {
 353         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 354         return stm32l4_info->part_info->flash_regs_base + reg_offset;
 355 }
 356
 357 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
 358 {
 359         return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
 360 }
 361
 362 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
 363 {
 364         return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
 365 }
 366
 367 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
 368 {
 369         uint32_t status;
 370         int retval = ERROR_OK;
 371
 372         /* wait for busy to clear */
 373         for (;;) {
 374                 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_SR, &status);
 375                 if (retval != ERROR_OK)
 376                         return retval;
 377                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 378                 if ((status & FLASH_BSY) == 0)
 379                         break;
 380                 if (timeout-- <= 0) {
 381                         LOG_ERROR("timed out waiting for flash");
 382                         return ERROR_FAIL;
 383                 }
 384                 alive_sleep(1);
 385         }
 386
 387
 388         if (status & FLASH_WRPERR) {
 389                 LOG_ERROR("stm32x device protected");
 390                 retval = ERROR_FAIL;
 391         }
 392
 393         /* Clear but report errors */
 394         if (status & FLASH_ERROR) {
 395                 if (retval == ERROR_OK)
 396                         retval = ERROR_FAIL;
 397                 /* If this operation fails, we ignore it and report the original
 398                  * retval
 399                  */
 400                 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, status & FLASH_ERROR);
 401         }
 402
 403         return retval;
 404 }
 405
 406 static int stm32l4_unlock_reg(struct flash_bank *bank)
 407 {
 408         uint32_t ctrl;
 409
 410         /* first check if not already unlocked
 411          * otherwise writing on STM32_FLASH_KEYR will fail
 412          */
 413         int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
 414         if (retval != ERROR_OK)
 415                 return retval;
 416
 417         if ((ctrl & FLASH_LOCK) == 0)
 418                 return ERROR_OK;
 419
 420         /* unlock flash registers */
 421         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY1);
 422         if (retval != ERROR_OK)
 423                 return retval;
 424
 425         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY2);
 426         if (retval != ERROR_OK)
 427                 return retval;
 428
 429         retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
 430         if (retval != ERROR_OK)
 431                 return retval;
 432
 433         if (ctrl & FLASH_LOCK) {
 434                 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
 435                 return ERROR_TARGET_FAILURE;
 436         }
 437
 438         return ERROR_OK;
 439 }
 440
 441 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
 442 {
 443         uint32_t ctrl;
 444
 445         int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
 446         if (retval != ERROR_OK)
 447                 return retval;
 448
 449         if ((ctrl & FLASH_OPTLOCK) == 0)
 450                 return ERROR_OK;
 451
 452         /* unlock option registers */
 453         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY1);
 454         if (retval != ERROR_OK)
 455                 return retval;
 456
 457         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY2);
 458         if (retval != ERROR_OK)
 459                 return retval;
 460
 461         retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
 462         if (retval != ERROR_OK)
 463                 return retval;
 464
 465         if (ctrl & FLASH_OPTLOCK) {
 466                 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
 467                 return ERROR_TARGET_FAILURE;
 468         }
 469
 470         return ERROR_OK;
 471 }
 472
 473 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
 474         uint32_t value, uint32_t mask)
 475 {
 476         uint32_t optiondata;
 477         int retval, retval2;
 478
 479         retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
 480         if (retval != ERROR_OK)
 481                 return retval;
 482
 483         retval = stm32l4_unlock_reg(bank);
 484         if (retval != ERROR_OK)
 485                 goto err_lock;
 486
 487         retval = stm32l4_unlock_option_reg(bank);
 488         if (retval != ERROR_OK)
 489                 goto err_lock;
 490
 491         optiondata = (optiondata & ~mask) | (value & mask);
 492
 493         retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
 494         if (retval != ERROR_OK)
 495                 goto err_lock;
 496
 497         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OPTSTRT);
 498         if (retval != ERROR_OK)
 499                 goto err_lock;
 500
 501         retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 502
 503 err_lock:
 504         retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK | FLASH_OPTLOCK);
 505
 506         if (retval != ERROR_OK)
 507                 return retval;
 508
 509         return retval2;
 510 }
 511
 512 static int stm32l4_protect_check(struct flash_bank *bank)
 513 {
 514         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 515
 516         uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
 517         stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar);
 518         stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br);
 519         if (stm32l4_info->part_info->has_dual_bank) {
 520                 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
 521                 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
 522         } else {
 523                 /* prevent unintialized errors */
 524                 wrp2ar = 0;
 525                 wrp2br = 0;
 526         }
 527
 528         const uint8_t wrp1a_start = wrp1ar & stm32l4_info->wrpxxr_mask;
 529         const uint8_t wrp1a_end = (wrp1ar >> 16) & stm32l4_info->wrpxxr_mask;
 530         const uint8_t wrp1b_start = wrp1br & stm32l4_info->wrpxxr_mask;
 531         const uint8_t wrp1b_end = (wrp1br >> 16) & stm32l4_info->wrpxxr_mask;
 532         const uint8_t wrp2a_start = wrp2ar & stm32l4_info->wrpxxr_mask;
 533         const uint8_t wrp2a_end = (wrp2ar >> 16) & stm32l4_info->wrpxxr_mask;
 534         const uint8_t wrp2b_start = wrp2br & stm32l4_info->wrpxxr_mask;
 535         const uint8_t wrp2b_end = (wrp2br >> 16) & stm32l4_info->wrpxxr_mask;
 536
 537         for (int i = 0; i < bank->num_sectors; i++) {
 538                 if (i < stm32l4_info->bank1_sectors) {
 539                         if (((i >= wrp1a_start) &&
 540                                  (i <= wrp1a_end)) ||
 541                                 ((i >= wrp1b_start) &&
 542                                  (i <= wrp1b_end)))
 543                                 bank->sectors[i].is_protected = 1;
 544                         else
 545                                 bank->sectors[i].is_protected = 0;
 546                 } else {
 547                         assert(stm32l4_info->part_info->has_dual_bank == true);
 548                         uint8_t snb;
 549                         snb = i - stm32l4_info->bank1_sectors;
 550                         if (((snb >= wrp2a_start) &&
 551                                  (snb <= wrp2a_end)) ||
 552                                 ((snb >= wrp2b_start) &&
 553                                  (snb <= wrp2b_end)))
 554                                 bank->sectors[i].is_protected = 1;
 555                         else
 556                                 bank->sectors[i].is_protected = 0;
 557                 }
 558         }
 559         return ERROR_OK;
 560 }
 561
 562 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
 563 {
 564         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 565         int i;
 566         int retval, retval2;
 567
 568         assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
 569
 570         if (bank->target->state != TARGET_HALTED) {
 571                 LOG_ERROR("Target not halted");
 572                 return ERROR_TARGET_NOT_HALTED;
 573         }
 574
 575         retval = stm32l4_unlock_reg(bank);
 576         if (retval != ERROR_OK)
 577                 goto err_lock;
 578
 579         /*
 580         Sector Erase
 581         To erase a sector, follow the procedure below:
 582         1. Check that no Flash memory operation is ongoing by
 583            checking the BSY bit in the FLASH_SR register
 584         2. Set the PER bit and select the page and bank
 585            you wish to erase in the FLASH_CR register
 586         3. Set the STRT bit in the FLASH_CR register
 587         4. Wait for the BSY bit to be cleared
 588          */
 589
 590         for (i = first; i <= last; i++) {
 591                 uint32_t erase_flags;
 592                 erase_flags = FLASH_PER | FLASH_STRT;
 593
 594                 if (i >= stm32l4_info->bank1_sectors) {
 595                         uint8_t snb;
 596                         snb = i - stm32l4_info->bank1_sectors;
 597                         erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
 598                 } else
 599                         erase_flags |= i << FLASH_PAGE_SHIFT;
 600                 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, erase_flags);
 601                 if (retval != ERROR_OK)
 602                         break;
 603
 604                 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 605                 if (retval != ERROR_OK)
 606                         break;
 607
 608                 bank->sectors[i].is_erased = 1;
 609         }
 610
 611 err_lock:
 612         retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
 613
 614         if (retval != ERROR_OK)
 615                 return retval;
 616
 617         return retval2;
 618 }
 619
 620 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
 621 {
 622         struct target *target = bank->target;
 623         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 624
 625         if (target->state != TARGET_HALTED) {
 626                 LOG_ERROR("Target not halted");
 627                 return ERROR_TARGET_NOT_HALTED;
 628         }
 629
 630         int ret = ERROR_OK;
 631         /* Bank 2 */
 632         uint32_t reg_value = 0xFF; /* Default to bank un-protected */
 633         if (last >= stm32l4_info->bank1_sectors) {
 634                 if (set == 1) {
 635                         uint8_t begin = first > stm32l4_info->bank1_sectors ? first : 0x00;
 636                         reg_value = ((last & 0xFF) << 16) | begin;
 637                 }
 638
 639                 ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
 640         }
 641         /* Bank 1 */
 642         reg_value = 0xFF; /* Default to bank un-protected */
 643         if (first < stm32l4_info->bank1_sectors) {
 644                 if (set == 1) {
 645                         uint8_t end = last >= stm32l4_info->bank1_sectors ? 0xFF : last;
 646                         reg_value = (end << 16) | (first & 0xFF);
 647                 }
 648
 649                 ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
 650         }
 651
 652         return ret;
 653 }
 654
 655 /* Count is in double-words */
 656 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
 657         uint32_t offset, uint32_t count)
 658 {
 659         struct target *target = bank->target;
 660         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 661         uint32_t buffer_size;
 662         struct working_area *write_algorithm;
 663         struct working_area *source;
 664         uint32_t address = bank->base + offset;
 665         struct reg_param reg_params[6];
 666         struct armv7m_algorithm armv7m_info;
 667         int retval = ERROR_OK;
 668
 669         static const uint8_t stm32l4_flash_write_code[] = {
 670 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
 671         };
 672
 673         if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
 674                         &write_algorithm) != ERROR_OK) {
 675                 LOG_WARNING("no working area available, can't do block memory writes");
 676                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 677         }
 678
 679         retval = target_write_buffer(target, write_algorithm->address,
 680                         sizeof(stm32l4_flash_write_code),
 681                         stm32l4_flash_write_code);
 682         if (retval != ERROR_OK) {
 683                 target_free_working_area(target, write_algorithm);
 684                 return retval;
 685         }
 686
 687         /* memory buffer, size *must* be multiple of dword plus one dword for rp and one for wp */
 688         buffer_size = target_get_working_area_avail(target) & ~(2 * sizeof(uint32_t) - 1);
 689         if (buffer_size < 256) {
 690                 LOG_WARNING("large enough working area not available, can't do block memory writes");
 691                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 692         } else if (buffer_size > 16384) {
 693                 /* probably won't benefit from more than 16k ... */
 694                 buffer_size = 16384;
 695         }
 696
 697         if (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 698                 LOG_ERROR("allocating working area failed");
 699                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 700         }
 701
 702         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 703         armv7m_info.core_mode = ARM_MODE_THREAD;
 704
 705         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
 706         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* buffer end */
 707         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* target address */
 708         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* count (double word-64bit) */
 709         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);    /* flash status register */
 710         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);    /* flash control register */
 711
 712         buf_set_u32(reg_params[0].value, 0, 32, source->address);
 713         buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
 714         buf_set_u32(reg_params[2].value, 0, 32, address);
 715         buf_set_u32(reg_params[3].value, 0, 32, count);
 716         buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base + STM32_FLASH_SR);
 717         buf_set_u32(reg_params[5].value, 0, 32, stm32l4_info->part_info->flash_regs_base + STM32_FLASH_CR);
 718
 719         retval = target_run_flash_async_algorithm(target, buffer, count, 8,
 720                         0, NULL,
 721                         ARRAY_SIZE(reg_params), reg_params,
 722                         source->address, source->size,
 723                         write_algorithm->address, 0,
 724                         &armv7m_info);
 725
 726         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 727                 LOG_ERROR("error executing stm32l4 flash write algorithm");
 728
 729                 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
 730
 731                 if (error & FLASH_WRPERR)
 732                         LOG_ERROR("flash memory write protected");
 733
 734                 if (error != 0) {
 735                         LOG_ERROR("flash write failed = %08" PRIx32, error);
 736                         /* Clear but report errors */
 737                         stm32l4_write_flash_reg(bank, STM32_FLASH_SR, error);
 738                         retval = ERROR_FAIL;
 739                 }
 740         }
 741
 742         target_free_working_area(target, source);
 743         target_free_working_area(target, write_algorithm);
 744
 745         destroy_reg_param(&reg_params[0]);
 746         destroy_reg_param(&reg_params[1]);
 747         destroy_reg_param(&reg_params[2]);
 748         destroy_reg_param(&reg_params[3]);
 749         destroy_reg_param(&reg_params[4]);
 750         destroy_reg_param(&reg_params[5]);
 751
 752         return retval;
 753 }
 754
 755 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
 756         uint32_t offset, uint32_t count)
 757 {
 758         int retval = ERROR_OK, retval2;
 759
 760         if (bank->target->state != TARGET_HALTED) {
 761                 LOG_ERROR("Target not halted");
 762                 return ERROR_TARGET_NOT_HALTED;
 763         }
 764
 765         /* The flash write must be aligned to a double word (8-bytes) boundary.
 766          * The flash infrastructure ensures it, do just a security check */
 767         assert(offset % 8 == 0);
 768         assert(count % 8 == 0);
 769
 770         /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
 771          * data to be written does not go into a gap:
 772          * suppose buffer is fully contained in bank from sector 0 to sector
 773          * num->sectors - 1 and sectors are ordered according to offset
 774          */
 775         struct flash_sector *head = &bank->sectors[0];
 776         struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
 777
 778         while ((head < tail) && (offset >= (head + 1)->offset)) {
 779                 /* buffer does not intersect head nor gap behind head */
 780                 head++;
 781         }
 782
 783         while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
 784                 /* buffer does not intersect tail nor gap before tail */
 785                 --tail;
 786         }
 787
 788         LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
 789                 offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
 790
 791         /* Now check that there is no gap from head to tail, this should work
 792          * even for multiple or non-symmetric gaps
 793          */
 794         while (head < tail) {
 795                 if (head->offset + head->size != (head + 1)->offset) {
 796                         LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
 797                                 bank->base + head->offset + head->size,
 798                                 bank->base + (head + 1)->offset - 1);
 799                         retval = ERROR_FLASH_DST_OUT_OF_BANK;
 800                 }
 801                 head++;
 802         }
 803
 804         if (retval != ERROR_OK)
 805                 return retval;
 806
 807         retval = stm32l4_unlock_reg(bank);
 808         if (retval != ERROR_OK)
 809                 goto err_lock;
 810
 811         retval = stm32l4_write_block(bank, buffer, offset, count / 8);
 812
 813 err_lock:
 814         retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
 815
 816         if (retval != ERROR_OK) {
 817                 LOG_ERROR("block write failed");
 818                 return retval;
 819         }
 820         return retval2;
 821 }
 822
 823 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
 824 {
 825         int retval;
 826
 827         /* try stm32l4/l4+/wb/g4 id register first, then stm32g0 id register */
 828         retval = target_read_u32(bank->target, DBGMCU_IDCODE_L4_G4, id);
 829         if ((retval != ERROR_OK) || ((*id & 0xfff) == 0) || ((*id & 0xfff) == 0xfff)) {
 830                 retval = target_read_u32(bank->target, DBGMCU_IDCODE_G0, id);
 831                 if ((retval != ERROR_OK) || ((*id & 0xfff) == 0) || ((*id & 0xfff) == 0xfff)) {
 832                         LOG_ERROR("can't get device id");
 833                         return (retval == ERROR_OK) ? ERROR_FAIL : retval;
 834                 }
 835         }
 836
 837         return retval;
 838 }
 839
 840 static int stm32l4_probe(struct flash_bank *bank)
 841 {
 842         struct target *target = bank->target;
 843         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 844         const struct stm32l4_part_info *part_info;
 845         uint16_t flash_size_kb = 0xffff;
 846         uint32_t device_id;
 847         uint32_t options;
 848
 849         stm32l4_info->probed = false;
 850
 851         /* read stm32 device id registers */
 852         int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
 853         if (retval != ERROR_OK)
 854                 return retval;
 855
 856         device_id = stm32l4_info->idcode & 0xFFF;
 857
 858         for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
 859                 if (device_id == stm32l4_parts[n].id)
 860                         stm32l4_info->part_info = &stm32l4_parts[n];
 861         }
 862
 863         if (!stm32l4_info->part_info) {
 864                 LOG_WARNING("Cannot identify target as an %s family device.", device_families);
 865                 return ERROR_FAIL;
 866         }
 867
 868         part_info = stm32l4_info->part_info;
 869
 870         char device_info[1024];
 871         retval = bank->driver->info(bank, device_info, sizeof(device_info));
 872         if (retval != ERROR_OK)
 873                 return retval;
 874
 875         LOG_INFO("device idcode = 0x%08" PRIx32 " (%s)", stm32l4_info->idcode, device_info);
 876
 877         /* get flash size from target. */
 878         retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
 879
 880         /* failed reading flash size or flash size invalid (early silicon),
 881          * default to max target family */
 882         if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
 883                         || flash_size_kb > part_info->max_flash_size_kb) {
 884                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 885                         part_info->max_flash_size_kb);
 886                 flash_size_kb = part_info->max_flash_size_kb;
 887         }
 888
 889         /* if the user sets the size manually then ignore the probed value
 890          * this allows us to work around devices that have a invalid flash size register value */
 891         if (stm32l4_info->user_bank_size) {
 892                 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
 893                 flash_size_kb = stm32l4_info->user_bank_size / 1024;
 894         }
 895
 896         LOG_INFO("flash size = %dkbytes", flash_size_kb);
 897
 898         /* did we assign a flash size? */
 899         assert((flash_size_kb != 0xffff) && flash_size_kb);
 900
 901         /* read flash option register */
 902         retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options);
 903         if (retval != ERROR_OK)
 904                 return retval;
 905
 906         stm32l4_info->bank1_sectors = 0;
 907         stm32l4_info->hole_sectors = 0;
 908
 909         int num_pages = 0;
 910         int page_size_kb = 0;
 911
 912         stm32l4_info->dual_bank_mode = false;
 913
 914         switch (device_id) {
 915         case 0x415: /* STM32L47/L48xx */
 916         case 0x461: /* STM32L49/L4Axx */
 917                 /* if flash size is max (1M) the device is always dual bank
 918                  * 0x415: has variants with 512K
 919                  * 0x461: has variants with 512 and 256
 920                  * for these variants:
 921                  *   if DUAL_BANK = 0 -> single bank
 922                  *   else -> dual bank without gap
 923                  * note: the page size is invariant
 924                  */
 925                 page_size_kb = 2;
 926                 num_pages = flash_size_kb / page_size_kb;
 927                 stm32l4_info->bank1_sectors = num_pages;
 928
 929                 /* check DUAL_BANK bit[21] if the flash is less than 1M */
 930                 if (flash_size_kb == 1024 || (options & BIT(21))) {
 931                         stm32l4_info->dual_bank_mode = true;
 932                         stm32l4_info->bank1_sectors = num_pages / 2;
 933                 }
 934                 break;
 935         case 0x435: /* STM32L43/L44xx */
 936         case 0x460: /* STM32G07/G08xx */
 937         case 0x462: /* STM32L45/L46xx */
 938         case 0x464: /* STM32L41/L42xx */
 939         case 0x466: /* STM32G03/G04xx */
 940         case 0x468: /* STM32G43/G44xx */
 941         case 0x497: /* STM32WLEx */
 942                 /* single bank flash */
 943                 page_size_kb = 2;
 944                 num_pages = flash_size_kb / page_size_kb;
 945                 stm32l4_info->bank1_sectors = num_pages;
 946                 break;
 947         case 0x469: /* STM32G47/G48xx */
 948                 /* STM32G47/8 can be single/dual bank:
 949                  *   if DUAL_BANK = 0 -> single bank
 950                  *   else -> dual bank WITH gap
 951                  */
 952                 page_size_kb = 4;
 953                 num_pages = flash_size_kb / page_size_kb;
 954                 stm32l4_info->bank1_sectors = num_pages;
 955                 if (options & BIT(22)) {
 956                         stm32l4_info->dual_bank_mode = true;
 957                         page_size_kb = 2;
 958                         num_pages = flash_size_kb / page_size_kb;
 959                         stm32l4_info->bank1_sectors = num_pages / 2;
 960
 961                         /* for devices with trimmed flash, there is a gap between both banks */
 962                         stm32l4_info->hole_sectors =
 963                                 (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
 964                 }
 965                 break;
 966         case 0x470: /* STM32L4R/L4Sxx */
 967         case 0x471: /* STM32L4P5/L4Q5x */
 968                 /* STM32L4R/S can be single/dual bank:
 969                  *   if size = 2M check DBANK bit(22)
 970                  *   if size = 1M check DB1M bit(21)
 971                  * STM32L4P/Q can be single/dual bank
 972                  *   if size = 1M check DBANK bit(22)
 973                  *   if size = 512K check DB512K bit(21)
 974                  */
 975                 page_size_kb = 8;
 976                 num_pages = flash_size_kb / page_size_kb;
 977                 stm32l4_info->bank1_sectors = num_pages;
 978                 const bool use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb;
 979                 if ((use_dbank_bit && (options & BIT(22))) ||
 980                         (!use_dbank_bit && (options & BIT(21)))) {
 981                         stm32l4_info->dual_bank_mode = true;
 982                         page_size_kb = 4;
 983                         num_pages = flash_size_kb / page_size_kb;
 984                         stm32l4_info->bank1_sectors = num_pages / 2;
 985                 }
 986                 break;
 987         case 0x495: /* STM32WB5x */
 988                 /* single bank flash */
 989                 page_size_kb = 4;
 990                 num_pages = flash_size_kb / page_size_kb;
 991                 stm32l4_info->bank1_sectors = num_pages;
 992                 break;
 993         default:
 994                 LOG_ERROR("unsupported device");
 995                 return ERROR_FAIL;
 996         }
 997
 998         LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
 999
1000         const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
1001
1002         if (gap_size_kb != 0) {
1003                 LOG_INFO("gap detected from 0x%08" PRIx32 " to 0x%08" PRIx32,
1004                         STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
1005                                 * page_size_kb * 1024,
1006                         STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
1007                                 * page_size_kb + gap_size_kb) * 1024 - 1);
1008         }
1009
1010         /* number of significant bits in WRPxxR differs per device,
1011          * always right adjusted, on some devices non-implemented
1012          * bits read as '0', on others as '1' ...
1013          * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
1014          */
1015
1016         /* use *max_flash_size* instead of actual size as the trimmed versions
1017          * certainly use the same number of bits
1018          * max_flash_size is always power of two, so max_pages too
1019          */
1020         uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
1021         assert((max_pages & (max_pages - 1)) == 0);
1022
1023         /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
1024         stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
1025         assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
1026         LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, stm32l4_info->wrpxxr_mask);
1027
1028         if (bank->sectors) {
1029                 free(bank->sectors);
1030                 bank->sectors = NULL;
1031         }
1032
1033         bank->size = (flash_size_kb + gap_size_kb) * 1024;
1034         bank->base = STM32_FLASH_BANK_BASE;
1035         bank->num_sectors = num_pages;
1036         bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
1037         if (bank->sectors == NULL) {
1038                 LOG_ERROR("failed to allocate bank sectors");
1039                 return ERROR_FAIL;
1040         }
1041
1042         for (int i = 0; i < bank->num_sectors; i++) {
1043                 bank->sectors[i].offset = i * page_size_kb * 1024;
1044                 /* in dual bank configuration, if there is a gap between banks
1045                  * we fix up the sector offset to consider this gap */
1046                 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
1047                         bank->sectors[i].offset += gap_size_kb * 1024;
1048                 bank->sectors[i].size = page_size_kb * 1024;
1049                 bank->sectors[i].is_erased = -1;
1050                 bank->sectors[i].is_protected = 1;
1051         }
1052
1053         stm32l4_info->probed = true;
1054         return ERROR_OK;
1055 }
1056
1057 static int stm32l4_auto_probe(struct flash_bank *bank)
1058 {
1059         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1060         if (stm32l4_info->probed)
1061                 return ERROR_OK;
1062
1063         return stm32l4_probe(bank);
1064 }
1065
1066 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
1067 {
1068         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1069         const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1070
1071         if (part_info) {
1072                 const char *rev_str = NULL;
1073                 uint16_t rev_id = stm32l4_info->idcode >> 16;
1074                 for (unsigned int i = 0; i < part_info->num_revs; i++) {
1075                         if (rev_id == part_info->revs[i].rev) {
1076                                 rev_str = part_info->revs[i].str;
1077
1078                                 if (rev_str != NULL) {
1079                                         snprintf(buf, buf_size, "%s - Rev: %s%s",
1080                                                 part_info->device_str, rev_str, stm32l4_info->probed ?
1081                                                         (stm32l4_info->dual_bank_mode ? " dual-bank" : " single-bank") : "");
1082                                         return ERROR_OK;
1083                                 }
1084                         }
1085                 }
1086
1087                 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)%s",
1088                         part_info->device_str, rev_id, stm32l4_info->probed ?
1089                                 (stm32l4_info->dual_bank_mode ? " dual-bank" : " single-bank") : "");
1090                 return ERROR_OK;
1091         } else {
1092                 snprintf(buf, buf_size, "Cannot identify target as an %s device", device_families);
1093                 return ERROR_FAIL;
1094         }
1095
1096         return ERROR_OK;
1097 }
1098
1099 static int stm32l4_mass_erase(struct flash_bank *bank)
1100 {
1101         int retval, retval2;
1102         struct target *target = bank->target;
1103         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1104
1105         uint32_t action = FLASH_MER1;
1106
1107         if (stm32l4_info->part_info->has_dual_bank)
1108                 action |= FLASH_MER2;
1109
1110         if (target->state != TARGET_HALTED) {
1111                 LOG_ERROR("Target not halted");
1112                 return ERROR_TARGET_NOT_HALTED;
1113         }
1114
1115         retval = stm32l4_unlock_reg(bank);
1116         if (retval != ERROR_OK)
1117                 goto err_lock;
1118
1119         /* mass erase flash memory */
1120         retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
1121         if (retval != ERROR_OK)
1122                 goto err_lock;
1123
1124         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action);
1125         if (retval != ERROR_OK)
1126                 goto err_lock;
1127
1128         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action | FLASH_STRT);
1129         if (retval != ERROR_OK)
1130                 goto err_lock;
1131
1132         retval = stm32l4_wait_status_busy(bank,  FLASH_ERASE_TIMEOUT);
1133
1134 err_lock:
1135         retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
1136
1137         if (retval != ERROR_OK)
1138                 return retval;
1139
1140         return retval2;
1141 }
1142
1143 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
1144 {
1145         if (CMD_ARGC < 1) {
1146                 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
1147                 return ERROR_COMMAND_SYNTAX_ERROR;
1148         }
1149
1150         struct flash_bank *bank;
1151         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1152         if (ERROR_OK != retval)
1153                 return retval;
1154
1155         retval = stm32l4_mass_erase(bank);
1156         if (retval == ERROR_OK) {
1157                 /* set all sectors as erased */
1158                 for (int i = 0; i < bank->num_sectors; i++)
1159                         bank->sectors[i].is_erased = 1;
1160
1161                 command_print(CMD, "stm32l4x mass erase complete");
1162         } else {
1163                 command_print(CMD, "stm32l4x mass erase failed");
1164         }
1165
1166         return retval;
1167 }
1168
1169 COMMAND_HANDLER(stm32l4_handle_option_read_command)
1170 {
1171         if (CMD_ARGC < 2) {
1172                 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
1173                 return ERROR_COMMAND_SYNTAX_ERROR;
1174         }
1175
1176         struct flash_bank *bank;
1177         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1178         if (ERROR_OK != retval)
1179                 return retval;
1180
1181         uint32_t reg_offset, reg_addr;
1182         uint32_t value = 0;
1183
1184         reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
1185         reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
1186
1187         retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
1188         if (ERROR_OK != retval)
1189                 return retval;
1190
1191         command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
1192
1193         return retval;
1194 }
1195
1196 COMMAND_HANDLER(stm32l4_handle_option_write_command)
1197 {
1198         if (CMD_ARGC < 3) {
1199                 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
1200                 return ERROR_COMMAND_SYNTAX_ERROR;
1201         }
1202
1203         struct flash_bank *bank;
1204         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1205         if (ERROR_OK != retval)
1206                 return retval;
1207
1208         uint32_t reg_offset;
1209         uint32_t value = 0;
1210         uint32_t mask = 0xFFFFFFFF;
1211
1212         reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
1213         value = strtoul(CMD_ARGV[2], NULL, 16);
1214         if (CMD_ARGC > 3)
1215                 mask = strtoul(CMD_ARGV[3], NULL, 16);
1216
1217         command_print(CMD, "%s Option written.\n"
1218                                 "INFO: a reset or power cycle is required "
1219                                 "for the new settings to take effect.", bank->driver->name);
1220
1221         retval = stm32l4_write_option(bank, reg_offset, value, mask);
1222         return retval;
1223 }
1224
1225 COMMAND_HANDLER(stm32l4_handle_option_load_command)
1226 {
1227         if (CMD_ARGC < 1)
1228                 return ERROR_COMMAND_SYNTAX_ERROR;
1229
1230         struct flash_bank *bank;
1231         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1232         if (ERROR_OK != retval)
1233                 return retval;
1234
1235         retval = stm32l4_unlock_reg(bank);
1236         if (ERROR_OK != retval)
1237                 return retval;
1238
1239         retval = stm32l4_unlock_option_reg(bank);
1240         if (ERROR_OK != retval)
1241                 return retval;
1242
1243         /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
1244          * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
1245          * "Note: If the read protection is set while the debugger is still
1246          * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
1247          */
1248         retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBL_LAUNCH);
1249
1250         command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
1251
1252         /* Need to re-probe after change */
1253         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1254         stm32l4_info->probed = false;
1255
1256         return retval;
1257 }
1258
1259 COMMAND_HANDLER(stm32l4_handle_lock_command)
1260 {
1261         struct target *target = NULL;
1262
1263         if (CMD_ARGC < 1)
1264                 return ERROR_COMMAND_SYNTAX_ERROR;
1265
1266         struct flash_bank *bank;
1267         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1268         if (ERROR_OK != retval)
1269                 return retval;
1270
1271         target = bank->target;
1272
1273         if (target->state != TARGET_HALTED) {
1274                 LOG_ERROR("Target not halted");
1275                 return ERROR_TARGET_NOT_HALTED;
1276         }
1277
1278         /* set readout protection level 1 by erasing the RDP option byte */
1279         if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
1280                 command_print(CMD, "%s failed to lock device", bank->driver->name);
1281                 return ERROR_OK;
1282         }
1283
1284         return ERROR_OK;
1285 }
1286
1287 COMMAND_HANDLER(stm32l4_handle_unlock_command)
1288 {
1289         struct target *target = NULL;
1290
1291         if (CMD_ARGC < 1)
1292                 return ERROR_COMMAND_SYNTAX_ERROR;
1293
1294         struct flash_bank *bank;
1295         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1296         if (ERROR_OK != retval)
1297                 return retval;
1298
1299         target = bank->target;
1300
1301         if (target->state != TARGET_HALTED) {
1302                 LOG_ERROR("Target not halted");
1303                 return ERROR_TARGET_NOT_HALTED;
1304         }
1305
1306         if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
1307                 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1308                 return ERROR_OK;
1309         }
1310
1311         return ERROR_OK;
1312 }
1313
1314 static const struct command_registration stm32l4_exec_command_handlers[] = {
1315         {
1316                 .name = "lock",
1317                 .handler = stm32l4_handle_lock_command,
1318                 .mode = COMMAND_EXEC,
1319                 .usage = "bank_id",
1320                 .help = "Lock entire flash device.",
1321         },
1322         {
1323                 .name = "unlock",
1324                 .handler = stm32l4_handle_unlock_command,
1325                 .mode = COMMAND_EXEC,
1326                 .usage = "bank_id",
1327                 .help = "Unlock entire protected flash device.",
1328         },
1329         {
1330                 .name = "mass_erase",
1331                 .handler = stm32l4_handle_mass_erase_command,
1332                 .mode = COMMAND_EXEC,
1333                 .usage = "bank_id",
1334                 .help = "Erase entire flash device.",
1335         },
1336         {
1337                 .name = "option_read",
1338                 .handler = stm32l4_handle_option_read_command,
1339                 .mode = COMMAND_EXEC,
1340                 .usage = "bank_id reg_offset",
1341                 .help = "Read & Display device option bytes.",
1342         },
1343         {
1344                 .name = "option_write",
1345                 .handler = stm32l4_handle_option_write_command,
1346                 .mode = COMMAND_EXEC,
1347                 .usage = "bank_id reg_offset value mask",
1348                 .help = "Write device option bit fields with provided value.",
1349         },
1350         {
1351                 .name = "option_load",
1352                 .handler = stm32l4_handle_option_load_command,
1353                 .mode = COMMAND_EXEC,
1354                 .usage = "bank_id",
1355                 .help = "Force re-load of device options (will cause device reset).",
1356         },
1357         COMMAND_REGISTRATION_DONE
1358 };
1359
1360 static const struct command_registration stm32l4_command_handlers[] = {
1361         {
1362                 .name = "stm32l4x",
1363                 .mode = COMMAND_ANY,
1364                 .help = "stm32l4x flash command group",
1365                 .usage = "",
1366                 .chain = stm32l4_exec_command_handlers,
1367         },
1368         COMMAND_REGISTRATION_DONE
1369 };
1370
1371 const struct flash_driver stm32l4x_flash = {
1372         .name = "stm32l4x",
1373         .commands = stm32l4_command_handlers,
1374         .flash_bank_command = stm32l4_flash_bank_command,
1375         .erase = stm32l4_erase,
1376         .protect = stm32l4_protect,
1377         .write = stm32l4_write,
1378         .read = default_flash_read,
1379         .probe = stm32l4_probe,
1380         .auto_probe = stm32l4_auto_probe,
1381         .erase_check = default_flash_blank_check,
1382         .protect_check = stm32l4_protect_check,
1383         .info = get_stm32l4_info,
1384         .free_driver_priv = default_flash_free_driver_priv,
1385 };