1 /***************************************************************************
2 * Copyright (C) 2017 by STMicroelectronics *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
22 #include <helper/binarybuffer.h>
23 #include <target/algorithm.h>
24 #include <target/armv7m.h>
27 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
28 #define FLASH_ERASE_TIMEOUT 10000
29 #define FLASH_WRITE_TIMEOUT 5
32 /* Same Flash registers for both banks, */
33 /* access depends on Flash Base address */
34 #define FLASH_ACR 0x00
35 #define FLASH_KEYR 0x04
36 #define FLASH_OPTKEYR 0x08
39 #define FLASH_CCR 0x14
40 #define FLASH_OPTCR 0x18
41 #define FLASH_OPTSR_CUR 0x1C
42 #define FLASH_OPTSR_PRG 0x20
43 #define FLASH_OPTCCR 0x24
44 #define FLASH_WPSN_CUR 0x38
45 #define FLASH_WPSN_PRG 0x3C
48 /* FLASH_CR register bits */
49 #define FLASH_LOCK (1 << 0)
50 #define FLASH_PG (1 << 1)
51 #define FLASH_SER (1 << 2)
52 #define FLASH_BER (1 << 3)
53 #define FLASH_PSIZE_8 (0 << 4)
54 #define FLASH_PSIZE_16 (1 << 4)
55 #define FLASH_PSIZE_32 (2 << 4)
56 #define FLASH_PSIZE_64 (3 << 4)
57 #define FLASH_FW (1 << 6)
58 #define FLASH_START (1 << 7)
60 /* FLASH_SR register bits */
61 #define FLASH_BSY (1 << 0) /* Operation in progress */
62 #define FLASH_QW (1 << 2) /* Operation queue in progress */
63 #define FLASH_WRPERR (1 << 17) /* Write protection error */
64 #define FLASH_PGSERR (1 << 18) /* Programming sequence error */
65 #define FLASH_STRBERR (1 << 19) /* Strobe error */
66 #define FLASH_INCERR (1 << 21) /* Inconsistency error */
67 #define FLASH_OPERR (1 << 22) /* Operation error */
68 #define FLASH_RDPERR (1 << 23) /* Read Protection error */
69 #define FLASH_RDSERR (1 << 24) /* Secure Protection error */
70 #define FLASH_SNECCERR (1 << 25) /* Single ECC error */
71 #define FLASH_DBECCERR (1 << 26) /* Double ECC error */
73 #define FLASH_ERROR (FLASH_WRPERR | FLASH_PGSERR | FLASH_STRBERR | FLASH_INCERR | FLASH_OPERR | \
74 FLASH_RDPERR | FLASH_RDSERR | FLASH_SNECCERR | FLASH_DBECCERR)
76 /* FLASH_OPTCR register bits */
77 #define OPT_LOCK (1 << 0)
78 #define OPT_START (1 << 1)
80 /* FLASH_OPTSR register bits */
81 #define OPT_BSY (1 << 0)
83 #define OPT_RDP_MASK (0xff << OPT_RDP_POS)
84 #define OPT_OPTCHANGEERR (1 << 30)
86 /* FLASH_OPTCCR register bits */
87 #define OPT_CLR_OPTCHANGEERR (1 << 30)
89 /* register unlock keys */
90 #define KEY1 0x45670123
91 #define KEY2 0xCDEF89AB
93 /* option register unlock key */
94 #define OPTKEY1 0x08192A3B
95 #define OPTKEY2 0x4C5D6E7F
97 #define DBGMCU_IDCODE_REGISTER 0x5C001000
98 #define FLASH_BANK0_ADDRESS 0x08000000
99 #define FLASH_BANK1_ADDRESS 0x08100000
100 #define FLASH_REG_BASE_B0 0x52002000
101 #define FLASH_REG_BASE_B1 0x52002100
103 struct stm32h7x_rev {
108 /* stm32h7x_part_info permits the store each device information and specificities.
109 * the default unit is byte unless the suffix '_kb' is used. */
111 struct stm32h7x_part_info {
113 const char *device_str;
114 const struct stm32h7x_rev *revs;
116 unsigned int page_size_kb;
117 unsigned int block_size; /* flash write word size in bytes */
118 uint16_t max_flash_size_kb;
120 uint16_t max_bank_size_kb; /* Used when has_dual_bank is true */
121 uint32_t fsize_addr; /* Location of FSIZE register */
122 uint32_t wps_group_size; /* write protection group sectors' count */
124 /* function to compute flash_cr register values */
125 uint32_t (*compute_flash_cr)(uint32_t cmd, int snb);
128 struct stm32h7x_flash_bank {
131 uint32_t user_bank_size;
132 uint32_t flash_regs_base; /* Address of flash reg controller */
133 const struct stm32h7x_part_info *part_info;
136 enum stm32h7x_opt_rdp {
142 static const struct stm32h7x_rev stm32_450_revs[] = {
143 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X" }, { 0x2003, "V" },
146 static const struct stm32h7x_rev stm32_480_revs[] = {
150 static uint32_t stm32x_compute_flash_cr_450(uint32_t cmd, int snb)
152 return cmd | (snb << 8);
155 static uint32_t stm32x_compute_flash_cr_480(uint32_t cmd, int snb)
157 /* save FW and START bits, to be right shifted by 2 bits later */
158 const uint32_t tmp = cmd & (FLASH_FW | FLASH_START);
160 /* mask parallelism (ignored), FW and START bits */
161 cmd &= ~(FLASH_PSIZE_64 | FLASH_FW | FLASH_START);
163 return cmd | (tmp >> 2) | (snb << 6);
166 static const struct stm32h7x_part_info stm32h7x_parts[] = {
169 .revs = stm32_450_revs,
170 .num_revs = ARRAY_SIZE(stm32_450_revs),
171 .device_str = "STM32H74x/75x",
174 .max_flash_size_kb = 2048,
175 .max_bank_size_kb = 1024,
176 .has_dual_bank = true,
177 .fsize_addr = 0x1FF1E880,
180 .compute_flash_cr = stm32x_compute_flash_cr_450,
184 .revs = stm32_480_revs,
185 .num_revs = ARRAY_SIZE(stm32_480_revs),
186 .device_str = "STM32H7Ax/7Bx",
189 .max_flash_size_kb = 2048,
190 .max_bank_size_kb = 1024,
191 .has_dual_bank = true,
192 .fsize_addr = 0x08FFF80C,
194 .wps_mask = 0xFFFFFFFF,
195 .compute_flash_cr = stm32x_compute_flash_cr_480,
199 /* flash bank stm32x <base> <size> 0 0 <target#> */
201 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
203 struct stm32h7x_flash_bank *stm32x_info;
206 return ERROR_COMMAND_SYNTAX_ERROR;
208 stm32x_info = malloc(sizeof(struct stm32h7x_flash_bank));
209 bank->driver_priv = stm32x_info;
211 stm32x_info->probed = false;
212 stm32x_info->user_bank_size = bank->size;
217 static inline uint32_t stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
219 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
220 return reg_offset + stm32x_info->flash_regs_base;
223 static inline int stm32x_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
225 uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
226 int retval = target_read_u32(bank->target, reg_addr, value);
228 if (retval != ERROR_OK)
229 LOG_ERROR("error while reading from address 0x%" PRIx32, reg_addr);
234 static inline int stm32x_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
236 uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
237 int retval = target_write_u32(bank->target, reg_addr, value);
239 if (retval != ERROR_OK)
240 LOG_ERROR("error while writing to address 0x%" PRIx32, reg_addr);
245 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
247 return stm32x_read_flash_reg(bank, FLASH_SR, status);
250 static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
255 /* wait for flash operations completion */
257 retval = stm32x_get_flash_status(bank, &status);
258 if (retval != ERROR_OK)
261 if ((status & FLASH_QW) == 0)
264 if (timeout-- <= 0) {
265 LOG_ERROR("wait_flash_op_queue, time out expired, status: 0x%" PRIx32 "", status);
271 if (status & FLASH_WRPERR) {
272 LOG_ERROR("wait_flash_op_queue, WRPERR detected");
276 /* Clear error + EOP flags but report errors */
277 if (status & FLASH_ERROR) {
278 if (retval == ERROR_OK)
280 /* If this operation fails, we ignore it and report the original retval */
281 stm32x_write_flash_reg(bank, FLASH_CCR, status);
286 static int stm32x_unlock_reg(struct flash_bank *bank)
290 /* first check if not already unlocked
291 * otherwise writing on FLASH_KEYR will fail
293 int retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
294 if (retval != ERROR_OK)
297 if ((ctrl & FLASH_LOCK) == 0)
300 /* unlock flash registers for bank */
301 retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY1);
302 if (retval != ERROR_OK)
305 retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY2);
306 if (retval != ERROR_OK)
309 retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
310 if (retval != ERROR_OK)
313 if (ctrl & FLASH_LOCK) {
314 LOG_ERROR("flash not unlocked STM32_FLASH_CRx: %" PRIx32, ctrl);
315 return ERROR_TARGET_FAILURE;
320 static int stm32x_unlock_option_reg(struct flash_bank *bank)
324 int retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
325 if (retval != ERROR_OK)
328 if ((ctrl & OPT_LOCK) == 0)
331 /* unlock option registers */
332 retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY1);
333 if (retval != ERROR_OK)
336 retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY2);
337 if (retval != ERROR_OK)
340 retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
341 if (retval != ERROR_OK)
344 if (ctrl & OPT_LOCK) {
345 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
346 return ERROR_TARGET_FAILURE;
352 static inline int stm32x_lock_reg(struct flash_bank *bank)
354 return stm32x_write_flash_reg(bank, FLASH_CR, FLASH_LOCK);
357 static inline int stm32x_lock_option_reg(struct flash_bank *bank)
359 return stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_LOCK);
362 static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
366 /* unlock option bytes for modification */
367 retval = stm32x_unlock_option_reg(bank);
368 if (retval != ERROR_OK)
369 goto flash_options_lock;
371 /* write option bytes */
372 retval = stm32x_write_flash_reg(bank, reg_offset, value);
373 if (retval != ERROR_OK)
374 goto flash_options_lock;
376 /* Remove OPT error flag before programming */
377 retval = stm32x_write_flash_reg(bank, FLASH_OPTCCR, OPT_CLR_OPTCHANGEERR);
378 if (retval != ERROR_OK)
379 goto flash_options_lock;
381 /* start programming cycle */
382 retval = stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_START);
383 if (retval != ERROR_OK)
384 goto flash_options_lock;
386 /* wait for completion */
387 int timeout = FLASH_ERASE_TIMEOUT;
390 retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_CUR, &status);
391 if (retval != ERROR_OK) {
392 LOG_ERROR("stm32x_options_program: failed to read FLASH_OPTSR_CUR");
393 goto flash_options_lock;
395 if ((status & OPT_BSY) == 0)
398 if (timeout-- <= 0) {
399 LOG_ERROR("waiting for OBL launch, time out expired, OPTSR: 0x%" PRIx32 "", status);
401 goto flash_options_lock;
406 /* check for failure */
407 if (status & OPT_OPTCHANGEERR) {
408 LOG_ERROR("error changing option bytes (OPTCHANGEERR=1)");
409 retval = ERROR_FLASH_OPERATION_FAILED;
413 retval2 = stm32x_lock_option_reg(bank);
414 if (retval2 != ERROR_OK)
415 LOG_ERROR("error during the lock of flash options");
417 return (retval == ERROR_OK) ? retval2 : retval;
420 static int stm32x_modify_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
424 int retval = stm32x_read_flash_reg(bank, reg_offset, &data);
425 if (retval != ERROR_OK)
428 data = (data & ~mask) | (value & mask);
430 return stm32x_write_option(bank, reg_offset, data);
433 static int stm32x_protect_check(struct flash_bank *bank)
437 /* read 'write protection' settings */
438 int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
439 if (retval != ERROR_OK) {
440 LOG_DEBUG("unable to read WPSN_CUR register");
444 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
445 bank->prot_blocks[i].is_protected = protection & (1 << i) ? 0 : 1;
450 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
453 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
456 assert(first < bank->num_sectors);
457 assert(last < bank->num_sectors);
459 if (bank->target->state != TARGET_HALTED)
460 return ERROR_TARGET_NOT_HALTED;
462 retval = stm32x_unlock_reg(bank);
463 if (retval != ERROR_OK)
468 To erase a sector, follow the procedure below:
469 1. Check that no Flash memory operation is ongoing by checking the QW bit in the
471 2. Set the SER bit and select the sector
472 you wish to erase (SNB) in the FLASH_CR register
473 3. Set the STRT bit in the FLASH_CR register
474 4. Wait for flash operations completion
476 for (unsigned int i = first; i <= last; i++) {
477 LOG_DEBUG("erase sector %u", i);
478 retval = stm32x_write_flash_reg(bank, FLASH_CR,
479 stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64, i));
480 if (retval != ERROR_OK) {
481 LOG_ERROR("Error erase sector %u", i);
484 retval = stm32x_write_flash_reg(bank, FLASH_CR,
485 stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64 | FLASH_START, i));
486 if (retval != ERROR_OK) {
487 LOG_ERROR("Error erase sector %u", i);
490 retval = stm32x_wait_flash_op_queue(bank, FLASH_ERASE_TIMEOUT);
492 if (retval != ERROR_OK) {
493 LOG_ERROR("erase time-out or operation error sector %u", i);
496 bank->sectors[i].is_erased = 1;
500 retval2 = stm32x_lock_reg(bank);
501 if (retval2 != ERROR_OK)
502 LOG_ERROR("error during the lock of flash");
504 return (retval == ERROR_OK) ? retval2 : retval;
507 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
510 struct target *target = bank->target;
513 if (target->state != TARGET_HALTED) {
514 LOG_ERROR("Target not halted");
515 return ERROR_TARGET_NOT_HALTED;
518 /* read 'write protection' settings */
519 int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
520 if (retval != ERROR_OK) {
521 LOG_DEBUG("unable to read WPSN_CUR register");
525 for (unsigned int i = first; i <= last; i++) {
527 protection &= ~(1 << i);
529 protection |= (1 << i);
532 /* apply WRPSN mask */
535 LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%" PRIx32, protection);
537 /* apply new option value */
538 return stm32x_write_option(bank, FLASH_WPSN_PRG, protection);
541 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
542 uint32_t offset, uint32_t count)
544 struct target *target = bank->target;
545 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
547 * If the size of the data part of the buffer is not a multiple of .block_size, we get
548 * "corrupted fifo read" pointer in target_run_flash_async_algorithm()
550 uint32_t data_size = 512 * stm32x_info->part_info->block_size;
551 uint32_t buffer_size = 8 + data_size;
552 struct working_area *write_algorithm;
553 struct working_area *source;
554 uint32_t address = bank->base + offset;
555 struct reg_param reg_params[6];
556 struct armv7m_algorithm armv7m_info;
557 int retval = ERROR_OK;
559 static const uint8_t stm32x_flash_write_code[] = {
560 #include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
563 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
564 &write_algorithm) != ERROR_OK) {
565 LOG_WARNING("no working area available, can't do block memory writes");
566 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
569 retval = target_write_buffer(target, write_algorithm->address,
570 sizeof(stm32x_flash_write_code),
571 stm32x_flash_write_code);
572 if (retval != ERROR_OK) {
573 target_free_working_area(target, write_algorithm);
578 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
580 buffer_size = 8 + data_size;
581 if (data_size <= 256) {
582 /* we already allocated the writing code, but failed to get a
583 * buffer, free the algorithm */
584 target_free_working_area(target, write_algorithm);
586 LOG_WARNING("no large enough working area available, can't do block memory writes");
587 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
591 LOG_DEBUG("target_alloc_working_area_try : buffer_size -> 0x%" PRIx32, buffer_size);
593 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
594 armv7m_info.core_mode = ARM_MODE_THREAD;
596 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
597 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
598 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
599 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count of words (word size = .block_size (bytes) */
600 init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* word size in bytes */
601 init_reg_param(®_params[5], "r5", 32, PARAM_OUT); /* flash reg base */
603 buf_set_u32(reg_params[0].value, 0, 32, source->address);
604 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
605 buf_set_u32(reg_params[2].value, 0, 32, address);
606 buf_set_u32(reg_params[3].value, 0, 32, count);
607 buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->part_info->block_size);
608 buf_set_u32(reg_params[5].value, 0, 32, stm32x_info->flash_regs_base);
610 retval = target_run_flash_async_algorithm(target,
613 stm32x_info->part_info->block_size,
615 ARRAY_SIZE(reg_params), reg_params,
616 source->address, source->size,
617 write_algorithm->address, 0,
620 if (retval == ERROR_FLASH_OPERATION_FAILED) {
621 LOG_ERROR("error executing stm32h7x flash write algorithm");
623 uint32_t flash_sr = buf_get_u32(reg_params[0].value, 0, 32);
625 if (flash_sr & FLASH_WRPERR)
626 LOG_ERROR("flash memory write protected");
628 if ((flash_sr & FLASH_ERROR) != 0) {
629 LOG_ERROR("flash write failed, FLASH_SR = %08" PRIx32, flash_sr);
630 /* Clear error + EOP flags but report errors */
631 stm32x_write_flash_reg(bank, FLASH_CCR, flash_sr);
636 target_free_working_area(target, source);
637 target_free_working_area(target, write_algorithm);
639 destroy_reg_param(®_params[0]);
640 destroy_reg_param(®_params[1]);
641 destroy_reg_param(®_params[2]);
642 destroy_reg_param(®_params[3]);
643 destroy_reg_param(®_params[4]);
644 destroy_reg_param(®_params[5]);
648 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
649 uint32_t offset, uint32_t count)
651 struct target *target = bank->target;
652 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
653 uint32_t address = bank->base + offset;
656 if (bank->target->state != TARGET_HALTED) {
657 LOG_ERROR("Target not halted");
658 return ERROR_TARGET_NOT_HALTED;
661 /* should be enforced via bank->write_start_alignment */
662 assert(!(offset % stm32x_info->part_info->block_size));
664 /* should be enforced via bank->write_end_alignment */
665 assert(!(count % stm32x_info->part_info->block_size));
667 retval = stm32x_unlock_reg(bank);
668 if (retval != ERROR_OK)
671 uint32_t blocks_remaining = count / stm32x_info->part_info->block_size;
673 /* multiple words (n * .block_size) to be programmed in block */
674 if (blocks_remaining) {
675 retval = stm32x_write_block(bank, buffer, offset, blocks_remaining);
676 if (retval != ERROR_OK) {
677 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
678 /* if block write failed (no sufficient working area),
679 * we use normal (slow) dword accesses */
680 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
683 buffer += blocks_remaining * stm32x_info->part_info->block_size;
684 address += blocks_remaining * stm32x_info->part_info->block_size;
685 blocks_remaining = 0;
687 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
693 The Flash memory programming sequence is as follows:
694 1. Check that no main Flash memory operation is ongoing by checking the QW bit in the
696 2. Set the PG bit in the FLASH_CR register
697 3. 8 x Word access (or Force Write FW)
698 4. Wait for flash operations completion
700 while (blocks_remaining > 0) {
701 retval = stm32x_write_flash_reg(bank, FLASH_CR,
702 stm32x_info->part_info->compute_flash_cr(FLASH_PG | FLASH_PSIZE_64, 0));
703 if (retval != ERROR_OK)
706 retval = target_write_buffer(target, address, stm32x_info->part_info->block_size, buffer);
707 if (retval != ERROR_OK)
710 retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
711 if (retval != ERROR_OK)
714 buffer += stm32x_info->part_info->block_size;
715 address += stm32x_info->part_info->block_size;
720 retval2 = stm32x_lock_reg(bank);
721 if (retval2 != ERROR_OK)
722 LOG_ERROR("error during the lock of flash");
724 return (retval == ERROR_OK) ? retval2 : retval;
727 static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
729 /* read stm32 device id register */
730 int retval = target_read_u32(bank->target, DBGMCU_IDCODE_REGISTER, id);
731 if (retval != ERROR_OK)
736 static int stm32x_probe(struct flash_bank *bank)
738 struct target *target = bank->target;
739 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
740 uint16_t flash_size_in_kb;
743 stm32x_info->probed = false;
744 stm32x_info->part_info = NULL;
746 int retval = stm32x_read_id_code(bank, &stm32x_info->idcode);
747 if (retval != ERROR_OK)
750 LOG_DEBUG("device id = 0x%08" PRIx32 "", stm32x_info->idcode);
752 device_id = stm32x_info->idcode & 0xfff;
754 for (unsigned int n = 0; n < ARRAY_SIZE(stm32h7x_parts); n++) {
755 if (device_id == stm32h7x_parts[n].id)
756 stm32x_info->part_info = &stm32h7x_parts[n];
758 if (!stm32x_info->part_info) {
759 LOG_WARNING("Cannot identify target as a STM32H7xx family.");
762 LOG_INFO("Device: %s", stm32x_info->part_info->device_str);
765 /* update the address of controller */
766 if (bank->base == FLASH_BANK0_ADDRESS)
767 stm32x_info->flash_regs_base = FLASH_REG_BASE_B0;
768 else if (bank->base == FLASH_BANK1_ADDRESS)
769 stm32x_info->flash_regs_base = FLASH_REG_BASE_B1;
771 LOG_WARNING("Flash register base not defined for bank %u", bank->bank_number);
774 LOG_DEBUG("flash_regs_base: 0x%" PRIx32, stm32x_info->flash_regs_base);
776 /* get flash size from target */
777 retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb);
778 if (retval != ERROR_OK) {
779 /* read error when device has invalid value, set max flash size */
780 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
782 LOG_INFO("flash size probed value %d", flash_size_in_kb);
787 /* setup bank size */
788 const uint32_t bank1_base = FLASH_BANK0_ADDRESS;
789 const uint32_t bank2_base = bank1_base + stm32x_info->part_info->max_bank_size_kb * 1024;
790 bool has_dual_bank = stm32x_info->part_info->has_dual_bank;
795 /* For STM32H74x/75x and STM32H7Ax/Bx
796 * - STM32H7xxxI devices contains dual bank, 1 Mbyte each
797 * - STM32H7xxxG devices contains dual bank, 512 Kbyte each
798 * - STM32H7xxxB devices contains single bank, 128 Kbyte
799 * - the second bank starts always from 0x08100000
801 if (flash_size_in_kb == 128)
802 has_dual_bank = false;
804 /* flash size is 2M or 1M */
805 flash_size_in_kb /= 2;
808 LOG_ERROR("unsupported device");
813 LOG_INFO("STM32H7 flash has dual banks");
814 if (bank->base != bank1_base && bank->base != bank2_base) {
815 LOG_ERROR("STM32H7 flash bank base address config is incorrect. "
816 TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
817 bank->base, bank1_base, bank2_base);
821 LOG_INFO("STM32H7 flash has a single bank");
822 if (bank->base == bank2_base) {
823 LOG_ERROR("this device has a single bank only");
825 } else if (bank->base != bank1_base) {
826 LOG_ERROR("STM32H7 flash bank base address config is incorrect. "
827 TARGET_ADDR_FMT " but should be 0x%" PRIx32,
828 bank->base, bank1_base);
833 LOG_INFO("Bank (%u) size is %d kb, base address is 0x%" PRIx32,
834 bank->bank_number, flash_size_in_kb, (uint32_t) bank->base);
836 /* if the user sets the size manually then ignore the probed value
837 * this allows us to work around devices that have an invalid flash size register value */
838 if (stm32x_info->user_bank_size) {
839 LOG_INFO("ignoring flash probed value, using configured bank size");
840 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
841 } else if (flash_size_in_kb == 0xffff) {
843 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
846 /* did we assign flash size? */
847 assert(flash_size_in_kb != 0xffff);
848 bank->size = flash_size_in_kb * 1024;
849 bank->write_start_alignment = stm32x_info->part_info->block_size;
850 bank->write_end_alignment = stm32x_info->part_info->block_size;
853 bank->num_sectors = flash_size_in_kb / stm32x_info->part_info->page_size_kb;
854 assert(bank->num_sectors > 0);
859 bank->sectors = alloc_block_array(0, stm32x_info->part_info->page_size_kb * 1024,
862 if (bank->sectors == NULL) {
863 LOG_ERROR("failed to allocate bank sectors");
867 /* setup protection blocks */
868 const uint32_t wpsn = stm32x_info->part_info->wps_group_size;
869 assert(bank->num_sectors % wpsn == 0);
871 bank->num_prot_blocks = bank->num_sectors / wpsn;
872 assert(bank->num_prot_blocks > 0);
874 if (bank->prot_blocks)
875 free(bank->prot_blocks);
877 bank->prot_blocks = alloc_block_array(0, stm32x_info->part_info->page_size_kb * wpsn * 1024,
878 bank->num_prot_blocks);
880 if (bank->prot_blocks == NULL) {
881 LOG_ERROR("failed to allocate bank prot_block");
885 stm32x_info->probed = 1;
889 static int stm32x_auto_probe(struct flash_bank *bank)
891 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
893 if (stm32x_info->probed)
896 return stm32x_probe(bank);
899 /* This method must return a string displaying information about the bank */
900 static int stm32x_get_info(struct flash_bank *bank, char *buf, int buf_size)
902 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
903 const struct stm32h7x_part_info *info = stm32x_info->part_info;
905 if (!stm32x_info->probed) {
906 int retval = stm32x_probe(bank);
907 if (retval != ERROR_OK) {
908 snprintf(buf, buf_size, "Unable to find bank information.");
914 const char *rev_str = NULL;
915 uint16_t rev_id = stm32x_info->idcode >> 16;
917 for (unsigned int i = 0; i < info->num_revs; i++)
918 if (rev_id == info->revs[i].rev)
919 rev_str = info->revs[i].str;
921 if (rev_str != NULL) {
922 snprintf(buf, buf_size, "%s - Rev: %s",
923 stm32x_info->part_info->device_str, rev_str);
925 snprintf(buf, buf_size,
926 "%s - Rev: unknown (0x%04x)",
927 stm32x_info->part_info->device_str, rev_id);
930 snprintf(buf, buf_size, "Cannot identify target as a STM32H7x");
936 static int stm32x_set_rdp(struct flash_bank *bank, enum stm32h7x_opt_rdp new_rdp)
938 struct target *target = bank->target;
939 uint32_t optsr, cur_rdp;
942 if (target->state != TARGET_HALTED) {
943 LOG_ERROR("Target not halted");
944 return ERROR_TARGET_NOT_HALTED;
947 retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_PRG, &optsr);
949 if (retval != ERROR_OK) {
950 LOG_DEBUG("unable to read FLASH_OPTSR_PRG register");
954 /* get current RDP, and check if there is a change */
955 cur_rdp = (optsr & OPT_RDP_MASK) >> OPT_RDP_POS;
956 if (new_rdp == cur_rdp) {
957 LOG_INFO("the requested RDP value is already programmed");
963 LOG_WARNING("unlocking the entire flash device");
966 LOG_WARNING("locking the entire flash device");
969 LOG_WARNING("locking the entire flash device, irreversible");
974 optsr = (optsr & ~OPT_RDP_MASK) | (new_rdp << OPT_RDP_POS);
976 /* apply new option value */
977 return stm32x_write_option(bank, FLASH_OPTSR_PRG, optsr);
980 COMMAND_HANDLER(stm32x_handle_lock_command)
983 return ERROR_COMMAND_SYNTAX_ERROR;
985 struct flash_bank *bank;
986 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
987 if (ERROR_OK != retval)
990 retval = stm32x_set_rdp(bank, OPT_RDP_L1);
992 if (retval != ERROR_OK)
993 command_print(CMD, "%s failed to lock device", bank->driver->name);
995 command_print(CMD, "%s locked", bank->driver->name);
1000 COMMAND_HANDLER(stm32x_handle_unlock_command)
1003 return ERROR_COMMAND_SYNTAX_ERROR;
1005 struct flash_bank *bank;
1006 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1007 if (ERROR_OK != retval)
1010 retval = stm32x_set_rdp(bank, OPT_RDP_L0);
1012 if (retval != ERROR_OK)
1013 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1015 command_print(CMD, "%s unlocked", bank->driver->name);
1020 static int stm32x_mass_erase(struct flash_bank *bank)
1022 int retval, retval2;
1023 struct target *target = bank->target;
1024 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
1026 if (target->state != TARGET_HALTED) {
1027 LOG_ERROR("Target not halted");
1028 return ERROR_TARGET_NOT_HALTED;
1031 retval = stm32x_unlock_reg(bank);
1032 if (retval != ERROR_OK)
1035 /* mass erase flash memory bank */
1036 retval = stm32x_write_flash_reg(bank, FLASH_CR,
1037 stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64, 0));
1038 if (retval != ERROR_OK)
1041 retval = stm32x_write_flash_reg(bank, FLASH_CR,
1042 stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64 | FLASH_START, 0));
1043 if (retval != ERROR_OK)
1046 retval = stm32x_wait_flash_op_queue(bank, 30000);
1047 if (retval != ERROR_OK)
1051 retval2 = stm32x_lock_reg(bank);
1052 if (retval2 != ERROR_OK)
1053 LOG_ERROR("error during the lock of flash");
1055 return (retval == ERROR_OK) ? retval2 : retval;
1058 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1061 command_print(CMD, "stm32h7x mass_erase <bank>");
1062 return ERROR_COMMAND_SYNTAX_ERROR;
1065 struct flash_bank *bank;
1066 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1067 if (ERROR_OK != retval)
1070 retval = stm32x_mass_erase(bank);
1071 if (retval == ERROR_OK) {
1072 /* set all sectors as erased */
1073 for (unsigned int i = 0; i < bank->num_sectors; i++)
1074 bank->sectors[i].is_erased = 1;
1076 command_print(CMD, "stm32h7x mass erase complete");
1078 command_print(CMD, "stm32h7x mass erase failed");
1084 COMMAND_HANDLER(stm32x_handle_option_read_command)
1087 command_print(CMD, "stm32h7x option_read <bank> <option_reg offset>");
1088 return ERROR_COMMAND_SYNTAX_ERROR;
1091 struct flash_bank *bank;
1092 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1093 if (ERROR_OK != retval)
1096 uint32_t reg_offset, value;
1098 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1099 retval = stm32x_read_flash_reg(bank, reg_offset, &value);
1100 if (ERROR_OK != retval)
1103 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "",
1104 stm32x_get_flash_reg(bank, reg_offset), value);
1109 COMMAND_HANDLER(stm32x_handle_option_write_command)
1112 command_print(CMD, "stm32h7x option_write <bank> <option_reg offset> <value> [mask]");
1113 return ERROR_COMMAND_SYNTAX_ERROR;
1116 struct flash_bank *bank;
1117 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1118 if (ERROR_OK != retval)
1121 uint32_t reg_offset, value, mask = 0xffffffff;
1123 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1124 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1126 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
1128 return stm32x_modify_option(bank, reg_offset, value, mask);
1131 static const struct command_registration stm32x_exec_command_handlers[] = {
1134 .handler = stm32x_handle_lock_command,
1135 .mode = COMMAND_EXEC,
1137 .help = "Lock entire flash device.",
1141 .handler = stm32x_handle_unlock_command,
1142 .mode = COMMAND_EXEC,
1144 .help = "Unlock entire protected flash device.",
1147 .name = "mass_erase",
1148 .handler = stm32x_handle_mass_erase_command,
1149 .mode = COMMAND_EXEC,
1151 .help = "Erase entire flash device.",
1154 .name = "option_read",
1155 .handler = stm32x_handle_option_read_command,
1156 .mode = COMMAND_EXEC,
1157 .usage = "bank_id reg_offset",
1158 .help = "Read and display device option bytes.",
1161 .name = "option_write",
1162 .handler = stm32x_handle_option_write_command,
1163 .mode = COMMAND_EXEC,
1164 .usage = "bank_id reg_offset value [mask]",
1165 .help = "Write device option bit fields with provided value.",
1167 COMMAND_REGISTRATION_DONE
1170 static const struct command_registration stm32x_command_handlers[] = {
1173 .mode = COMMAND_ANY,
1174 .help = "stm32h7x flash command group",
1176 .chain = stm32x_exec_command_handlers,
1178 COMMAND_REGISTRATION_DONE
1181 const struct flash_driver stm32h7x_flash = {
1183 .commands = stm32x_command_handlers,
1184 .flash_bank_command = stm32x_flash_bank_command,
1185 .erase = stm32x_erase,
1186 .protect = stm32x_protect,
1187 .write = stm32x_write,
1188 .read = default_flash_read,
1189 .probe = stm32x_probe,
1190 .auto_probe = stm32x_auto_probe,
1191 .erase_check = default_flash_blank_check,
1192 .protect_check = stm32x_protect_check,
1193 .info = stm32x_get_info,
1194 .free_driver_priv = default_flash_free_driver_priv,