1 /***************************************************************************
2 * Copyright (C) 2017 by STMicroelectronics *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
22 #include <helper/binarybuffer.h>
23 #include <target/algorithm.h>
24 #include <target/armv7m.h>
27 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
28 #define FLASH_ERASE_TIMEOUT 10000
29 #define FLASH_WRITE_TIMEOUT 5
32 /* Same Flash registers for both banks, */
33 /* access depends on Flash Base address */
34 #define FLASH_ACR 0x00
35 #define FLASH_KEYR 0x04
36 #define FLASH_OPTKEYR 0x08
39 #define FLASH_CCR 0x14
40 #define FLASH_OPTCR 0x18
41 #define FLASH_OPTSR_CUR 0x1C
42 #define FLASH_OPTSR_PRG 0x20
43 #define FLASH_OPTCCR 0x24
44 #define FLASH_WPSN_CUR 0x38
45 #define FLASH_WPSN_PRG 0x3C
48 /* FLASH_CR register bits */
49 #define FLASH_LOCK (1 << 0)
50 #define FLASH_PG (1 << 1)
51 #define FLASH_SER (1 << 2)
52 #define FLASH_BER (1 << 3)
53 #define FLASH_PSIZE_8 (0 << 4)
54 #define FLASH_PSIZE_16 (1 << 4)
55 #define FLASH_PSIZE_32 (2 << 4)
56 #define FLASH_PSIZE_64 (3 << 4)
57 #define FLASH_FW (1 << 6)
58 #define FLASH_START (1 << 7)
60 #define FLASH_SNB(a) ((a) << 8)
62 /* FLASH_SR register bits */
63 #define FLASH_BSY (1 << 0) /* Operation in progress */
64 #define FLASH_QW (1 << 2) /* Operation queue in progress */
65 #define FLASH_WRPERR (1 << 17) /* Write protection error */
66 #define FLASH_PGSERR (1 << 18) /* Programming sequence error */
67 #define FLASH_STRBERR (1 << 19) /* Strobe error */
68 #define FLASH_INCERR (1 << 21) /* Inconsistency error */
69 #define FLASH_OPERR (1 << 22) /* Operation error */
70 #define FLASH_RDPERR (1 << 23) /* Read Protection error */
71 #define FLASH_RDSERR (1 << 24) /* Secure Protection error */
72 #define FLASH_SNECCERR (1 << 25) /* Single ECC error */
73 #define FLASH_DBECCERR (1 << 26) /* Double ECC error */
75 #define FLASH_ERROR (FLASH_WRPERR | FLASH_PGSERR | FLASH_STRBERR | FLASH_INCERR | FLASH_OPERR | \
76 FLASH_RDPERR | FLASH_RDSERR | FLASH_SNECCERR | FLASH_DBECCERR)
78 /* FLASH_OPTCR register bits */
79 #define OPT_LOCK (1 << 0)
80 #define OPT_START (1 << 1)
82 /* FLASH_OPTSR register bits */
83 #define OPT_BSY (1 << 0)
85 #define OPT_RDP_MASK (0xff << OPT_RDP_POS)
86 #define OPT_OPTCHANGEERR (1 << 30)
88 /* FLASH_OPTCCR register bits */
89 #define OPT_CLR_OPTCHANGEERR (1 << 30)
91 /* register unlock keys */
92 #define KEY1 0x45670123
93 #define KEY2 0xCDEF89AB
95 /* option register unlock key */
96 #define OPTKEY1 0x08192A3B
97 #define OPTKEY2 0x4C5D6E7F
99 #define DBGMCU_IDCODE_REGISTER 0x5C001000
100 #define FLASH_BANK0_ADDRESS 0x08000000
101 #define FLASH_BANK1_ADDRESS 0x08100000
102 #define FLASH_REG_BASE_B0 0x52002000
103 #define FLASH_REG_BASE_B1 0x52002100
104 #define FLASH_SIZE_ADDRESS 0x1FF1E880
105 #define FLASH_BLOCK_SIZE 32
107 struct stm32h7x_rev {
112 struct stm32h7x_part_info {
114 const char *device_str;
115 const struct stm32h7x_rev *revs;
117 unsigned int page_size;
118 uint16_t max_flash_size_kb;
119 uint8_t has_dual_bank;
120 uint16_t first_bank_size_kb; /* Used when has_dual_bank is true */
121 uint32_t flash_regs_base; /* Flash controller registers location */
122 uint32_t fsize_addr; /* Location of FSIZE register */
125 struct stm32h7x_flash_bank {
128 uint32_t user_bank_size;
129 uint32_t flash_regs_base; /* Address of flash reg controller */
130 const struct stm32h7x_part_info *part_info;
133 enum stm32h7x_opt_rdp {
139 static const struct stm32h7x_rev stm32_450_revs[] = {
140 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X" }, { 0x2003, "V" },
143 static const struct stm32h7x_part_info stm32h7x_parts[] = {
146 .revs = stm32_450_revs,
147 .num_revs = ARRAY_SIZE(stm32_450_revs),
148 .device_str = "STM32H74x/75x",
149 .page_size = 128, /* 128 KB */
150 .max_flash_size_kb = 2048,
151 .first_bank_size_kb = 1024,
153 .flash_regs_base = FLASH_REG_BASE_B0,
154 .fsize_addr = FLASH_SIZE_ADDRESS,
158 /* flash bank stm32x <base> <size> 0 0 <target#> */
160 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
162 struct stm32h7x_flash_bank *stm32x_info;
165 return ERROR_COMMAND_SYNTAX_ERROR;
167 stm32x_info = malloc(sizeof(struct stm32h7x_flash_bank));
168 bank->driver_priv = stm32x_info;
170 stm32x_info->probed = 0;
171 stm32x_info->user_bank_size = bank->size;
173 bank->write_start_alignment = FLASH_BLOCK_SIZE;
174 bank->write_end_alignment = FLASH_BLOCK_SIZE;
179 static inline uint32_t stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
181 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
182 return reg_offset + stm32x_info->flash_regs_base;
185 static inline int stm32x_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
187 uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
188 int retval = target_read_u32(bank->target, reg_addr, value);
190 if (retval != ERROR_OK)
191 LOG_ERROR("error while reading from address 0x%" PRIx32, reg_addr);
196 static inline int stm32x_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
198 uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
199 int retval = target_write_u32(bank->target, reg_addr, value);
201 if (retval != ERROR_OK)
202 LOG_ERROR("error while writing to address 0x%" PRIx32, reg_addr);
207 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
209 return stm32x_read_flash_reg(bank, FLASH_SR, status);
212 static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
217 /* wait for flash operations completion */
219 retval = stm32x_get_flash_status(bank, &status);
220 if (retval != ERROR_OK)
223 if ((status & FLASH_QW) == 0)
226 if (timeout-- <= 0) {
227 LOG_ERROR("wait_flash_op_queue, time out expired, status: 0x%" PRIx32 "", status);
233 if (status & FLASH_WRPERR) {
234 LOG_ERROR("wait_flash_op_queue, WRPERR detected");
238 /* Clear error + EOP flags but report errors */
239 if (status & FLASH_ERROR) {
240 if (retval == ERROR_OK)
242 /* If this operation fails, we ignore it and report the original retval */
243 stm32x_write_flash_reg(bank, FLASH_CCR, status);
248 static int stm32x_unlock_reg(struct flash_bank *bank)
252 /* first check if not already unlocked
253 * otherwise writing on FLASH_KEYR will fail
255 int retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
256 if (retval != ERROR_OK)
259 if ((ctrl & FLASH_LOCK) == 0)
262 /* unlock flash registers for bank */
263 retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY1);
264 if (retval != ERROR_OK)
267 retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY2);
268 if (retval != ERROR_OK)
271 retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
272 if (retval != ERROR_OK)
275 if (ctrl & FLASH_LOCK) {
276 LOG_ERROR("flash not unlocked STM32_FLASH_CRx: %" PRIx32, ctrl);
277 return ERROR_TARGET_FAILURE;
282 static int stm32x_unlock_option_reg(struct flash_bank *bank)
286 int retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
287 if (retval != ERROR_OK)
290 if ((ctrl & OPT_LOCK) == 0)
293 /* unlock option registers */
294 retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY1);
295 if (retval != ERROR_OK)
298 retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY2);
299 if (retval != ERROR_OK)
302 retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
303 if (retval != ERROR_OK)
306 if (ctrl & OPT_LOCK) {
307 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
308 return ERROR_TARGET_FAILURE;
314 static inline int stm32x_lock_reg(struct flash_bank *bank)
316 return stm32x_write_flash_reg(bank, FLASH_CR, FLASH_LOCK);
319 static inline int stm32x_lock_option_reg(struct flash_bank *bank)
321 return stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_LOCK);
324 static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
328 /* unlock option bytes for modification */
329 retval = stm32x_unlock_option_reg(bank);
330 if (retval != ERROR_OK)
331 goto flash_options_lock;
333 /* write option bytes */
334 retval = stm32x_write_flash_reg(bank, reg_offset, value);
335 if (retval != ERROR_OK)
336 goto flash_options_lock;
338 /* Remove OPT error flag before programming */
339 retval = stm32x_write_flash_reg(bank, FLASH_OPTCCR, OPT_CLR_OPTCHANGEERR);
340 if (retval != ERROR_OK)
341 goto flash_options_lock;
343 /* start programming cycle */
344 retval = stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_START);
345 if (retval != ERROR_OK)
346 goto flash_options_lock;
348 /* wait for completion */
349 int timeout = FLASH_ERASE_TIMEOUT;
352 retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_CUR, &status);
353 if (retval != ERROR_OK) {
354 LOG_ERROR("stm32x_options_program: failed to read FLASH_OPTSR_CUR");
355 goto flash_options_lock;
357 if ((status & OPT_BSY) == 0)
360 if (timeout-- <= 0) {
361 LOG_ERROR("waiting for OBL launch, time out expired, OPTSR: 0x%" PRIx32 "", status);
363 goto flash_options_lock;
368 /* check for failure */
369 if (status & OPT_OPTCHANGEERR) {
370 LOG_ERROR("error changing option bytes (OPTCHANGEERR=1)");
371 retval = ERROR_FLASH_OPERATION_FAILED;
375 retval2 = stm32x_lock_option_reg(bank);
376 if (retval2 != ERROR_OK)
377 LOG_ERROR("error during the lock of flash options");
379 return (retval == ERROR_OK) ? retval2 : retval;
382 static int stm32x_modify_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
386 int retval = stm32x_read_flash_reg(bank, reg_offset, &data);
387 if (retval != ERROR_OK)
390 data = (data & ~mask) | (value & mask);
392 return stm32x_write_option(bank, reg_offset, data);
395 static int stm32x_protect_check(struct flash_bank *bank)
399 /* read 'write protection' settings */
400 int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
401 if (retval != ERROR_OK) {
402 LOG_DEBUG("unable to read WPSN_CUR register");
406 for (int i = 0; i < bank->num_sectors; i++) {
407 bank->sectors[i].is_protected = protection & (1 << i) ? 0 : 1;
412 static int stm32x_erase(struct flash_bank *bank, int first, int last)
416 assert(first < bank->num_sectors);
417 assert(last < bank->num_sectors);
419 if (bank->target->state != TARGET_HALTED)
420 return ERROR_TARGET_NOT_HALTED;
422 retval = stm32x_unlock_reg(bank);
423 if (retval != ERROR_OK)
428 To erase a sector, follow the procedure below:
429 1. Check that no Flash memory operation is ongoing by checking the QW bit in the
431 2. Set the SER bit and select the sector
432 you wish to erase (SNB) in the FLASH_CR register
433 3. Set the STRT bit in the FLASH_CR register
434 4. Wait for flash operations completion
436 for (int i = first; i <= last; i++) {
437 LOG_DEBUG("erase sector %d", i);
438 retval = stm32x_write_flash_reg(bank, FLASH_CR,
439 FLASH_SER | FLASH_SNB(i) | FLASH_PSIZE_64);
440 if (retval != ERROR_OK) {
441 LOG_ERROR("Error erase sector %d", i);
444 retval = stm32x_write_flash_reg(bank, FLASH_CR,
445 FLASH_SER | FLASH_SNB(i) | FLASH_PSIZE_64 | FLASH_START);
446 if (retval != ERROR_OK) {
447 LOG_ERROR("Error erase sector %d", i);
450 retval = stm32x_wait_flash_op_queue(bank, FLASH_ERASE_TIMEOUT);
452 if (retval != ERROR_OK) {
453 LOG_ERROR("erase time-out or operation error sector %d", i);
456 bank->sectors[i].is_erased = 1;
460 retval2 = stm32x_lock_reg(bank);
461 if (retval2 != ERROR_OK)
462 LOG_ERROR("error during the lock of flash");
464 return (retval == ERROR_OK) ? retval2 : retval;
467 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
469 struct target *target = bank->target;
472 if (target->state != TARGET_HALTED) {
473 LOG_ERROR("Target not halted");
474 return ERROR_TARGET_NOT_HALTED;
477 /* read 'write protection' settings */
478 int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
479 if (retval != ERROR_OK) {
480 LOG_DEBUG("unable to read WPSN_CUR register");
484 for (int i = first; i <= last; i++) {
486 protection &= ~(1 << i);
488 protection |= (1 << i);
491 /* apply WRPSN mask */
494 LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%" PRIx32, protection);
496 /* apply new option value */
497 return stm32x_write_option(bank, FLASH_WPSN_PRG, protection);
500 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
501 uint32_t offset, uint32_t count)
503 struct target *target = bank->target;
505 * If the size of the data part of the buffer is not a multiple of FLASH_BLOCK_SIZE, we get
506 * "corrupted fifo read" pointer in target_run_flash_async_algorithm()
508 uint32_t data_size = 512 * FLASH_BLOCK_SIZE; /* 16384 */
509 uint32_t buffer_size = 8 + data_size;
510 struct working_area *write_algorithm;
511 struct working_area *source;
512 uint32_t address = bank->base + offset;
513 struct reg_param reg_params[5];
514 struct armv7m_algorithm armv7m_info;
515 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
516 int retval = ERROR_OK;
518 static const uint8_t stm32x_flash_write_code[] = {
519 #include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
522 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
523 &write_algorithm) != ERROR_OK) {
524 LOG_WARNING("no working area available, can't do block memory writes");
525 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
528 retval = target_write_buffer(target, write_algorithm->address,
529 sizeof(stm32x_flash_write_code),
530 stm32x_flash_write_code);
531 if (retval != ERROR_OK) {
532 target_free_working_area(target, write_algorithm);
537 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
539 buffer_size = 8 + data_size;
540 if (data_size <= 256) {
541 /* we already allocated the writing code, but failed to get a
542 * buffer, free the algorithm */
543 target_free_working_area(target, write_algorithm);
545 LOG_WARNING("no large enough working area available, can't do block memory writes");
546 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
550 LOG_DEBUG("target_alloc_working_area_try : buffer_size -> 0x%" PRIx32, buffer_size);
552 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
553 armv7m_info.core_mode = ARM_MODE_THREAD;
555 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
556 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
557 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
558 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (word-256 bits) */
559 init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash reg base */
561 buf_set_u32(reg_params[0].value, 0, 32, source->address);
562 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
563 buf_set_u32(reg_params[2].value, 0, 32, address);
564 buf_set_u32(reg_params[3].value, 0, 32, count);
565 buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->flash_regs_base);
567 retval = target_run_flash_async_algorithm(target,
573 source->address, source->size,
574 write_algorithm->address, 0,
577 if (retval == ERROR_FLASH_OPERATION_FAILED) {
578 LOG_ERROR("error executing stm32h7x flash write algorithm");
580 uint32_t flash_sr = buf_get_u32(reg_params[0].value, 0, 32);
582 if (flash_sr & FLASH_WRPERR)
583 LOG_ERROR("flash memory write protected");
585 if ((flash_sr & FLASH_ERROR) != 0) {
586 LOG_ERROR("flash write failed, FLASH_SR = %08" PRIx32, flash_sr);
587 /* Clear error + EOP flags but report errors */
588 stm32x_write_flash_reg(bank, FLASH_CCR, flash_sr);
593 target_free_working_area(target, source);
594 target_free_working_area(target, write_algorithm);
596 destroy_reg_param(®_params[0]);
597 destroy_reg_param(®_params[1]);
598 destroy_reg_param(®_params[2]);
599 destroy_reg_param(®_params[3]);
600 destroy_reg_param(®_params[4]);
604 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
605 uint32_t offset, uint32_t count)
607 struct target *target = bank->target;
608 uint32_t address = bank->base + offset;
611 if (bank->target->state != TARGET_HALTED) {
612 LOG_ERROR("Target not halted");
613 return ERROR_TARGET_NOT_HALTED;
616 /* should be enforced via bank->write_start_alignment */
617 assert(!(offset % FLASH_BLOCK_SIZE));
619 /* should be enforced via bank->write_end_alignment */
620 assert(!(count % FLASH_BLOCK_SIZE));
622 retval = stm32x_unlock_reg(bank);
623 if (retval != ERROR_OK)
626 uint32_t blocks_remaining = count / FLASH_BLOCK_SIZE;
628 /* multiple words (32-bytes) to be programmed in block */
629 if (blocks_remaining) {
630 retval = stm32x_write_block(bank, buffer, offset, blocks_remaining);
631 if (retval != ERROR_OK) {
632 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
633 /* if block write failed (no sufficient working area),
634 * we use normal (slow) dword accesses */
635 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
638 buffer += blocks_remaining * FLASH_BLOCK_SIZE;
639 address += blocks_remaining * FLASH_BLOCK_SIZE;
640 blocks_remaining = 0;
642 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
648 The Flash memory programming sequence is as follows:
649 1. Check that no main Flash memory operation is ongoing by checking the QW bit in the
651 2. Set the PG bit in the FLASH_CR register
652 3. 8 x Word access (or Force Write FW)
653 4. Wait for flash operations completion
655 while (blocks_remaining > 0) {
656 retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_PG | FLASH_PSIZE_64);
657 if (retval != ERROR_OK)
660 retval = target_write_buffer(target, address, FLASH_BLOCK_SIZE, buffer);
661 if (retval != ERROR_OK)
664 retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
665 if (retval != ERROR_OK)
668 buffer += FLASH_BLOCK_SIZE;
669 address += FLASH_BLOCK_SIZE;
674 retval2 = stm32x_lock_reg(bank);
675 if (retval2 != ERROR_OK)
676 LOG_ERROR("error during the lock of flash");
678 return (retval == ERROR_OK) ? retval2 : retval;
681 static void setup_sector(struct flash_bank *bank, int start, int num, int size)
683 for (int i = start; i < (start + num) ; i++) {
684 assert(i < bank->num_sectors);
685 bank->sectors[i].offset = bank->size;
686 bank->sectors[i].size = size;
687 bank->size += bank->sectors[i].size;
691 static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
693 /* read stm32 device id register */
694 int retval = target_read_u32(bank->target, DBGMCU_IDCODE_REGISTER, id);
695 if (retval != ERROR_OK)
700 static int stm32x_probe(struct flash_bank *bank)
702 struct target *target = bank->target;
703 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
705 uint16_t flash_size_in_kb;
707 uint32_t base_address = FLASH_BANK0_ADDRESS;
708 uint32_t second_bank_base;
710 stm32x_info->probed = 0;
711 stm32x_info->part_info = NULL;
713 int retval = stm32x_read_id_code(bank, &stm32x_info->idcode);
714 if (retval != ERROR_OK)
717 LOG_DEBUG("device id = 0x%08" PRIx32 "", stm32x_info->idcode);
719 device_id = stm32x_info->idcode & 0xfff;
721 for (unsigned int n = 0; n < ARRAY_SIZE(stm32h7x_parts); n++) {
722 if (device_id == stm32h7x_parts[n].id)
723 stm32x_info->part_info = &stm32h7x_parts[n];
725 if (!stm32x_info->part_info) {
726 LOG_WARNING("Cannot identify target as a STM32H7xx family.");
729 LOG_INFO("Device: %s", stm32x_info->part_info->device_str);
732 /* update the address of controller from data base */
733 stm32x_info->flash_regs_base = stm32x_info->part_info->flash_regs_base;
735 /* get flash size from target */
736 retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb);
737 if (retval != ERROR_OK) {
738 /* read error when device has invalid value, set max flash size */
739 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
741 LOG_INFO("flash size probed value %d", flash_size_in_kb);
743 /* Lower flash size devices are single bank */
744 if (stm32x_info->part_info->has_dual_bank && (flash_size_in_kb > stm32x_info->part_info->first_bank_size_kb)) {
745 /* Use the configured base address to determine if this is the first or second flash bank.
746 * Verify that the base address is reasonably correct and determine the flash bank size
748 second_bank_base = base_address + stm32x_info->part_info->first_bank_size_kb * 1024;
749 if (bank->base == second_bank_base) {
750 /* This is the second bank */
751 base_address = second_bank_base;
752 flash_size_in_kb = flash_size_in_kb - stm32x_info->part_info->first_bank_size_kb;
753 /* bank1 also uses a register offset */
754 stm32x_info->flash_regs_base = FLASH_REG_BASE_B1;
755 } else if (bank->base == base_address) {
756 /* This is the first bank */
757 flash_size_in_kb = stm32x_info->part_info->first_bank_size_kb;
759 LOG_WARNING("STM32H flash bank base address config is incorrect. "
760 TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
761 bank->base, base_address, second_bank_base);
764 LOG_INFO("STM32H flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32,
765 bank->bank_number, flash_size_in_kb, base_address);
767 LOG_INFO("STM32H flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
770 /* if the user sets the size manually then ignore the probed value
771 * this allows us to work around devices that have an invalid flash size register value */
772 if (stm32x_info->user_bank_size) {
773 LOG_INFO("ignoring flash probed value, using configured bank size");
774 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
775 } else if (flash_size_in_kb == 0xffff) {
777 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
780 /* did we assign flash size? */
781 assert(flash_size_in_kb != 0xffff);
783 /* calculate numbers of pages */
784 int num_pages = flash_size_in_kb / stm32x_info->part_info->page_size;
786 /* check that calculation result makes sense */
787 assert(num_pages > 0);
791 bank->sectors = NULL;
794 bank->base = base_address;
795 bank->num_sectors = num_pages;
796 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
797 if (bank->sectors == NULL) {
798 LOG_ERROR("failed to allocate bank sectors");
804 setup_sector(bank, 0, num_pages, stm32x_info->part_info->page_size * 1024);
806 for (i = 0; i < num_pages; i++) {
807 bank->sectors[i].is_erased = -1;
808 bank->sectors[i].is_protected = 0;
811 stm32x_info->probed = 1;
815 static int stm32x_auto_probe(struct flash_bank *bank)
817 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
819 if (stm32x_info->probed)
822 return stm32x_probe(bank);
825 /* This method must return a string displaying information about the bank */
826 static int stm32x_get_info(struct flash_bank *bank, char *buf, int buf_size)
828 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
829 const struct stm32h7x_part_info *info = stm32x_info->part_info;
831 if (!stm32x_info->probed) {
832 int retval = stm32x_probe(bank);
833 if (retval != ERROR_OK) {
834 snprintf(buf, buf_size, "Unable to find bank information.");
840 const char *rev_str = NULL;
841 uint16_t rev_id = stm32x_info->idcode >> 16;
843 for (unsigned int i = 0; i < info->num_revs; i++)
844 if (rev_id == info->revs[i].rev)
845 rev_str = info->revs[i].str;
847 if (rev_str != NULL) {
848 snprintf(buf, buf_size, "%s - Rev: %s",
849 stm32x_info->part_info->device_str, rev_str);
851 snprintf(buf, buf_size,
852 "%s - Rev: unknown (0x%04x)",
853 stm32x_info->part_info->device_str, rev_id);
856 snprintf(buf, buf_size, "Cannot identify target as a STM32H7x");
862 static int stm32x_set_rdp(struct flash_bank *bank, enum stm32h7x_opt_rdp new_rdp)
864 struct target *target = bank->target;
865 uint32_t optsr, cur_rdp;
868 if (target->state != TARGET_HALTED) {
869 LOG_ERROR("Target not halted");
870 return ERROR_TARGET_NOT_HALTED;
873 retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_PRG, &optsr);
875 if (retval != ERROR_OK) {
876 LOG_DEBUG("unable to read FLASH_OPTSR_PRG register");
880 /* get current RDP, and check if there is a change */
881 cur_rdp = (optsr & OPT_RDP_MASK) >> OPT_RDP_POS;
882 if (new_rdp == cur_rdp) {
883 LOG_INFO("the requested RDP value is already programmed");
889 LOG_WARNING("unlocking the entire flash device");
892 LOG_WARNING("locking the entire flash device");
895 LOG_WARNING("locking the entire flash device, irreversible");
900 optsr = (optsr & ~OPT_RDP_MASK) | (new_rdp << OPT_RDP_POS);
902 /* apply new option value */
903 return stm32x_write_option(bank, FLASH_OPTSR_PRG, optsr);
906 COMMAND_HANDLER(stm32x_handle_lock_command)
909 return ERROR_COMMAND_SYNTAX_ERROR;
911 struct flash_bank *bank;
912 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
913 if (ERROR_OK != retval)
916 retval = stm32x_set_rdp(bank, OPT_RDP_L1);
918 if (retval != ERROR_OK)
919 command_print(CMD, "%s failed to lock device", bank->driver->name);
921 command_print(CMD, "%s locked", bank->driver->name);
926 COMMAND_HANDLER(stm32x_handle_unlock_command)
929 return ERROR_COMMAND_SYNTAX_ERROR;
931 struct flash_bank *bank;
932 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
933 if (ERROR_OK != retval)
936 retval = stm32x_set_rdp(bank, OPT_RDP_L0);
938 if (retval != ERROR_OK)
939 command_print(CMD, "%s failed to unlock device", bank->driver->name);
941 command_print(CMD, "%s unlocked", bank->driver->name);
946 static int stm32x_mass_erase(struct flash_bank *bank)
949 struct target *target = bank->target;
951 if (target->state != TARGET_HALTED) {
952 LOG_ERROR("Target not halted");
953 return ERROR_TARGET_NOT_HALTED;
956 retval = stm32x_unlock_reg(bank);
957 if (retval != ERROR_OK)
960 /* mass erase flash memory bank */
961 retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_BER | FLASH_PSIZE_64);
962 if (retval != ERROR_OK)
965 retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_BER | FLASH_PSIZE_64 | FLASH_START);
966 if (retval != ERROR_OK)
969 retval = stm32x_wait_flash_op_queue(bank, 30000);
970 if (retval != ERROR_OK)
974 retval2 = stm32x_lock_reg(bank);
975 if (retval2 != ERROR_OK)
976 LOG_ERROR("error during the lock of flash");
978 return (retval == ERROR_OK) ? retval2 : retval;
981 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
986 command_print(CMD, "stm32h7x mass_erase <bank>");
987 return ERROR_COMMAND_SYNTAX_ERROR;
990 struct flash_bank *bank;
991 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
992 if (ERROR_OK != retval)
995 retval = stm32x_mass_erase(bank);
996 if (retval == ERROR_OK) {
997 /* set all sectors as erased */
998 for (i = 0; i < bank->num_sectors; i++)
999 bank->sectors[i].is_erased = 1;
1001 command_print(CMD, "stm32h7x mass erase complete");
1003 command_print(CMD, "stm32h7x mass erase failed");
1009 COMMAND_HANDLER(stm32x_handle_option_read_command)
1012 command_print(CMD, "stm32h7x option_read <bank> <option_reg offset>");
1013 return ERROR_COMMAND_SYNTAX_ERROR;
1016 struct flash_bank *bank;
1017 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1018 if (ERROR_OK != retval)
1021 uint32_t reg_offset, value;
1023 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1024 retval = stm32x_read_flash_reg(bank, reg_offset, &value);
1025 if (ERROR_OK != retval)
1028 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "",
1029 stm32x_get_flash_reg(bank, reg_offset), value);
1034 COMMAND_HANDLER(stm32x_handle_option_write_command)
1037 command_print(CMD, "stm32h7x option_write <bank> <option_reg offset> <value> [mask]");
1038 return ERROR_COMMAND_SYNTAX_ERROR;
1041 struct flash_bank *bank;
1042 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1043 if (ERROR_OK != retval)
1046 uint32_t reg_offset, value, mask = 0xffffffff;
1048 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1049 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1051 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
1053 return stm32x_modify_option(bank, reg_offset, value, mask);
1056 static const struct command_registration stm32x_exec_command_handlers[] = {
1059 .handler = stm32x_handle_lock_command,
1060 .mode = COMMAND_EXEC,
1062 .help = "Lock entire flash device.",
1066 .handler = stm32x_handle_unlock_command,
1067 .mode = COMMAND_EXEC,
1069 .help = "Unlock entire protected flash device.",
1072 .name = "mass_erase",
1073 .handler = stm32x_handle_mass_erase_command,
1074 .mode = COMMAND_EXEC,
1076 .help = "Erase entire flash device.",
1079 .name = "option_read",
1080 .handler = stm32x_handle_option_read_command,
1081 .mode = COMMAND_EXEC,
1082 .usage = "bank_id reg_offset",
1083 .help = "Read and display device option bytes.",
1086 .name = "option_write",
1087 .handler = stm32x_handle_option_write_command,
1088 .mode = COMMAND_EXEC,
1089 .usage = "bank_id reg_offset value [mask]",
1090 .help = "Write device option bit fields with provided value.",
1092 COMMAND_REGISTRATION_DONE
1095 static const struct command_registration stm32x_command_handlers[] = {
1098 .mode = COMMAND_ANY,
1099 .help = "stm32h7x flash command group",
1101 .chain = stm32x_exec_command_handlers,
1103 COMMAND_REGISTRATION_DONE
1106 const struct flash_driver stm32h7x_flash = {
1108 .commands = stm32x_command_handlers,
1109 .flash_bank_command = stm32x_flash_bank_command,
1110 .erase = stm32x_erase,
1111 .protect = stm32x_protect,
1112 .write = stm32x_write,
1113 .read = default_flash_read,
1114 .probe = stm32x_probe,
1115 .auto_probe = stm32x_auto_probe,
1116 .erase_check = default_flash_blank_check,
1117 .protect_check = stm32x_protect_check,
1118 .info = stm32x_get_info,
1119 .free_driver_priv = default_flash_free_driver_priv,