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   1 /***************************************************************************
   2  *   Copyright (C) 2017 by STMicroelectronics                              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  16  ***************************************************************************/
  17 #ifdef HAVE_CONFIG_H
  18 #include "config.h"
  19 #endif
  20
  21 #include "imp.h"
  22 #include <helper/binarybuffer.h>
  23 #include <target/algorithm.h>
  24 #include <target/armv7m.h>
  25
  26
  27 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
  28 #define FLASH_ERASE_TIMEOUT 10000
  29 #define FLASH_WRITE_TIMEOUT 5
  30
  31 /* RM 433 */
  32 /* Same Flash registers for both banks, */
  33 /* access depends on Flash Base address */
  34 #define FLASH_ACR       0x00
  35 #define FLASH_KEYR      0x04
  36 #define FLASH_OPTKEYR   0x08
  37 #define FLASH_CR        0x0C
  38 #define FLASH_SR        0x10
  39 #define FLASH_CCR       0x14
  40 #define FLASH_OPTCR     0x18
  41 #define FLASH_OPTSR_CUR 0x1C
  42 #define FLASH_OPTSR_PRG 0x20
  43 #define FLASH_OPTCCR    0x24
  44 #define FLASH_WPSN_CUR  0x38
  45 #define FLASH_WPSN_PRG  0x3C
  46
  47
  48 /* FLASH_CR register bits */
  49 #define FLASH_LOCK     (1 << 0)
  50 #define FLASH_PG       (1 << 1)
  51 #define FLASH_SER      (1 << 2)
  52 #define FLASH_BER      (1 << 3)
  53 #define FLASH_PSIZE_8  (0 << 4)
  54 #define FLASH_PSIZE_16 (1 << 4)
  55 #define FLASH_PSIZE_32 (2 << 4)
  56 #define FLASH_PSIZE_64 (3 << 4)
  57 #define FLASH_FW       (1 << 6)
  58 #define FLASH_START    (1 << 7)
  59
  60 /* FLASH_SR register bits */
  61 #define FLASH_BSY      (1 << 0)  /* Operation in progress */
  62 #define FLASH_QW       (1 << 2)  /* Operation queue in progress */
  63 #define FLASH_WRPERR   (1 << 17) /* Write protection error */
  64 #define FLASH_PGSERR   (1 << 18) /* Programming sequence error */
  65 #define FLASH_STRBERR  (1 << 19) /* Strobe error */
  66 #define FLASH_INCERR   (1 << 21) /* Inconsistency error */
  67 #define FLASH_OPERR    (1 << 22) /* Operation error */
  68 #define FLASH_RDPERR   (1 << 23) /* Read Protection error */
  69 #define FLASH_RDSERR   (1 << 24) /* Secure Protection error */
  70 #define FLASH_SNECCERR (1 << 25) /* Single ECC error */
  71 #define FLASH_DBECCERR (1 << 26) /* Double ECC error */
  72
  73 #define FLASH_ERROR (FLASH_WRPERR | FLASH_PGSERR | FLASH_STRBERR | FLASH_INCERR | FLASH_OPERR | \
  74                                          FLASH_RDPERR | FLASH_RDSERR | FLASH_SNECCERR | FLASH_DBECCERR)
  75
  76 /* FLASH_OPTCR register bits */
  77 #define OPT_LOCK       (1 << 0)
  78 #define OPT_START      (1 << 1)
  79
  80 /* FLASH_OPTSR register bits */
  81 #define OPT_BSY        (1 << 0)
  82 #define OPT_RDP_POS    8
  83 #define OPT_RDP_MASK   (0xff << OPT_RDP_POS)
  84 #define OPT_OPTCHANGEERR (1 << 30)
  85
  86 /* FLASH_OPTCCR register bits */
  87 #define OPT_CLR_OPTCHANGEERR (1 << 30)
  88
  89 /* register unlock keys */
  90 #define KEY1           0x45670123
  91 #define KEY2           0xCDEF89AB
  92
  93 /* option register unlock key */
  94 #define OPTKEY1        0x08192A3B
  95 #define OPTKEY2        0x4C5D6E7F
  96
  97 #define DBGMCU_IDCODE_REGISTER  0x5C001000
  98 #define FLASH_BANK0_ADDRESS     0x08000000
  99 #define FLASH_BANK1_ADDRESS     0x08100000
 100 #define FLASH_REG_BASE_B0       0x52002000
 101 #define FLASH_REG_BASE_B1       0x52002100
 102
 103 struct stm32h7x_rev {
 104         uint16_t rev;
 105         const char *str;
 106 };
 107
 108 /* stm32h7x_part_info permits the store each device information and specificities.
 109  * the default unit is byte unless the suffix '_kb' is used. */
 110
 111 struct stm32h7x_part_info {
 112         uint16_t id;
 113         const char *device_str;
 114         const struct stm32h7x_rev *revs;
 115         size_t num_revs;
 116         unsigned int page_size_kb;
 117         unsigned int block_size;     /* flash write word size in bytes */
 118         uint16_t max_flash_size_kb;
 119         uint8_t has_dual_bank;
 120         uint16_t first_bank_size_kb; /* Used when has_dual_bank is true */
 121         uint32_t flash_regs_base;    /* Flash controller registers location */
 122         uint32_t fsize_addr;         /* Location of FSIZE register */
 123         uint32_t wps_group_size; /* write protection group sectors' count */
 124         uint32_t wps_mask;
 125         /* function to compute flash_cr register values */
 126         uint32_t (*compute_flash_cr)(uint32_t cmd, int snb);
 127 };
 128
 129 struct stm32h7x_flash_bank {
 130         bool probed;
 131         uint32_t idcode;
 132         uint32_t user_bank_size;
 133         uint32_t flash_regs_base;    /* Address of flash reg controller */
 134         const struct stm32h7x_part_info *part_info;
 135 };
 136
 137 enum stm32h7x_opt_rdp {
 138         OPT_RDP_L0 = 0xaa,
 139         OPT_RDP_L1 = 0x00,
 140         OPT_RDP_L2 = 0xcc
 141 };
 142
 143 static const struct stm32h7x_rev stm32_450_revs[] = {
 144         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X"  }, { 0x2003, "V"  },
 145 };
 146
 147 static const struct stm32h7x_rev stm32_480_revs[] = {
 148         { 0x1000, "A"},
 149 };
 150
 151 static uint32_t stm32x_compute_flash_cr_450(uint32_t cmd, int snb)
 152 {
 153         return cmd | (snb << 8);
 154 }
 155
 156 static uint32_t stm32x_compute_flash_cr_480(uint32_t cmd, int snb)
 157 {
 158         /* save FW and START bits, to be right shifted by 2 bits later */
 159         const uint32_t tmp = cmd & (FLASH_FW | FLASH_START);
 160
 161         /* mask parallelism (ignored), FW and START bits */
 162         cmd &= ~(FLASH_PSIZE_64 | FLASH_FW | FLASH_START);
 163
 164         return cmd | (tmp >> 2) | (snb << 6);
 165 }
 166
 167 static const struct stm32h7x_part_info stm32h7x_parts[] = {
 168         {
 169         .id                                     = 0x450,
 170         .revs                           = stm32_450_revs,
 171         .num_revs                       = ARRAY_SIZE(stm32_450_revs),
 172         .device_str                     = "STM32H74x/75x",
 173         .page_size_kb           = 128,
 174         .block_size                     = 32,
 175         .max_flash_size_kb      = 2048,
 176         .first_bank_size_kb     = 1024,
 177         .has_dual_bank          = 1,
 178         .flash_regs_base        = FLASH_REG_BASE_B0,
 179         .fsize_addr                     = 0x1FF1E880,
 180         .wps_group_size         = 1,
 181         .wps_mask                       = 0xFF,
 182         .compute_flash_cr       = stm32x_compute_flash_cr_450,
 183         },
 184         {
 185         .id                                     = 0x480,
 186         .revs                           = stm32_480_revs,
 187         .num_revs                       = ARRAY_SIZE(stm32_480_revs),
 188         .device_str                     = "STM32H7Ax/7Bx",
 189         .page_size_kb           = 8,
 190         .block_size                     = 16,
 191         .max_flash_size_kb      = 2048,
 192         .first_bank_size_kb     = 1024,
 193         .has_dual_bank          = 1,
 194         .flash_regs_base        = FLASH_REG_BASE_B0,
 195         .fsize_addr                     = 0x08FFF80C,
 196         .wps_group_size         = 4,
 197         .wps_mask                       = 0xFFFFFFFF,
 198         .compute_flash_cr       = stm32x_compute_flash_cr_480,
 199         },
 200 };
 201
 202 /* flash bank stm32x <base> <size> 0 0 <target#> */
 203
 204 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 205 {
 206         struct stm32h7x_flash_bank *stm32x_info;
 207
 208         if (CMD_ARGC < 6)
 209                 return ERROR_COMMAND_SYNTAX_ERROR;
 210
 211         stm32x_info = malloc(sizeof(struct stm32h7x_flash_bank));
 212         bank->driver_priv = stm32x_info;
 213
 214         stm32x_info->probed = false;
 215         stm32x_info->user_bank_size = bank->size;
 216
 217         return ERROR_OK;
 218 }
 219
 220 static inline uint32_t stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
 221 {
 222         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 223         return reg_offset + stm32x_info->flash_regs_base;
 224 }
 225
 226 static inline int stm32x_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
 227 {
 228         uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
 229         int retval = target_read_u32(bank->target, reg_addr, value);
 230
 231         if (retval != ERROR_OK)
 232                 LOG_ERROR("error while reading from address 0x%" PRIx32, reg_addr);
 233
 234         return retval;
 235 }
 236
 237 static inline int stm32x_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
 238 {
 239         uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
 240         int retval = target_write_u32(bank->target, reg_addr, value);
 241
 242         if (retval != ERROR_OK)
 243                 LOG_ERROR("error while writing to address 0x%" PRIx32, reg_addr);
 244
 245         return retval;
 246 }
 247
 248 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 249 {
 250         return stm32x_read_flash_reg(bank, FLASH_SR, status);
 251 }
 252
 253 static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
 254 {
 255         uint32_t status;
 256         int retval;
 257
 258         /* wait for flash operations completion */
 259         for (;;) {
 260                 retval = stm32x_get_flash_status(bank, &status);
 261                 if (retval != ERROR_OK)
 262                         return retval;
 263
 264                 if ((status & FLASH_QW) == 0)
 265                         break;
 266
 267                 if (timeout-- <= 0) {
 268                         LOG_ERROR("wait_flash_op_queue, time out expired, status: 0x%" PRIx32 "", status);
 269                         return ERROR_FAIL;
 270                 }
 271                 alive_sleep(1);
 272         }
 273
 274         if (status & FLASH_WRPERR) {
 275                 LOG_ERROR("wait_flash_op_queue, WRPERR detected");
 276                 retval = ERROR_FAIL;
 277         }
 278
 279         /* Clear error + EOP flags but report errors */
 280         if (status & FLASH_ERROR) {
 281                 if (retval == ERROR_OK)
 282                         retval = ERROR_FAIL;
 283                 /* If this operation fails, we ignore it and report the original retval */
 284                 stm32x_write_flash_reg(bank, FLASH_CCR, status);
 285         }
 286         return retval;
 287 }
 288
 289 static int stm32x_unlock_reg(struct flash_bank *bank)
 290 {
 291         uint32_t ctrl;
 292
 293         /* first check if not already unlocked
 294          * otherwise writing on FLASH_KEYR will fail
 295          */
 296         int retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
 297         if (retval != ERROR_OK)
 298                 return retval;
 299
 300         if ((ctrl & FLASH_LOCK) == 0)
 301                 return ERROR_OK;
 302
 303         /* unlock flash registers for bank */
 304         retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY1);
 305         if (retval != ERROR_OK)
 306                 return retval;
 307
 308         retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY2);
 309         if (retval != ERROR_OK)
 310                 return retval;
 311
 312         retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
 313         if (retval != ERROR_OK)
 314                 return retval;
 315
 316         if (ctrl & FLASH_LOCK) {
 317                 LOG_ERROR("flash not unlocked STM32_FLASH_CRx: %" PRIx32, ctrl);
 318                 return ERROR_TARGET_FAILURE;
 319         }
 320         return ERROR_OK;
 321 }
 322
 323 static int stm32x_unlock_option_reg(struct flash_bank *bank)
 324 {
 325         uint32_t ctrl;
 326
 327         int retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
 328         if (retval != ERROR_OK)
 329                 return retval;
 330
 331         if ((ctrl & OPT_LOCK) == 0)
 332                 return ERROR_OK;
 333
 334         /* unlock option registers */
 335         retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY1);
 336         if (retval != ERROR_OK)
 337                 return retval;
 338
 339         retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY2);
 340         if (retval != ERROR_OK)
 341                 return retval;
 342
 343         retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
 344         if (retval != ERROR_OK)
 345                 return retval;
 346
 347         if (ctrl & OPT_LOCK) {
 348                 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
 349                 return ERROR_TARGET_FAILURE;
 350         }
 351
 352         return ERROR_OK;
 353 }
 354
 355 static inline int stm32x_lock_reg(struct flash_bank *bank)
 356 {
 357         return stm32x_write_flash_reg(bank, FLASH_CR, FLASH_LOCK);
 358 }
 359
 360 static inline int stm32x_lock_option_reg(struct flash_bank *bank)
 361 {
 362         return stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_LOCK);
 363 }
 364
 365 static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
 366 {
 367         int retval, retval2;
 368
 369         /* unlock option bytes for modification */
 370         retval = stm32x_unlock_option_reg(bank);
 371         if (retval != ERROR_OK)
 372                 goto flash_options_lock;
 373
 374         /* write option bytes */
 375         retval = stm32x_write_flash_reg(bank, reg_offset, value);
 376         if (retval != ERROR_OK)
 377                 goto flash_options_lock;
 378
 379         /* Remove OPT error flag before programming */
 380         retval = stm32x_write_flash_reg(bank, FLASH_OPTCCR, OPT_CLR_OPTCHANGEERR);
 381         if (retval != ERROR_OK)
 382                 goto flash_options_lock;
 383
 384         /* start programming cycle */
 385         retval = stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_START);
 386         if (retval != ERROR_OK)
 387                 goto flash_options_lock;
 388
 389         /* wait for completion */
 390         int timeout = FLASH_ERASE_TIMEOUT;
 391         uint32_t status;
 392         for (;;) {
 393                 retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_CUR, &status);
 394                 if (retval != ERROR_OK) {
 395                         LOG_ERROR("stm32x_options_program: failed to read FLASH_OPTSR_CUR");
 396                         goto flash_options_lock;
 397                 }
 398                 if ((status & OPT_BSY) == 0)
 399                         break;
 400
 401                 if (timeout-- <= 0) {
 402                         LOG_ERROR("waiting for OBL launch, time out expired, OPTSR: 0x%" PRIx32 "", status);
 403                         retval = ERROR_FAIL;
 404                         goto flash_options_lock;
 405                 }
 406                 alive_sleep(1);
 407         }
 408
 409         /* check for failure */
 410         if (status & OPT_OPTCHANGEERR) {
 411                 LOG_ERROR("error changing option bytes (OPTCHANGEERR=1)");
 412                 retval = ERROR_FLASH_OPERATION_FAILED;
 413         }
 414
 415 flash_options_lock:
 416         retval2 = stm32x_lock_option_reg(bank);
 417         if (retval2 != ERROR_OK)
 418                 LOG_ERROR("error during the lock of flash options");
 419
 420         return (retval == ERROR_OK) ? retval2 : retval;
 421 }
 422
 423 static int stm32x_modify_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
 424 {
 425         uint32_t data;
 426
 427         int retval = stm32x_read_flash_reg(bank, reg_offset, &data);
 428         if (retval != ERROR_OK)
 429                 return retval;
 430
 431         data = (data & ~mask) | (value & mask);
 432
 433         return stm32x_write_option(bank, reg_offset, data);
 434 }
 435
 436 static int stm32x_protect_check(struct flash_bank *bank)
 437 {
 438         uint32_t protection;
 439
 440         /* read 'write protection' settings */
 441         int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
 442         if (retval != ERROR_OK) {
 443                 LOG_DEBUG("unable to read WPSN_CUR register");
 444                 return retval;
 445         }
 446
 447         for (int i = 0; i < bank->num_prot_blocks; i++)
 448                 bank->prot_blocks[i].is_protected = protection & (1 << i) ? 0 : 1;
 449
 450         return ERROR_OK;
 451 }
 452
 453 static int stm32x_erase(struct flash_bank *bank, int first, int last)
 454 {
 455         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 456         int retval, retval2;
 457
 458         assert(first < bank->num_sectors);
 459         assert(last < bank->num_sectors);
 460
 461         if (bank->target->state != TARGET_HALTED)
 462                 return ERROR_TARGET_NOT_HALTED;
 463
 464         retval = stm32x_unlock_reg(bank);
 465         if (retval != ERROR_OK)
 466                 goto flash_lock;
 467
 468         /*
 469         Sector Erase
 470         To erase a sector, follow the procedure below:
 471         1. Check that no Flash memory operation is ongoing by checking the QW bit in the
 472           FLASH_SR register
 473         2. Set the SER bit and select the sector
 474           you wish to erase (SNB) in the FLASH_CR register
 475         3. Set the STRT bit in the FLASH_CR register
 476         4. Wait for flash operations completion
 477          */
 478         for (int i = first; i <= last; i++) {
 479                 LOG_DEBUG("erase sector %d", i);
 480                 retval = stm32x_write_flash_reg(bank, FLASH_CR,
 481                                 stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64, i));
 482                 if (retval != ERROR_OK) {
 483                         LOG_ERROR("Error erase sector %d", i);
 484                         goto flash_lock;
 485                 }
 486                 retval = stm32x_write_flash_reg(bank, FLASH_CR,
 487                                 stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64 | FLASH_START, i));
 488                 if (retval != ERROR_OK) {
 489                         LOG_ERROR("Error erase sector %d", i);
 490                         goto flash_lock;
 491                 }
 492                 retval = stm32x_wait_flash_op_queue(bank, FLASH_ERASE_TIMEOUT);
 493
 494                 if (retval != ERROR_OK) {
 495                         LOG_ERROR("erase time-out or operation error sector %d", i);
 496                         goto flash_lock;
 497                 }
 498                 bank->sectors[i].is_erased = 1;
 499         }
 500
 501 flash_lock:
 502         retval2 = stm32x_lock_reg(bank);
 503         if (retval2 != ERROR_OK)
 504                 LOG_ERROR("error during the lock of flash");
 505
 506         return (retval == ERROR_OK) ? retval2 : retval;
 507 }
 508
 509 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
 510 {
 511         struct target *target = bank->target;
 512         uint32_t protection;
 513
 514         if (target->state != TARGET_HALTED) {
 515                 LOG_ERROR("Target not halted");
 516                 return ERROR_TARGET_NOT_HALTED;
 517         }
 518
 519         /* read 'write protection' settings */
 520         int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
 521         if (retval != ERROR_OK) {
 522                 LOG_DEBUG("unable to read WPSN_CUR register");
 523                 return retval;
 524         }
 525
 526         for (int i = first; i <= last; i++) {
 527                 if (set)
 528                         protection &= ~(1 << i);
 529                 else
 530                         protection |= (1 << i);
 531         }
 532
 533         /* apply WRPSN mask */
 534         protection &= 0xff;
 535
 536         LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%" PRIx32, protection);
 537
 538         /* apply new option value */
 539         return stm32x_write_option(bank, FLASH_WPSN_PRG, protection);
 540 }
 541
 542 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 543                 uint32_t offset, uint32_t count)
 544 {
 545         struct target *target = bank->target;
 546         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 547         /*
 548          * If the size of the data part of the buffer is not a multiple of .block_size, we get
 549          * "corrupted fifo read" pointer in target_run_flash_async_algorithm()
 550          */
 551         uint32_t data_size = 512 * stm32x_info->part_info->block_size;
 552         uint32_t buffer_size = 8 + data_size;
 553         struct working_area *write_algorithm;
 554         struct working_area *source;
 555         uint32_t address = bank->base + offset;
 556         struct reg_param reg_params[6];
 557         struct armv7m_algorithm armv7m_info;
 558         int retval = ERROR_OK;
 559
 560         static const uint8_t stm32x_flash_write_code[] = {
 561 #include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
 562         };
 563
 564         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 565                         &write_algorithm) != ERROR_OK) {
 566                 LOG_WARNING("no working area available, can't do block memory writes");
 567                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 568         }
 569
 570         retval = target_write_buffer(target, write_algorithm->address,
 571                         sizeof(stm32x_flash_write_code),
 572                         stm32x_flash_write_code);
 573         if (retval != ERROR_OK) {
 574                 target_free_working_area(target, write_algorithm);
 575                 return retval;
 576         }
 577
 578         /* memory buffer */
 579         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 580                 data_size /= 2;
 581                 buffer_size = 8 + data_size;
 582                 if (data_size <= 256) {
 583                         /* we already allocated the writing code, but failed to get a
 584                          * buffer, free the algorithm */
 585                         target_free_working_area(target, write_algorithm);
 586
 587                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 588                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 589                 }
 590         }
 591
 592         LOG_DEBUG("target_alloc_working_area_try : buffer_size -> 0x%" PRIx32, buffer_size);
 593
 594         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 595         armv7m_info.core_mode = ARM_MODE_THREAD;
 596
 597         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);         /* buffer start, status (out) */
 598         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);            /* buffer end */
 599         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);            /* target address */
 600         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);            /* count of words (word size = .block_size (bytes) */
 601         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);            /* word size in bytes */
 602         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);            /* flash reg base */
 603
 604         buf_set_u32(reg_params[0].value, 0, 32, source->address);
 605         buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
 606         buf_set_u32(reg_params[2].value, 0, 32, address);
 607         buf_set_u32(reg_params[3].value, 0, 32, count);
 608         buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->part_info->block_size);
 609         buf_set_u32(reg_params[5].value, 0, 32, stm32x_info->flash_regs_base);
 610
 611         retval = target_run_flash_async_algorithm(target,
 612                                                   buffer,
 613                                                   count,
 614                                                   stm32x_info->part_info->block_size,
 615                                                   0, NULL,
 616                                                   ARRAY_SIZE(reg_params), reg_params,
 617                                                   source->address, source->size,
 618                                                   write_algorithm->address, 0,
 619                                                   &armv7m_info);
 620
 621         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 622                 LOG_ERROR("error executing stm32h7x flash write algorithm");
 623
 624                 uint32_t flash_sr = buf_get_u32(reg_params[0].value, 0, 32);
 625
 626                 if (flash_sr & FLASH_WRPERR)
 627                         LOG_ERROR("flash memory write protected");
 628
 629                 if ((flash_sr & FLASH_ERROR) != 0) {
 630                         LOG_ERROR("flash write failed, FLASH_SR = %08" PRIx32, flash_sr);
 631                         /* Clear error + EOP flags but report errors */
 632                         stm32x_write_flash_reg(bank, FLASH_CCR, flash_sr);
 633                         retval = ERROR_FAIL;
 634                 }
 635         }
 636
 637         target_free_working_area(target, source);
 638         target_free_working_area(target, write_algorithm);
 639
 640         destroy_reg_param(&reg_params[0]);
 641         destroy_reg_param(&reg_params[1]);
 642         destroy_reg_param(&reg_params[2]);
 643         destroy_reg_param(&reg_params[3]);
 644         destroy_reg_param(&reg_params[4]);
 645         destroy_reg_param(&reg_params[5]);
 646         return retval;
 647 }
 648
 649 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 650                 uint32_t offset, uint32_t count)
 651 {
 652         struct target *target = bank->target;
 653         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 654         uint32_t address = bank->base + offset;
 655         int retval, retval2;
 656
 657         if (bank->target->state != TARGET_HALTED) {
 658                 LOG_ERROR("Target not halted");
 659                 return ERROR_TARGET_NOT_HALTED;
 660         }
 661
 662         /* should be enforced via bank->write_start_alignment */
 663         assert(!(offset % stm32x_info->part_info->block_size));
 664
 665         /* should be enforced via bank->write_end_alignment */
 666         assert(!(count % stm32x_info->part_info->block_size));
 667
 668         retval = stm32x_unlock_reg(bank);
 669         if (retval != ERROR_OK)
 670                 goto flash_lock;
 671
 672         uint32_t blocks_remaining = count / stm32x_info->part_info->block_size;
 673
 674         /* multiple words (n * .block_size) to be programmed in block */
 675         if (blocks_remaining) {
 676                 retval = stm32x_write_block(bank, buffer, offset, blocks_remaining);
 677                 if (retval != ERROR_OK) {
 678                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 679                                 /* if block write failed (no sufficient working area),
 680                                  * we use normal (slow) dword accesses */
 681                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 682                         }
 683                 } else {
 684                         buffer += blocks_remaining * stm32x_info->part_info->block_size;
 685                         address += blocks_remaining * stm32x_info->part_info->block_size;
 686                         blocks_remaining = 0;
 687                 }
 688                 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
 689                         goto flash_lock;
 690         }
 691
 692         /*
 693         Standard programming
 694         The Flash memory programming sequence is as follows:
 695         1. Check that no main Flash memory operation is ongoing by checking the QW bit in the
 696            FLASH_SR register.
 697         2. Set the PG bit in the FLASH_CR register
 698         3. 8 x Word access (or Force Write FW)
 699         4. Wait for flash operations completion
 700         */
 701         while (blocks_remaining > 0) {
 702                 retval = stm32x_write_flash_reg(bank, FLASH_CR,
 703                                 stm32x_info->part_info->compute_flash_cr(FLASH_PG | FLASH_PSIZE_64, 0));
 704                 if (retval != ERROR_OK)
 705                         goto flash_lock;
 706
 707                 retval = target_write_buffer(target, address, stm32x_info->part_info->block_size, buffer);
 708                 if (retval != ERROR_OK)
 709                         goto flash_lock;
 710
 711                 retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
 712                 if (retval != ERROR_OK)
 713                         goto flash_lock;
 714
 715                 buffer += stm32x_info->part_info->block_size;
 716                 address += stm32x_info->part_info->block_size;
 717                 blocks_remaining--;
 718         }
 719
 720 flash_lock:
 721         retval2 = stm32x_lock_reg(bank);
 722         if (retval2 != ERROR_OK)
 723                 LOG_ERROR("error during the lock of flash");
 724
 725         return (retval == ERROR_OK) ? retval2 : retval;
 726 }
 727
 728 static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
 729 {
 730         /* read stm32 device id register */
 731         int retval = target_read_u32(bank->target, DBGMCU_IDCODE_REGISTER, id);
 732         if (retval != ERROR_OK)
 733                 return retval;
 734         return ERROR_OK;
 735 }
 736
 737 static int stm32x_probe(struct flash_bank *bank)
 738 {
 739         struct target *target = bank->target;
 740         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 741         uint16_t flash_size_in_kb;
 742         uint32_t device_id;
 743         uint32_t base_address = FLASH_BANK0_ADDRESS;
 744         uint32_t second_bank_base;
 745
 746         stm32x_info->probed = false;
 747         stm32x_info->part_info = NULL;
 748
 749         int retval = stm32x_read_id_code(bank, &stm32x_info->idcode);
 750         if (retval != ERROR_OK)
 751                 return retval;
 752
 753         LOG_DEBUG("device id = 0x%08" PRIx32 "", stm32x_info->idcode);
 754
 755         device_id = stm32x_info->idcode & 0xfff;
 756
 757         for (unsigned int n = 0; n < ARRAY_SIZE(stm32h7x_parts); n++) {
 758                 if (device_id == stm32h7x_parts[n].id)
 759                         stm32x_info->part_info = &stm32h7x_parts[n];
 760         }
 761         if (!stm32x_info->part_info) {
 762                 LOG_WARNING("Cannot identify target as a STM32H7xx family.");
 763                 return ERROR_FAIL;
 764         } else {
 765                 LOG_INFO("Device: %s", stm32x_info->part_info->device_str);
 766         }
 767
 768         /* update the address of controller from data base */
 769         stm32x_info->flash_regs_base = stm32x_info->part_info->flash_regs_base;
 770
 771         /* get flash size from target */
 772         retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb);
 773         if (retval != ERROR_OK) {
 774                 /* read error when device has invalid value, set max flash size */
 775                 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
 776         } else
 777                 LOG_INFO("flash size probed value %d", flash_size_in_kb);
 778
 779         /* Lower flash size devices are single bank */
 780         if (stm32x_info->part_info->has_dual_bank && (flash_size_in_kb > stm32x_info->part_info->first_bank_size_kb)) {
 781                 /* Use the configured base address to determine if this is the first or second flash bank.
 782                  * Verify that the base address is reasonably correct and determine the flash bank size
 783                  */
 784                 second_bank_base = base_address + stm32x_info->part_info->first_bank_size_kb * 1024;
 785                 if (bank->base == second_bank_base) {
 786                         /* This is the second bank  */
 787                         base_address = second_bank_base;
 788                         flash_size_in_kb = flash_size_in_kb - stm32x_info->part_info->first_bank_size_kb;
 789                         /* bank1 also uses a register offset */
 790                         stm32x_info->flash_regs_base = FLASH_REG_BASE_B1;
 791                 } else if (bank->base == base_address) {
 792                         /* This is the first bank */
 793                         flash_size_in_kb = stm32x_info->part_info->first_bank_size_kb;
 794                 } else {
 795                         LOG_WARNING("STM32H flash bank base address config is incorrect. "
 796                                     TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
 797                                         bank->base, base_address, second_bank_base);
 798                         return ERROR_FAIL;
 799                 }
 800                 LOG_INFO("STM32H flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32,
 801                                 bank->bank_number, flash_size_in_kb, base_address);
 802         } else {
 803                 LOG_INFO("STM32H flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
 804         }
 805
 806         /* if the user sets the size manually then ignore the probed value
 807          * this allows us to work around devices that have an invalid flash size register value */
 808         if (stm32x_info->user_bank_size) {
 809                 LOG_INFO("ignoring flash probed value, using configured bank size");
 810                 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
 811         } else if (flash_size_in_kb == 0xffff) {
 812                 /* die flash size */
 813                 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
 814         }
 815
 816         /* did we assign flash size? */
 817         assert(flash_size_in_kb != 0xffff);
 818
 819         bank->base = base_address;
 820         bank->size = flash_size_in_kb * 1024;
 821         bank->write_start_alignment = stm32x_info->part_info->block_size;
 822         bank->write_end_alignment = stm32x_info->part_info->block_size;
 823
 824         /* setup sectors */
 825         bank->num_sectors = flash_size_in_kb / stm32x_info->part_info->page_size_kb;
 826         assert(bank->num_sectors > 0);
 827
 828         if (bank->sectors)
 829                 free(bank->sectors);
 830
 831         bank->sectors = alloc_block_array(0, stm32x_info->part_info->page_size_kb * 1024,
 832                         bank->num_sectors);
 833
 834         if (bank->sectors == NULL) {
 835                 LOG_ERROR("failed to allocate bank sectors");
 836                 return ERROR_FAIL;
 837         }
 838
 839         /* setup protection blocks */
 840         const uint32_t wpsn = stm32x_info->part_info->wps_group_size;
 841         assert(bank->num_sectors % wpsn == 0);
 842
 843         bank->num_prot_blocks = bank->num_sectors / wpsn;
 844         assert(bank->num_prot_blocks > 0);
 845
 846         if (bank->prot_blocks)
 847                 free(bank->prot_blocks);
 848
 849         bank->prot_blocks = alloc_block_array(0, stm32x_info->part_info->page_size_kb * wpsn * 1024,
 850                         bank->num_prot_blocks);
 851
 852         if (bank->prot_blocks == NULL) {
 853                 LOG_ERROR("failed to allocate bank prot_block");
 854                 return ERROR_FAIL;
 855         }
 856
 857         stm32x_info->probed = 1;
 858         return ERROR_OK;
 859 }
 860
 861 static int stm32x_auto_probe(struct flash_bank *bank)
 862 {
 863         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 864
 865         if (stm32x_info->probed)
 866                 return ERROR_OK;
 867
 868         return stm32x_probe(bank);
 869 }
 870
 871 /* This method must return a string displaying information about the bank */
 872 static int stm32x_get_info(struct flash_bank *bank, char *buf, int buf_size)
 873 {
 874         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 875         const struct stm32h7x_part_info *info = stm32x_info->part_info;
 876
 877         if (!stm32x_info->probed) {
 878                 int retval = stm32x_probe(bank);
 879                 if (retval != ERROR_OK) {
 880                         snprintf(buf, buf_size, "Unable to find bank information.");
 881                         return retval;
 882                 }
 883         }
 884
 885         if (info) {
 886                 const char *rev_str = NULL;
 887                 uint16_t rev_id = stm32x_info->idcode >> 16;
 888
 889                 for (unsigned int i = 0; i < info->num_revs; i++)
 890                         if (rev_id == info->revs[i].rev)
 891                                 rev_str = info->revs[i].str;
 892
 893                 if (rev_str != NULL) {
 894                         snprintf(buf, buf_size, "%s - Rev: %s",
 895                                 stm32x_info->part_info->device_str, rev_str);
 896                 } else {
 897                         snprintf(buf, buf_size,
 898                                  "%s - Rev: unknown (0x%04x)",
 899                                 stm32x_info->part_info->device_str, rev_id);
 900                 }
 901         } else {
 902           snprintf(buf, buf_size, "Cannot identify target as a STM32H7x");
 903           return ERROR_FAIL;
 904         }
 905         return ERROR_OK;
 906 }
 907
 908 static int stm32x_set_rdp(struct flash_bank *bank, enum stm32h7x_opt_rdp new_rdp)
 909 {
 910         struct target *target = bank->target;
 911         uint32_t optsr, cur_rdp;
 912         int retval;
 913
 914         if (target->state != TARGET_HALTED) {
 915                 LOG_ERROR("Target not halted");
 916                 return ERROR_TARGET_NOT_HALTED;
 917         }
 918
 919         retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_PRG, &optsr);
 920
 921         if (retval != ERROR_OK) {
 922                 LOG_DEBUG("unable to read FLASH_OPTSR_PRG register");
 923                 return retval;
 924         }
 925
 926         /* get current RDP, and check if there is a change */
 927         cur_rdp = (optsr & OPT_RDP_MASK) >> OPT_RDP_POS;
 928         if (new_rdp == cur_rdp) {
 929                 LOG_INFO("the requested RDP value is already programmed");
 930                 return ERROR_OK;
 931         }
 932
 933         switch (new_rdp) {
 934         case OPT_RDP_L0:
 935                 LOG_WARNING("unlocking the entire flash device");
 936                 break;
 937         case OPT_RDP_L1:
 938                 LOG_WARNING("locking the entire flash device");
 939                 break;
 940         case OPT_RDP_L2:
 941                 LOG_WARNING("locking the entire flash device, irreversible");
 942                 break;
 943         }
 944
 945         /* apply new RDP */
 946         optsr = (optsr & ~OPT_RDP_MASK) | (new_rdp << OPT_RDP_POS);
 947
 948         /* apply new option value */
 949         return stm32x_write_option(bank, FLASH_OPTSR_PRG, optsr);
 950 }
 951
 952 COMMAND_HANDLER(stm32x_handle_lock_command)
 953 {
 954         if (CMD_ARGC < 1)
 955                 return ERROR_COMMAND_SYNTAX_ERROR;
 956
 957         struct flash_bank *bank;
 958         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 959         if (ERROR_OK != retval)
 960                 return retval;
 961
 962         retval = stm32x_set_rdp(bank, OPT_RDP_L1);
 963
 964         if (retval != ERROR_OK)
 965                 command_print(CMD, "%s failed to lock device", bank->driver->name);
 966         else
 967                 command_print(CMD, "%s locked", bank->driver->name);
 968
 969         return retval;
 970 }
 971
 972 COMMAND_HANDLER(stm32x_handle_unlock_command)
 973 {
 974         if (CMD_ARGC < 1)
 975                 return ERROR_COMMAND_SYNTAX_ERROR;
 976
 977         struct flash_bank *bank;
 978         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 979         if (ERROR_OK != retval)
 980                 return retval;
 981
 982         retval = stm32x_set_rdp(bank, OPT_RDP_L0);
 983
 984         if (retval != ERROR_OK)
 985                 command_print(CMD, "%s failed to unlock device", bank->driver->name);
 986         else
 987                 command_print(CMD, "%s unlocked", bank->driver->name);
 988
 989         return retval;
 990 }
 991
 992 static int stm32x_mass_erase(struct flash_bank *bank)
 993 {
 994         int retval, retval2;
 995         struct target *target = bank->target;
 996         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 997
 998         if (target->state != TARGET_HALTED) {
 999                 LOG_ERROR("Target not halted");
1000                 return ERROR_TARGET_NOT_HALTED;
1001         }
1002
1003         retval = stm32x_unlock_reg(bank);
1004         if (retval != ERROR_OK)
1005                 goto flash_lock;
1006
1007         /* mass erase flash memory bank */
1008         retval = stm32x_write_flash_reg(bank, FLASH_CR,
1009                         stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64, 0));
1010         if (retval != ERROR_OK)
1011                 goto flash_lock;
1012
1013         retval = stm32x_write_flash_reg(bank, FLASH_CR,
1014                         stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64 | FLASH_START, 0));
1015         if (retval != ERROR_OK)
1016                 goto flash_lock;
1017
1018         retval = stm32x_wait_flash_op_queue(bank, 30000);
1019         if (retval != ERROR_OK)
1020                 goto flash_lock;
1021
1022 flash_lock:
1023         retval2 = stm32x_lock_reg(bank);
1024         if (retval2 != ERROR_OK)
1025                 LOG_ERROR("error during the lock of flash");
1026
1027         return (retval == ERROR_OK) ? retval2 : retval;
1028 }
1029
1030 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1031 {
1032         if (CMD_ARGC < 1) {
1033                 command_print(CMD, "stm32h7x mass_erase <bank>");
1034                 return ERROR_COMMAND_SYNTAX_ERROR;
1035         }
1036
1037         struct flash_bank *bank;
1038         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1039         if (ERROR_OK != retval)
1040                 return retval;
1041
1042         retval = stm32x_mass_erase(bank);
1043         if (retval == ERROR_OK) {
1044                 /* set all sectors as erased */
1045                 for (int i = 0; i < bank->num_sectors; i++)
1046                         bank->sectors[i].is_erased = 1;
1047
1048                 command_print(CMD, "stm32h7x mass erase complete");
1049         } else {
1050                 command_print(CMD, "stm32h7x mass erase failed");
1051         }
1052
1053         return retval;
1054 }
1055
1056 COMMAND_HANDLER(stm32x_handle_option_read_command)
1057 {
1058         if (CMD_ARGC < 2) {
1059                 command_print(CMD, "stm32h7x option_read <bank> <option_reg offset>");
1060                 return ERROR_COMMAND_SYNTAX_ERROR;
1061         }
1062
1063         struct flash_bank *bank;
1064         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1065         if (ERROR_OK != retval)
1066                 return retval;
1067
1068         uint32_t reg_offset, value;
1069
1070         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1071         retval = stm32x_read_flash_reg(bank, reg_offset, &value);
1072         if (ERROR_OK != retval)
1073                 return retval;
1074
1075         command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "",
1076                         stm32x_get_flash_reg(bank, reg_offset), value);
1077
1078         return retval;
1079 }
1080
1081 COMMAND_HANDLER(stm32x_handle_option_write_command)
1082 {
1083         if (CMD_ARGC < 3) {
1084                 command_print(CMD, "stm32h7x option_write <bank> <option_reg offset> <value> [mask]");
1085                 return ERROR_COMMAND_SYNTAX_ERROR;
1086         }
1087
1088         struct flash_bank *bank;
1089         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1090         if (ERROR_OK != retval)
1091                 return retval;
1092
1093         uint32_t reg_offset, value, mask = 0xffffffff;
1094
1095         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1096         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1097         if (CMD_ARGC > 3)
1098                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
1099
1100         return stm32x_modify_option(bank, reg_offset, value, mask);
1101 }
1102
1103 static const struct command_registration stm32x_exec_command_handlers[] = {
1104         {
1105                 .name = "lock",
1106                 .handler = stm32x_handle_lock_command,
1107                 .mode = COMMAND_EXEC,
1108                 .usage = "bank_id",
1109                 .help = "Lock entire flash device.",
1110         },
1111         {
1112                 .name = "unlock",
1113                 .handler = stm32x_handle_unlock_command,
1114                 .mode = COMMAND_EXEC,
1115                 .usage = "bank_id",
1116                 .help = "Unlock entire protected flash device.",
1117         },
1118         {
1119                 .name = "mass_erase",
1120                 .handler = stm32x_handle_mass_erase_command,
1121                 .mode = COMMAND_EXEC,
1122                 .usage = "bank_id",
1123                 .help = "Erase entire flash device.",
1124         },
1125         {
1126                 .name = "option_read",
1127                 .handler = stm32x_handle_option_read_command,
1128                 .mode = COMMAND_EXEC,
1129                 .usage = "bank_id reg_offset",
1130                 .help = "Read and display device option bytes.",
1131         },
1132         {
1133                 .name = "option_write",
1134                 .handler = stm32x_handle_option_write_command,
1135                 .mode = COMMAND_EXEC,
1136                 .usage = "bank_id reg_offset value [mask]",
1137                 .help = "Write device option bit fields with provided value.",
1138         },
1139         COMMAND_REGISTRATION_DONE
1140 };
1141
1142 static const struct command_registration stm32x_command_handlers[] = {
1143         {
1144                 .name = "stm32h7x",
1145                 .mode = COMMAND_ANY,
1146                 .help = "stm32h7x flash command group",
1147                 .usage = "",
1148                 .chain = stm32x_exec_command_handlers,
1149         },
1150         COMMAND_REGISTRATION_DONE
1151 };
1152
1153 const struct flash_driver stm32h7x_flash = {
1154         .name = "stm32h7x",
1155         .commands = stm32x_command_handlers,
1156         .flash_bank_command = stm32x_flash_bank_command,
1157         .erase = stm32x_erase,
1158         .protect = stm32x_protect,
1159         .write = stm32x_write,
1160         .read = default_flash_read,
1161         .probe = stm32x_probe,
1162         .auto_probe = stm32x_auto_probe,
1163         .erase_check = default_flash_blank_check,
1164         .protect_check = stm32x_protect_check,
1165         .info = stm32x_get_info,
1166         .free_driver_priv = default_flash_free_driver_priv,
1167 };