1 /***************************************************************************
2 * Copyright (C) 2017 by STMicroelectronics *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
22 #include <helper/binarybuffer.h>
23 #include <target/algorithm.h>
24 #include <target/armv7m.h>
27 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
28 #define FLASH_ERASE_TIMEOUT 10000
29 #define FLASH_WRITE_TIMEOUT 5
32 /* Same Flash registers for both banks, */
33 /* access depends on Flash Base address */
34 #define FLASH_ACR 0x00
35 #define FLASH_KEYR 0x04
36 #define FLASH_OPTKEYR 0x08
39 #define FLASH_CCR 0x14
40 #define FLASH_OPTCR 0x18
41 #define FLASH_OPTSR_CUR 0x1C
42 #define FLASH_OPTSR_PRG 0x20
43 #define FLASH_OPTCCR 0x24
44 #define FLASH_WPSN_CUR 0x38
45 #define FLASH_WPSN_PRG 0x3C
48 /* FLASH_CR register bits */
49 #define FLASH_LOCK (1 << 0)
50 #define FLASH_PG (1 << 1)
51 #define FLASH_SER (1 << 2)
52 #define FLASH_BER (1 << 3)
53 #define FLASH_PSIZE_8 (0 << 4)
54 #define FLASH_PSIZE_16 (1 << 4)
55 #define FLASH_PSIZE_32 (2 << 4)
56 #define FLASH_PSIZE_64 (3 << 4)
57 #define FLASH_FW (1 << 6)
58 #define FLASH_START (1 << 7)
60 #define FLASH_SNB(a) ((a) << 8)
62 /* FLASH_SR register bits */
63 #define FLASH_BSY (1 << 0) /* Operation in progress */
64 #define FLASH_QW (1 << 2) /* Operation queue in progress */
65 #define FLASH_WRPERR (1 << 17) /* Write protection error */
66 #define FLASH_PGSERR (1 << 18) /* Programming sequence error */
67 #define FLASH_STRBERR (1 << 19) /* Strobe error */
68 #define FLASH_INCERR (1 << 21) /* Inconsistency error */
69 #define FLASH_OPERR (1 << 22) /* Operation error */
70 #define FLASH_RDPERR (1 << 23) /* Read Protection error */
71 #define FLASH_RDSERR (1 << 24) /* Secure Protection error */
72 #define FLASH_SNECCERR (1 << 25) /* Single ECC error */
73 #define FLASH_DBECCERR (1 << 26) /* Double ECC error */
75 #define FLASH_ERROR (FLASH_WRPERR | FLASH_PGSERR | FLASH_STRBERR | FLASH_INCERR | FLASH_OPERR | \
76 FLASH_RDPERR | FLASH_RDSERR | FLASH_SNECCERR | FLASH_DBECCERR)
78 /* FLASH_OPTCR register bits */
79 #define OPT_LOCK (1 << 0)
80 #define OPT_START (1 << 1)
82 /* FLASH_OPTSR register bits */
83 #define OPT_BSY (1 << 0)
85 #define OPT_RDP_MASK (0xff << OPT_RDP_POS)
87 /* FLASH_OPTCCR register bits */
88 #define OPT_CLR_OPTCHANGEERR (1 << 30)
90 /* register unlock keys */
91 #define KEY1 0x45670123
92 #define KEY2 0xCDEF89AB
94 /* option register unlock key */
95 #define OPTKEY1 0x08192A3B
96 #define OPTKEY2 0x4C5D6E7F
98 #define DBGMCU_IDCODE_REGISTER 0x5C001000
99 #define FLASH_BANK0_ADDRESS 0x08000000
100 #define FLASH_BANK1_ADDRESS 0x08100000
101 #define FLASH_REG_BASE_B0 0x52002000
102 #define FLASH_REG_BASE_B1 0x52002100
103 #define FLASH_SIZE_ADDRESS 0x1FF1E880
104 #define FLASH_BLOCK_SIZE 32
106 struct stm32h7x_rev {
111 struct stm32h7x_part_info {
113 const char *device_str;
114 const struct stm32h7x_rev *revs;
116 unsigned int page_size;
117 uint16_t max_flash_size_kb;
118 uint8_t has_dual_bank;
119 uint16_t first_bank_size_kb; /* Used when has_dual_bank is true */
120 uint32_t flash_base; /* Flash controller registers location */
121 uint32_t fsize_base; /* Location of FSIZE register */
124 struct stm32h7x_flash_bank {
127 uint32_t user_bank_size;
128 uint32_t flash_base; /* Address of flash reg controller */
129 const struct stm32h7x_part_info *part_info;
132 enum stm32h7x_opt_rdp {
138 static const struct stm32h7x_rev stm32_450_revs[] = {
139 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X" },
142 static const struct stm32h7x_part_info stm32h7x_parts[] = {
145 .revs = stm32_450_revs,
146 .num_revs = ARRAY_SIZE(stm32_450_revs),
147 .device_str = "STM32H74x/75x",
148 .page_size = 128, /* 128 KB */
149 .max_flash_size_kb = 2048,
150 .first_bank_size_kb = 1024,
152 .flash_base = FLASH_REG_BASE_B0,
153 .fsize_base = FLASH_SIZE_ADDRESS,
157 /* flash bank stm32x <base> <size> 0 0 <target#> */
159 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
161 struct stm32h7x_flash_bank *stm32x_info;
164 return ERROR_COMMAND_SYNTAX_ERROR;
166 stm32x_info = malloc(sizeof(struct stm32h7x_flash_bank));
167 bank->driver_priv = stm32x_info;
169 stm32x_info->probed = 0;
170 stm32x_info->user_bank_size = bank->size;
175 static inline uint32_t stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
177 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
178 return reg_offset + stm32x_info->flash_base;
181 static inline int stm32x_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
183 return target_read_u32(bank->target, stm32x_get_flash_reg(bank, reg_offset), value);
186 static inline int stm32x_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
188 return target_write_u32(bank->target, stm32x_get_flash_reg(bank, reg_offset), value);
191 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
193 return stm32x_read_flash_reg(bank, FLASH_SR, status);
196 static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
198 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
202 /* wait for flash operations completion */
204 retval = stm32x_get_flash_status(bank, &status);
205 if (retval != ERROR_OK) {
206 LOG_INFO("wait_flash_op_queue, target_read_u32 : error : remote address 0x%x", stm32x_info->flash_base);
210 if ((status & FLASH_QW) == 0)
213 if (timeout-- <= 0) {
214 LOG_INFO("wait_flash_op_queue, time out expired, status: 0x%" PRIx32 "", status);
220 if (status & FLASH_WRPERR) {
221 LOG_INFO("wait_flash_op_queue, WRPERR : error : remote address 0x%x", stm32x_info->flash_base);
225 /* Clear error + EOP flags but report errors */
226 if (status & FLASH_ERROR) {
227 if (retval == ERROR_OK)
229 /* If this operation fails, we ignore it and report the original retval */
230 stm32x_write_flash_reg(bank, FLASH_CCR, status);
235 static int stm32x_unlock_reg(struct flash_bank *bank)
239 /* first check if not already unlocked
240 * otherwise writing on FLASH_KEYR will fail
242 int retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
243 if (retval != ERROR_OK)
246 if ((ctrl & FLASH_LOCK) == 0)
249 /* unlock flash registers for bank */
250 retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY1);
251 if (retval != ERROR_OK)
254 retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY2);
255 if (retval != ERROR_OK)
258 retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
259 if (retval != ERROR_OK)
262 if (ctrl & FLASH_LOCK) {
263 LOG_ERROR("flash not unlocked STM32_FLASH_CRx: %" PRIx32, ctrl);
264 return ERROR_TARGET_FAILURE;
269 static int stm32x_unlock_option_reg(struct flash_bank *bank)
273 int retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
274 if (retval != ERROR_OK)
277 if ((ctrl & OPT_LOCK) == 0)
280 /* unlock option registers */
281 retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY1);
282 if (retval != ERROR_OK)
285 retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY2);
286 if (retval != ERROR_OK)
289 retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
290 if (retval != ERROR_OK)
293 if (ctrl & OPT_LOCK) {
294 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
295 return ERROR_TARGET_FAILURE;
301 static inline int stm32x_lock_reg(struct flash_bank *bank)
303 return stm32x_write_flash_reg(bank, FLASH_CR, FLASH_LOCK);
306 static inline int stm32x_lock_option_reg(struct flash_bank *bank)
308 return stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_LOCK);
311 static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
315 /* unlock option bytes for modification */
316 retval = stm32x_unlock_option_reg(bank);
317 if (retval != ERROR_OK)
318 goto flash_options_lock;
320 /* write option bytes */
321 retval = stm32x_write_flash_reg(bank, reg_offset, value);
322 if (retval != ERROR_OK)
323 goto flash_options_lock;
325 /* Remove OPT error flag before programming */
326 retval = stm32x_write_flash_reg(bank, FLASH_OPTCCR, OPT_CLR_OPTCHANGEERR);
327 if (retval != ERROR_OK)
328 goto flash_options_lock;
330 /* start programming cycle */
331 retval = stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_START);
332 if (retval != ERROR_OK)
333 goto flash_options_lock;
335 /* wait for completion */
336 int timeout = FLASH_ERASE_TIMEOUT;
339 retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_CUR, &status);
340 if (retval != ERROR_OK) {
341 LOG_INFO("stm32x_options_program: failed to read FLASH_OPTSR_CUR");
342 goto flash_options_lock;
344 if ((status & OPT_BSY) == 0)
347 if (timeout-- <= 0) {
348 LOG_INFO("waiting for OBL launch, time out expired, OPTSR: 0x%" PRIx32 "", status);
350 goto flash_options_lock;
356 retval2 = stm32x_lock_option_reg(bank);
357 if (retval2 != ERROR_OK)
358 LOG_ERROR("error during the lock of flash options");
360 return (retval == ERROR_OK) ? retval2 : retval;
363 static int stm32x_modify_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
367 int retval = stm32x_read_flash_reg(bank, reg_offset, &data);
368 if (retval != ERROR_OK)
371 data = (data & ~mask) | (value & mask);
373 return stm32x_write_option(bank, reg_offset, data);
376 static int stm32x_protect_check(struct flash_bank *bank)
380 /* read 'write protection' settings */
381 int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
382 if (retval != ERROR_OK) {
383 LOG_DEBUG("unable to read WPSN_CUR register");
387 for (int i = 0; i < bank->num_sectors; i++) {
388 bank->sectors[i].is_protected = protection & (1 << i) ? 0 : 1;
393 static int stm32x_erase(struct flash_bank *bank, int first, int last)
397 assert(first < bank->num_sectors);
398 assert(last < bank->num_sectors);
400 if (bank->target->state != TARGET_HALTED)
401 return ERROR_TARGET_NOT_HALTED;
403 retval = stm32x_unlock_reg(bank);
404 if (retval != ERROR_OK)
409 To erase a sector, follow the procedure below:
410 1. Check that no Flash memory operation is ongoing by checking the QW bit in the
412 2. Set the SER bit and select the sector
413 you wish to erase (SNB) in the FLASH_CR register
414 3. Set the STRT bit in the FLASH_CR register
415 4. Wait for flash operations completion
417 for (int i = first; i <= last; i++) {
418 LOG_DEBUG("erase sector %d", i);
419 retval = stm32x_write_flash_reg(bank, FLASH_CR,
420 FLASH_SER | FLASH_SNB(i) | FLASH_PSIZE_64);
421 if (retval != ERROR_OK) {
422 LOG_ERROR("Error erase sector %d", i);
425 retval = stm32x_write_flash_reg(bank, FLASH_CR,
426 FLASH_SER | FLASH_SNB(i) | FLASH_PSIZE_64 | FLASH_START);
427 if (retval != ERROR_OK) {
428 LOG_ERROR("Error erase sector %d", i);
431 retval = stm32x_wait_flash_op_queue(bank, FLASH_ERASE_TIMEOUT);
433 if (retval != ERROR_OK) {
434 LOG_ERROR("erase time-out or operation error sector %d", i);
437 bank->sectors[i].is_erased = 1;
441 retval2 = stm32x_lock_reg(bank);
442 if (retval2 != ERROR_OK)
443 LOG_ERROR("error during the lock of flash");
445 return (retval == ERROR_OK) ? retval2 : retval;
448 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
450 struct target *target = bank->target;
453 if (target->state != TARGET_HALTED) {
454 LOG_ERROR("Target not halted");
455 return ERROR_TARGET_NOT_HALTED;
458 /* read 'write protection' settings */
459 int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
460 if (retval != ERROR_OK) {
461 LOG_DEBUG("unable to read WPSN_CUR register");
465 for (int i = first; i <= last; i++) {
467 protection &= ~(1 << i);
469 protection |= (1 << i);
472 /* apply WRPSN mask */
475 LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%x", protection);
477 /* apply new option value */
478 return stm32x_write_option(bank, FLASH_WPSN_PRG, protection);
481 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
482 uint32_t offset, uint32_t count)
484 struct target *target = bank->target;
486 * If the size of the data part of the buffer is not a multiple of FLASH_BLOCK_SIZE, we get
487 * "corrupted fifo read" pointer in target_run_flash_async_algorithm()
489 uint32_t data_size = 512 * FLASH_BLOCK_SIZE; /* 16384 */
490 uint32_t buffer_size = 8 + data_size;
491 struct working_area *write_algorithm;
492 struct working_area *source;
493 uint32_t address = bank->base + offset;
494 struct reg_param reg_params[5];
495 struct armv7m_algorithm armv7m_info;
496 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
497 int retval = ERROR_OK;
499 static const uint8_t stm32x_flash_write_code[] = {
500 #include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
503 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
504 &write_algorithm) != ERROR_OK) {
505 LOG_WARNING("no working area available, can't do block memory writes");
506 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
509 retval = target_write_buffer(target, write_algorithm->address,
510 sizeof(stm32x_flash_write_code),
511 stm32x_flash_write_code);
512 if (retval != ERROR_OK) {
513 target_free_working_area(target, write_algorithm);
518 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
520 buffer_size = 8 + data_size;
521 if (data_size <= 256) {
522 /* we already allocated the writing code, but failed to get a
523 * buffer, free the algorithm */
524 target_free_working_area(target, write_algorithm);
526 LOG_WARNING("no large enough working area available, can't do block memory writes");
527 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
531 LOG_DEBUG("target_alloc_working_area_try : buffer_size -> 0x%x", buffer_size);
533 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
534 armv7m_info.core_mode = ARM_MODE_THREAD;
536 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
537 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
538 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
539 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (word-256 bits) */
540 init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash reg base */
542 buf_set_u32(reg_params[0].value, 0, 32, source->address);
543 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
544 buf_set_u32(reg_params[2].value, 0, 32, address);
545 buf_set_u32(reg_params[3].value, 0, 32, count);
546 buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->flash_base);
548 retval = target_run_flash_async_algorithm(target,
554 source->address, source->size,
555 write_algorithm->address, 0,
558 if (retval == ERROR_FLASH_OPERATION_FAILED) {
559 LOG_INFO("error executing stm32h7x flash write algorithm");
561 uint32_t flash_sr = buf_get_u32(reg_params[0].value, 0, 32);
563 if (flash_sr & FLASH_WRPERR)
564 LOG_ERROR("flash memory write protected");
566 if ((flash_sr & FLASH_ERROR) != 0) {
567 LOG_ERROR("flash write failed, FLASH_SR = %08" PRIx32, flash_sr);
568 /* Clear error + EOP flags but report errors */
569 stm32x_write_flash_reg(bank, FLASH_CCR, flash_sr);
574 target_free_working_area(target, source);
575 target_free_working_area(target, write_algorithm);
577 destroy_reg_param(®_params[0]);
578 destroy_reg_param(®_params[1]);
579 destroy_reg_param(®_params[2]);
580 destroy_reg_param(®_params[3]);
581 destroy_reg_param(®_params[4]);
585 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
586 uint32_t offset, uint32_t count)
588 struct target *target = bank->target;
589 uint32_t address = bank->base + offset;
592 if (bank->target->state != TARGET_HALTED) {
593 LOG_ERROR("Target not halted");
594 return ERROR_TARGET_NOT_HALTED;
597 if (offset % FLASH_BLOCK_SIZE) {
598 LOG_WARNING("offset 0x%" PRIx32 " breaks required 32-byte alignment", offset);
599 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
602 retval = stm32x_unlock_reg(bank);
603 if (retval != ERROR_OK)
606 uint32_t blocks_remaining = count / FLASH_BLOCK_SIZE;
607 uint32_t bytes_remaining = count % FLASH_BLOCK_SIZE;
609 /* multiple words (32-bytes) to be programmed in block */
610 if (blocks_remaining) {
611 retval = stm32x_write_block(bank, buffer, offset, blocks_remaining);
612 if (retval != ERROR_OK) {
613 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
614 /* if block write failed (no sufficient working area),
615 * we use normal (slow) dword accesses */
616 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
619 buffer += blocks_remaining * FLASH_BLOCK_SIZE;
620 address += blocks_remaining * FLASH_BLOCK_SIZE;
621 blocks_remaining = 0;
623 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
629 The Flash memory programming sequence is as follows:
630 1. Check that no main Flash memory operation is ongoing by checking the QW bit in the
632 2. Set the PG bit in the FLASH_CR register
633 3. 8 x Word access (or Force Write FW)
634 4. Wait for flash operations completion
636 while (blocks_remaining > 0) {
637 retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_PG | FLASH_PSIZE_64);
638 if (retval != ERROR_OK)
641 retval = target_write_buffer(target, address, FLASH_BLOCK_SIZE, buffer);
642 if (retval != ERROR_OK)
645 retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
646 if (retval != ERROR_OK)
649 buffer += FLASH_BLOCK_SIZE;
650 address += FLASH_BLOCK_SIZE;
654 if (bytes_remaining) {
655 retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_PG | FLASH_PSIZE_64);
656 if (retval != ERROR_OK)
659 retval = target_write_buffer(target, address, bytes_remaining, buffer);
660 if (retval != ERROR_OK)
663 /* Force Write buffer of FLASH_BLOCK_SIZE = 32 bytes */
664 retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_PG | FLASH_PSIZE_64 | FLASH_FW);
665 if (retval != ERROR_OK)
668 retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
669 if (retval != ERROR_OK)
674 retval2 = stm32x_lock_reg(bank);
675 if (retval2 != ERROR_OK)
676 LOG_ERROR("error during the lock of flash");
678 return (retval == ERROR_OK) ? retval2 : retval;
681 static void setup_sector(struct flash_bank *bank, int start, int num, int size)
683 for (int i = start; i < (start + num) ; i++) {
684 assert(i < bank->num_sectors);
685 bank->sectors[i].offset = bank->size;
686 bank->sectors[i].size = size;
687 bank->size += bank->sectors[i].size;
691 static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
693 /* read stm32 device id register */
694 int retval = target_read_u32(bank->target, DBGMCU_IDCODE_REGISTER, id);
695 if (retval != ERROR_OK)
700 static int stm32x_probe(struct flash_bank *bank)
702 struct target *target = bank->target;
703 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
705 uint16_t flash_size_in_kb;
707 uint32_t base_address = FLASH_BANK0_ADDRESS;
708 uint32_t second_bank_base;
710 stm32x_info->probed = 0;
711 stm32x_info->part_info = NULL;
713 int retval = stm32x_read_id_code(bank, &stm32x_info->idcode);
714 if (retval != ERROR_OK)
717 LOG_DEBUG("device id = 0x%08" PRIx32 "", stm32x_info->idcode);
719 device_id = stm32x_info->idcode & 0xfff;
721 for (unsigned int n = 0; n < ARRAY_SIZE(stm32h7x_parts); n++) {
722 if (device_id == stm32h7x_parts[n].id)
723 stm32x_info->part_info = &stm32h7x_parts[n];
725 if (!stm32x_info->part_info) {
726 LOG_WARNING("Cannot identify target as a STM32H7xx family.");
729 LOG_INFO("Device: %s", stm32x_info->part_info->device_str);
732 /* update the address of controller from data base */
733 stm32x_info->flash_base = stm32x_info->part_info->flash_base;
735 /* get flash size from target */
736 retval = target_read_u16(target, stm32x_info->part_info->fsize_base, &flash_size_in_kb);
737 if (retval != ERROR_OK) {
738 /* read error when device has invalid value, set max flash size */
739 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
741 LOG_INFO("flash size probed value %d", flash_size_in_kb);
743 /* Lower flash size devices are single bank */
744 if (stm32x_info->part_info->has_dual_bank && (flash_size_in_kb > stm32x_info->part_info->first_bank_size_kb)) {
745 /* Use the configured base address to determine if this is the first or second flash bank.
746 * Verify that the base address is reasonably correct and determine the flash bank size
748 second_bank_base = base_address + stm32x_info->part_info->first_bank_size_kb * 1024;
749 if (bank->base == second_bank_base) {
750 /* This is the second bank */
751 base_address = second_bank_base;
752 flash_size_in_kb = flash_size_in_kb - stm32x_info->part_info->first_bank_size_kb;
753 /* bank1 also uses a register offset */
754 stm32x_info->flash_base = FLASH_REG_BASE_B1;
755 } else if (bank->base == base_address) {
756 /* This is the first bank */
757 flash_size_in_kb = stm32x_info->part_info->first_bank_size_kb;
759 LOG_WARNING("STM32H flash bank base address config is incorrect. "
760 TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
761 bank->base, base_address, second_bank_base);
764 LOG_INFO("STM32H flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32,
765 bank->bank_number, flash_size_in_kb, base_address);
767 LOG_INFO("STM32H flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
770 /* if the user sets the size manually then ignore the probed value
771 * this allows us to work around devices that have an invalid flash size register value */
772 if (stm32x_info->user_bank_size) {
773 LOG_INFO("ignoring flash probed value, using configured bank size");
774 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
775 } else if (flash_size_in_kb == 0xffff) {
777 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
780 /* did we assign flash size? */
781 assert(flash_size_in_kb != 0xffff);
783 /* calculate numbers of pages */
784 int num_pages = flash_size_in_kb / stm32x_info->part_info->page_size;
786 /* check that calculation result makes sense */
787 assert(num_pages > 0);
791 bank->sectors = NULL;
794 bank->base = base_address;
795 bank->num_sectors = num_pages;
796 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
797 if (bank->sectors == NULL) {
798 LOG_ERROR("failed to allocate bank sectors");
804 setup_sector(bank, 0, num_pages, stm32x_info->part_info->page_size * 1024);
806 for (i = 0; i < num_pages; i++) {
807 bank->sectors[i].is_erased = -1;
808 bank->sectors[i].is_protected = 0;
811 stm32x_info->probed = 1;
815 static int stm32x_auto_probe(struct flash_bank *bank)
817 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
819 if (stm32x_info->probed)
822 return stm32x_probe(bank);
825 /* This method must return a string displaying information about the bank */
826 static int stm32x_get_info(struct flash_bank *bank, char *buf, int buf_size)
828 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
829 const struct stm32h7x_part_info *info = stm32x_info->part_info;
831 if (!stm32x_info->probed) {
832 int retval = stm32x_probe(bank);
833 if (retval != ERROR_OK) {
834 snprintf(buf, buf_size, "Unable to find bank information.");
840 const char *rev_str = NULL;
841 uint16_t rev_id = stm32x_info->idcode >> 16;
843 for (unsigned int i = 0; i < info->num_revs; i++)
844 if (rev_id == info->revs[i].rev)
845 rev_str = info->revs[i].str;
847 if (rev_str != NULL) {
848 snprintf(buf, buf_size, "%s - Rev: %s",
849 stm32x_info->part_info->device_str, rev_str);
851 snprintf(buf, buf_size,
852 "%s - Rev: unknown (0x%04x)",
853 stm32x_info->part_info->device_str, rev_id);
856 snprintf(buf, buf_size, "Cannot identify target as a STM32H7x");
862 static int stm32x_set_rdp(struct flash_bank *bank, enum stm32h7x_opt_rdp new_rdp)
864 struct target *target = bank->target;
865 uint32_t optsr, cur_rdp;
868 if (target->state != TARGET_HALTED) {
869 LOG_ERROR("Target not halted");
870 return ERROR_TARGET_NOT_HALTED;
873 retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_PRG, &optsr);
875 if (retval != ERROR_OK) {
876 LOG_DEBUG("unable to read FLASH_OPTSR_PRG register");
880 /* get current RDP, and check if there is a change */
881 cur_rdp = (optsr & OPT_RDP_MASK) >> OPT_RDP_POS;
882 if (new_rdp == cur_rdp) {
883 LOG_INFO("the requested RDP value is already programmed");
889 LOG_WARNING("unlocking the entire flash device");
892 LOG_WARNING("locking the entire flash device");
895 LOG_WARNING("locking the entire flash device, irreversible");
900 optsr = (optsr & ~OPT_RDP_MASK) | (new_rdp << OPT_RDP_POS);
902 /* apply new option value */
903 return stm32x_write_option(bank, FLASH_OPTSR_PRG, optsr);
906 COMMAND_HANDLER(stm32x_handle_lock_command)
909 return ERROR_COMMAND_SYNTAX_ERROR;
911 struct flash_bank *bank;
912 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
913 if (ERROR_OK != retval)
916 retval = stm32x_set_rdp(bank, OPT_RDP_L1);
918 if (retval != ERROR_OK)
919 command_print(CMD, "%s failed to lock device", bank->driver->name);
921 command_print(CMD, "%s locked", bank->driver->name);
926 COMMAND_HANDLER(stm32x_handle_unlock_command)
929 return ERROR_COMMAND_SYNTAX_ERROR;
931 struct flash_bank *bank;
932 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
933 if (ERROR_OK != retval)
936 retval = stm32x_set_rdp(bank, OPT_RDP_L0);
938 if (retval != ERROR_OK)
939 command_print(CMD, "%s failed to unlock device", bank->driver->name);
941 command_print(CMD, "%s unlocked", bank->driver->name);
946 static int stm32x_mass_erase(struct flash_bank *bank)
949 struct target *target = bank->target;
951 if (target->state != TARGET_HALTED) {
952 LOG_ERROR("Target not halted");
953 return ERROR_TARGET_NOT_HALTED;
956 retval = stm32x_unlock_reg(bank);
957 if (retval != ERROR_OK)
960 /* mass erase flash memory bank */
961 retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_BER | FLASH_PSIZE_64);
962 if (retval != ERROR_OK)
965 retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_BER | FLASH_PSIZE_64 | FLASH_START);
966 if (retval != ERROR_OK)
969 retval = stm32x_wait_flash_op_queue(bank, 30000);
970 if (retval != ERROR_OK)
974 retval2 = stm32x_lock_reg(bank);
975 if (retval2 != ERROR_OK)
976 LOG_ERROR("error during the lock of flash");
978 return (retval == ERROR_OK) ? retval2 : retval;
981 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
986 command_print(CMD, "stm32h7x mass_erase <bank>");
987 return ERROR_COMMAND_SYNTAX_ERROR;
990 struct flash_bank *bank;
991 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
992 if (ERROR_OK != retval)
995 retval = stm32x_mass_erase(bank);
996 if (retval == ERROR_OK) {
997 /* set all sectors as erased */
998 for (i = 0; i < bank->num_sectors; i++)
999 bank->sectors[i].is_erased = 1;
1001 command_print(CMD, "stm32h7x mass erase complete");
1003 command_print(CMD, "stm32h7x mass erase failed");
1009 COMMAND_HANDLER(stm32x_handle_option_read_command)
1012 command_print(CMD, "stm32h7x option_read <bank> <option_reg offset>");
1013 return ERROR_COMMAND_SYNTAX_ERROR;
1016 struct flash_bank *bank;
1017 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1018 if (ERROR_OK != retval)
1021 uint32_t reg_offset, value;
1023 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1024 retval = stm32x_read_flash_reg(bank, reg_offset, &value);
1025 if (ERROR_OK != retval)
1028 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "",
1029 stm32x_get_flash_reg(bank, reg_offset), value);
1034 COMMAND_HANDLER(stm32x_handle_option_write_command)
1037 command_print(CMD, "stm32h7x option_write <bank> <option_reg offset> <value> [mask]");
1038 return ERROR_COMMAND_SYNTAX_ERROR;
1041 struct flash_bank *bank;
1042 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1043 if (ERROR_OK != retval)
1046 uint32_t reg_offset, value, mask = 0xffffffff;
1048 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1049 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1051 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], mask);
1053 return stm32x_modify_option(bank, reg_offset, value, mask);
1056 static const struct command_registration stm32x_exec_command_handlers[] = {
1059 .handler = stm32x_handle_lock_command,
1060 .mode = COMMAND_EXEC,
1062 .help = "Lock entire flash device.",
1066 .handler = stm32x_handle_unlock_command,
1067 .mode = COMMAND_EXEC,
1069 .help = "Unlock entire protected flash device.",
1072 .name = "mass_erase",
1073 .handler = stm32x_handle_mass_erase_command,
1074 .mode = COMMAND_EXEC,
1076 .help = "Erase entire flash device.",
1079 .name = "option_read",
1080 .handler = stm32x_handle_option_read_command,
1081 .mode = COMMAND_EXEC,
1082 .usage = "bank_id reg_offset",
1083 .help = "Read and display device option bytes.",
1086 .name = "option_write",
1087 .handler = stm32x_handle_option_write_command,
1088 .mode = COMMAND_EXEC,
1089 .usage = "bank_id reg_offset value [mask]",
1090 .help = "Write device option bit fields with provided value.",
1092 COMMAND_REGISTRATION_DONE
1095 static const struct command_registration stm32x_command_handlers[] = {
1098 .mode = COMMAND_ANY,
1099 .help = "stm32h7x flash command group",
1101 .chain = stm32x_exec_command_handlers,
1103 COMMAND_REGISTRATION_DONE
1106 const struct flash_driver stm32h7x_flash = {
1108 .commands = stm32x_command_handlers,
1109 .flash_bank_command = stm32x_flash_bank_command,
1110 .erase = stm32x_erase,
1111 .protect = stm32x_protect,
1112 .write = stm32x_write,
1113 .read = default_flash_read,
1114 .probe = stm32x_probe,
1115 .auto_probe = stm32x_auto_probe,
1116 .erase_check = default_flash_blank_check,
1117 .protect_check = stm32x_protect_check,
1118 .info = stm32x_get_info,
1119 .free_driver_priv = default_flash_free_driver_priv,