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   1 /***************************************************************************
   2  *   Copyright (C) 2017 by STMicroelectronics                              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  16  ***************************************************************************/
  17 #ifdef HAVE_CONFIG_H
  18 #include "config.h"
  19 #endif
  20
  21 #include "imp.h"
  22 #include <helper/binarybuffer.h>
  23 #include <target/algorithm.h>
  24 #include <target/cortex_m.h>
  25
  26
  27 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
  28 #define FLASH_ERASE_TIMEOUT 10000
  29 #define FLASH_WRITE_TIMEOUT 5
  30
  31 /* RM 433 */
  32 /* Same Flash registers for both banks, */
  33 /* access depends on Flash Base address */
  34 #define FLASH_ACR       0x00
  35 #define FLASH_KEYR      0x04
  36 #define FLASH_OPTKEYR   0x08
  37 #define FLASH_CR        0x0C
  38 #define FLASH_SR        0x10
  39 #define FLASH_CCR       0x14
  40 #define FLASH_OPTCR     0x18
  41 #define FLASH_OPTSR_CUR 0x1C
  42 #define FLASH_OPTSR_PRG 0x20
  43 #define FLASH_OPTCCR    0x24
  44 #define FLASH_WPSN_CUR  0x38
  45 #define FLASH_WPSN_PRG  0x3C
  46
  47
  48 /* FLASH_CR register bits */
  49 #define FLASH_LOCK     (1 << 0)
  50 #define FLASH_PG       (1 << 1)
  51 #define FLASH_SER      (1 << 2)
  52 #define FLASH_BER      (1 << 3)
  53 #define FLASH_PSIZE_8  (0 << 4)
  54 #define FLASH_PSIZE_16 (1 << 4)
  55 #define FLASH_PSIZE_32 (2 << 4)
  56 #define FLASH_PSIZE_64 (3 << 4)
  57 #define FLASH_FW       (1 << 6)
  58 #define FLASH_START    (1 << 7)
  59
  60 /* FLASH_SR register bits */
  61 #define FLASH_BSY      (1 << 0)  /* Operation in progress */
  62 #define FLASH_QW       (1 << 2)  /* Operation queue in progress */
  63 #define FLASH_WRPERR   (1 << 17) /* Write protection error */
  64 #define FLASH_PGSERR   (1 << 18) /* Programming sequence error */
  65 #define FLASH_STRBERR  (1 << 19) /* Strobe error */
  66 #define FLASH_INCERR   (1 << 21) /* Inconsistency error */
  67 #define FLASH_OPERR    (1 << 22) /* Operation error */
  68 #define FLASH_RDPERR   (1 << 23) /* Read Protection error */
  69 #define FLASH_RDSERR   (1 << 24) /* Secure Protection error */
  70 #define FLASH_SNECCERR (1 << 25) /* Single ECC error */
  71 #define FLASH_DBECCERR (1 << 26) /* Double ECC error */
  72
  73 #define FLASH_ERROR (FLASH_WRPERR | FLASH_PGSERR | FLASH_STRBERR | FLASH_INCERR | FLASH_OPERR | \
  74                                          FLASH_RDPERR | FLASH_RDSERR | FLASH_SNECCERR | FLASH_DBECCERR)
  75
  76 /* FLASH_OPTCR register bits */
  77 #define OPT_LOCK       (1 << 0)
  78 #define OPT_START      (1 << 1)
  79
  80 /* FLASH_OPTSR register bits */
  81 #define OPT_BSY        (1 << 0)
  82 #define OPT_RDP_POS    8
  83 #define OPT_RDP_MASK   (0xff << OPT_RDP_POS)
  84 #define OPT_OPTCHANGEERR (1 << 30)
  85
  86 /* FLASH_OPTCCR register bits */
  87 #define OPT_CLR_OPTCHANGEERR (1 << 30)
  88
  89 /* register unlock keys */
  90 #define KEY1           0x45670123
  91 #define KEY2           0xCDEF89AB
  92
  93 /* option register unlock key */
  94 #define OPTKEY1        0x08192A3B
  95 #define OPTKEY2        0x4C5D6E7F
  96
  97 #define DBGMCU_IDCODE_REGISTER  0x5C001000
  98 #define FLASH_BANK0_ADDRESS     0x08000000
  99 #define FLASH_BANK1_ADDRESS     0x08100000
 100 #define FLASH_REG_BASE_B0       0x52002000
 101 #define FLASH_REG_BASE_B1       0x52002100
 102
 103 /* Supported device IDs */
 104 #define DEVID_STM32H74_H75XX    0x450
 105 #define DEVID_STM32H7A_H7BXX    0x480
 106 #define DEVID_STM32H72_H73XX    0x483
 107
 108 struct stm32h7x_rev {
 109         uint16_t rev;
 110         const char *str;
 111 };
 112
 113 /* stm32h7x_part_info permits the store each device information and specificities.
 114  * the default unit is byte unless the suffix '_kb' is used. */
 115
 116 struct stm32h7x_part_info {
 117         uint16_t id;
 118         const char *device_str;
 119         const struct stm32h7x_rev *revs;
 120         size_t num_revs;
 121         unsigned int page_size_kb;
 122         unsigned int block_size;    /* flash write word size in bytes */
 123         uint16_t max_flash_size_kb;
 124         bool has_dual_bank;
 125         uint16_t max_bank_size_kb;  /* Used when has_dual_bank is true */
 126         uint32_t fsize_addr;        /* Location of FSIZE register */
 127         uint32_t wps_group_size;    /* write protection group sectors' count */
 128         uint32_t wps_mask;
 129         /* function to compute flash_cr register values */
 130         uint32_t (*compute_flash_cr)(uint32_t cmd, int snb);
 131 };
 132
 133 struct stm32h7x_flash_bank {
 134         bool probed;
 135         uint32_t idcode;
 136         uint32_t user_bank_size;
 137         uint32_t flash_regs_base;    /* Address of flash reg controller */
 138         const struct stm32h7x_part_info *part_info;
 139 };
 140
 141 enum stm32h7x_opt_rdp {
 142         OPT_RDP_L0 = 0xaa,
 143         OPT_RDP_L1 = 0x00,
 144         OPT_RDP_L2 = 0xcc
 145 };
 146
 147 static const struct stm32h7x_rev stm32h74_h75xx_revs[] = {
 148         { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X"  }, { 0x2003, "V"  },
 149 };
 150
 151 static const struct stm32h7x_rev stm32h7a_h7bxx_revs[] = {
 152         { 0x1000, "A"},
 153 };
 154
 155 static const struct stm32h7x_rev stm32h72_h73xx_revs[] = {
 156         { 0x1000, "A" }, { 0x1001, "Z" },
 157 };
 158
 159 static uint32_t stm32h74_h75xx_compute_flash_cr(uint32_t cmd, int snb)
 160 {
 161         return cmd | (snb << 8);
 162 }
 163
 164 static uint32_t stm32h7a_h7bxx_compute_flash_cr(uint32_t cmd, int snb)
 165 {
 166         /* save FW and START bits, to be right shifted by 2 bits later */
 167         const uint32_t tmp = cmd & (FLASH_FW | FLASH_START);
 168
 169         /* mask parallelism (ignored), FW and START bits */
 170         cmd &= ~(FLASH_PSIZE_64 | FLASH_FW | FLASH_START);
 171
 172         return cmd | (tmp >> 2) | (snb << 6);
 173 }
 174
 175 static const struct stm32h7x_part_info stm32h7x_parts[] = {
 176         {
 177         .id                                     = DEVID_STM32H74_H75XX,
 178         .revs                           = stm32h74_h75xx_revs,
 179         .num_revs                       = ARRAY_SIZE(stm32h74_h75xx_revs),
 180         .device_str                     = "STM32H74x/75x",
 181         .page_size_kb           = 128,
 182         .block_size                     = 32,
 183         .max_flash_size_kb      = 2048,
 184         .max_bank_size_kb       = 1024,
 185         .has_dual_bank          = true,
 186         .fsize_addr                     = 0x1FF1E880,
 187         .wps_group_size         = 1,
 188         .wps_mask                       = 0xFF,
 189         .compute_flash_cr       = stm32h74_h75xx_compute_flash_cr,
 190         },
 191         {
 192         .id                                     = DEVID_STM32H7A_H7BXX,
 193         .revs                           = stm32h7a_h7bxx_revs,
 194         .num_revs                       = ARRAY_SIZE(stm32h7a_h7bxx_revs),
 195         .device_str                     = "STM32H7Ax/7Bx",
 196         .page_size_kb           = 8,
 197         .block_size                     = 16,
 198         .max_flash_size_kb      = 2048,
 199         .max_bank_size_kb       = 1024,
 200         .has_dual_bank          = true,
 201         .fsize_addr                     = 0x08FFF80C,
 202         .wps_group_size         = 4,
 203         .wps_mask                       = 0xFFFFFFFF,
 204         .compute_flash_cr       = stm32h7a_h7bxx_compute_flash_cr,
 205         },
 206         {
 207         .id                                     = DEVID_STM32H72_H73XX,
 208         .revs                           = stm32h72_h73xx_revs,
 209         .num_revs                       = ARRAY_SIZE(stm32h72_h73xx_revs),
 210         .device_str                     = "STM32H72x/73x",
 211         .page_size_kb           = 128,
 212         .block_size                     = 32,
 213         .max_flash_size_kb      = 1024,
 214         .max_bank_size_kb       = 1024,
 215         .has_dual_bank          = false,
 216         .fsize_addr                     = 0x1FF1E880,
 217         .wps_group_size         = 1,
 218         .wps_mask                       = 0xFF,
 219         .compute_flash_cr   = stm32h74_h75xx_compute_flash_cr,
 220         },
 221 };
 222
 223 /* flash bank stm32x <base> <size> 0 0 <target#> */
 224
 225 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 226 {
 227         struct stm32h7x_flash_bank *stm32x_info;
 228
 229         if (CMD_ARGC < 6)
 230                 return ERROR_COMMAND_SYNTAX_ERROR;
 231
 232         stm32x_info = malloc(sizeof(struct stm32h7x_flash_bank));
 233         bank->driver_priv = stm32x_info;
 234
 235         stm32x_info->probed = false;
 236         stm32x_info->user_bank_size = bank->size;
 237
 238         return ERROR_OK;
 239 }
 240
 241 static inline uint32_t stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
 242 {
 243         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 244         return reg_offset + stm32x_info->flash_regs_base;
 245 }
 246
 247 static inline int stm32x_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
 248 {
 249         uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
 250         int retval = target_read_u32(bank->target, reg_addr, value);
 251
 252         if (retval != ERROR_OK)
 253                 LOG_ERROR("error while reading from address 0x%" PRIx32, reg_addr);
 254
 255         return retval;
 256 }
 257
 258 static inline int stm32x_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
 259 {
 260         uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
 261         int retval = target_write_u32(bank->target, reg_addr, value);
 262
 263         if (retval != ERROR_OK)
 264                 LOG_ERROR("error while writing to address 0x%" PRIx32, reg_addr);
 265
 266         return retval;
 267 }
 268
 269 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 270 {
 271         return stm32x_read_flash_reg(bank, FLASH_SR, status);
 272 }
 273
 274 static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
 275 {
 276         uint32_t status;
 277         int retval;
 278
 279         /* wait for flash operations completion */
 280         for (;;) {
 281                 retval = stm32x_get_flash_status(bank, &status);
 282                 if (retval != ERROR_OK)
 283                         return retval;
 284
 285                 if ((status & FLASH_QW) == 0)
 286                         break;
 287
 288                 if (timeout-- <= 0) {
 289                         LOG_ERROR("wait_flash_op_queue, time out expired, status: 0x%" PRIx32, status);
 290                         return ERROR_FAIL;
 291                 }
 292                 alive_sleep(1);
 293         }
 294
 295         if (status & FLASH_WRPERR) {
 296                 LOG_ERROR("wait_flash_op_queue, WRPERR detected");
 297                 retval = ERROR_FAIL;
 298         }
 299
 300         /* Clear error + EOP flags but report errors */
 301         if (status & FLASH_ERROR) {
 302                 if (retval == ERROR_OK)
 303                         retval = ERROR_FAIL;
 304                 /* If this operation fails, we ignore it and report the original retval */
 305                 stm32x_write_flash_reg(bank, FLASH_CCR, status);
 306         }
 307         return retval;
 308 }
 309
 310 static int stm32x_unlock_reg(struct flash_bank *bank)
 311 {
 312         uint32_t ctrl;
 313
 314         /* first check if not already unlocked
 315          * otherwise writing on FLASH_KEYR will fail
 316          */
 317         int retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
 318         if (retval != ERROR_OK)
 319                 return retval;
 320
 321         if ((ctrl & FLASH_LOCK) == 0)
 322                 return ERROR_OK;
 323
 324         /* unlock flash registers for bank */
 325         retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY1);
 326         if (retval != ERROR_OK)
 327                 return retval;
 328
 329         retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY2);
 330         if (retval != ERROR_OK)
 331                 return retval;
 332
 333         retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
 334         if (retval != ERROR_OK)
 335                 return retval;
 336
 337         if (ctrl & FLASH_LOCK) {
 338                 LOG_ERROR("flash not unlocked STM32_FLASH_CRx: 0x%" PRIx32, ctrl);
 339                 return ERROR_TARGET_FAILURE;
 340         }
 341         return ERROR_OK;
 342 }
 343
 344 static int stm32x_unlock_option_reg(struct flash_bank *bank)
 345 {
 346         uint32_t ctrl;
 347
 348         int retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
 349         if (retval != ERROR_OK)
 350                 return retval;
 351
 352         if ((ctrl & OPT_LOCK) == 0)
 353                 return ERROR_OK;
 354
 355         /* unlock option registers */
 356         retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY1);
 357         if (retval != ERROR_OK)
 358                 return retval;
 359
 360         retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY2);
 361         if (retval != ERROR_OK)
 362                 return retval;
 363
 364         retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
 365         if (retval != ERROR_OK)
 366                 return retval;
 367
 368         if (ctrl & OPT_LOCK) {
 369                 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: 0x%" PRIx32, ctrl);
 370                 return ERROR_TARGET_FAILURE;
 371         }
 372
 373         return ERROR_OK;
 374 }
 375
 376 static inline int stm32x_lock_reg(struct flash_bank *bank)
 377 {
 378         return stm32x_write_flash_reg(bank, FLASH_CR, FLASH_LOCK);
 379 }
 380
 381 static inline int stm32x_lock_option_reg(struct flash_bank *bank)
 382 {
 383         return stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_LOCK);
 384 }
 385
 386 static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
 387 {
 388         int retval, retval2;
 389
 390         /* unlock option bytes for modification */
 391         retval = stm32x_unlock_option_reg(bank);
 392         if (retval != ERROR_OK)
 393                 goto flash_options_lock;
 394
 395         /* write option bytes */
 396         retval = stm32x_write_flash_reg(bank, reg_offset, value);
 397         if (retval != ERROR_OK)
 398                 goto flash_options_lock;
 399
 400         /* Remove OPT error flag before programming */
 401         retval = stm32x_write_flash_reg(bank, FLASH_OPTCCR, OPT_CLR_OPTCHANGEERR);
 402         if (retval != ERROR_OK)
 403                 goto flash_options_lock;
 404
 405         /* start programming cycle */
 406         retval = stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_START);
 407         if (retval != ERROR_OK)
 408                 goto flash_options_lock;
 409
 410         /* wait for completion */
 411         int timeout = FLASH_ERASE_TIMEOUT;
 412         uint32_t status;
 413         for (;;) {
 414                 retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_CUR, &status);
 415                 if (retval != ERROR_OK) {
 416                         LOG_ERROR("stm32x_options_program: failed to read FLASH_OPTSR_CUR");
 417                         goto flash_options_lock;
 418                 }
 419                 if ((status & OPT_BSY) == 0)
 420                         break;
 421
 422                 if (timeout-- <= 0) {
 423                         LOG_ERROR("waiting for OBL launch, time out expired, OPTSR: 0x%" PRIx32, status);
 424                         retval = ERROR_FAIL;
 425                         goto flash_options_lock;
 426                 }
 427                 alive_sleep(1);
 428         }
 429
 430         /* check for failure */
 431         if (status & OPT_OPTCHANGEERR) {
 432                 LOG_ERROR("error changing option bytes (OPTCHANGEERR=1)");
 433                 retval = ERROR_FLASH_OPERATION_FAILED;
 434         }
 435
 436 flash_options_lock:
 437         retval2 = stm32x_lock_option_reg(bank);
 438         if (retval2 != ERROR_OK)
 439                 LOG_ERROR("error during the lock of flash options");
 440
 441         return (retval == ERROR_OK) ? retval2 : retval;
 442 }
 443
 444 static int stm32x_modify_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
 445 {
 446         uint32_t data;
 447
 448         int retval = stm32x_read_flash_reg(bank, reg_offset, &data);
 449         if (retval != ERROR_OK)
 450                 return retval;
 451
 452         data = (data & ~mask) | (value & mask);
 453
 454         return stm32x_write_option(bank, reg_offset, data);
 455 }
 456
 457 static int stm32x_protect_check(struct flash_bank *bank)
 458 {
 459         uint32_t protection;
 460
 461         /* read 'write protection' settings */
 462         int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
 463         if (retval != ERROR_OK) {
 464                 LOG_DEBUG("unable to read WPSN_CUR register");
 465                 return retval;
 466         }
 467
 468         for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
 469                 bank->prot_blocks[i].is_protected = protection & (1 << i) ? 0 : 1;
 470
 471         return ERROR_OK;
 472 }
 473
 474 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
 475                 unsigned int last)
 476 {
 477         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 478         int retval, retval2;
 479
 480         assert(first < bank->num_sectors);
 481         assert(last < bank->num_sectors);
 482
 483         if (bank->target->state != TARGET_HALTED)
 484                 return ERROR_TARGET_NOT_HALTED;
 485
 486         retval = stm32x_unlock_reg(bank);
 487         if (retval != ERROR_OK)
 488                 goto flash_lock;
 489
 490         /*
 491         Sector Erase
 492         To erase a sector, follow the procedure below:
 493         1. Check that no Flash memory operation is ongoing by checking the QW bit in the
 494           FLASH_SR register
 495         2. Set the SER bit and select the sector
 496           you wish to erase (SNB) in the FLASH_CR register
 497         3. Set the STRT bit in the FLASH_CR register
 498         4. Wait for flash operations completion
 499          */
 500         for (unsigned int i = first; i <= last; i++) {
 501                 LOG_DEBUG("erase sector %u", i);
 502                 retval = stm32x_write_flash_reg(bank, FLASH_CR,
 503                                 stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64, i));
 504                 if (retval != ERROR_OK) {
 505                         LOG_ERROR("Error erase sector %u", i);
 506                         goto flash_lock;
 507                 }
 508                 retval = stm32x_write_flash_reg(bank, FLASH_CR,
 509                                 stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64 | FLASH_START, i));
 510                 if (retval != ERROR_OK) {
 511                         LOG_ERROR("Error erase sector %u", i);
 512                         goto flash_lock;
 513                 }
 514                 retval = stm32x_wait_flash_op_queue(bank, FLASH_ERASE_TIMEOUT);
 515
 516                 if (retval != ERROR_OK) {
 517                         LOG_ERROR("erase time-out or operation error sector %u", i);
 518                         goto flash_lock;
 519                 }
 520         }
 521
 522 flash_lock:
 523         retval2 = stm32x_lock_reg(bank);
 524         if (retval2 != ERROR_OK)
 525                 LOG_ERROR("error during the lock of flash");
 526
 527         return (retval == ERROR_OK) ? retval2 : retval;
 528 }
 529
 530 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 531                 unsigned int last)
 532 {
 533         struct target *target = bank->target;
 534         uint32_t protection;
 535
 536         if (target->state != TARGET_HALTED) {
 537                 LOG_ERROR("Target not halted");
 538                 return ERROR_TARGET_NOT_HALTED;
 539         }
 540
 541         /* read 'write protection' settings */
 542         int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
 543         if (retval != ERROR_OK) {
 544                 LOG_DEBUG("unable to read WPSN_CUR register");
 545                 return retval;
 546         }
 547
 548         for (unsigned int i = first; i <= last; i++) {
 549                 if (set)
 550                         protection &= ~(1 << i);
 551                 else
 552                         protection |= (1 << i);
 553         }
 554
 555         /* apply WRPSN mask */
 556         protection &= 0xff;
 557
 558         LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%" PRIx32, protection);
 559
 560         /* apply new option value */
 561         return stm32x_write_option(bank, FLASH_WPSN_PRG, protection);
 562 }
 563
 564 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 565                 uint32_t offset, uint32_t count)
 566 {
 567         struct target *target = bank->target;
 568         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 569         /*
 570          * If the size of the data part of the buffer is not a multiple of .block_size, we get
 571          * "corrupted fifo read" pointer in target_run_flash_async_algorithm()
 572          */
 573         uint32_t data_size = 512 * stm32x_info->part_info->block_size;
 574         uint32_t buffer_size = 8 + data_size;
 575         struct working_area *write_algorithm;
 576         struct working_area *source;
 577         uint32_t address = bank->base + offset;
 578         struct reg_param reg_params[6];
 579         struct armv7m_algorithm armv7m_info;
 580         int retval = ERROR_OK;
 581
 582         static const uint8_t stm32x_flash_write_code[] = {
 583 #include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
 584         };
 585
 586         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 587                         &write_algorithm) != ERROR_OK) {
 588                 LOG_WARNING("no working area available, can't do block memory writes");
 589                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 590         }
 591
 592         retval = target_write_buffer(target, write_algorithm->address,
 593                         sizeof(stm32x_flash_write_code),
 594                         stm32x_flash_write_code);
 595         if (retval != ERROR_OK) {
 596                 target_free_working_area(target, write_algorithm);
 597                 return retval;
 598         }
 599
 600         /* memory buffer */
 601         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 602                 data_size /= 2;
 603                 buffer_size = 8 + data_size;
 604                 if (data_size <= 256) {
 605                         /* we already allocated the writing code, but failed to get a
 606                          * buffer, free the algorithm */
 607                         target_free_working_area(target, write_algorithm);
 608
 609                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 610                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 611                 }
 612         }
 613
 614         LOG_DEBUG("target_alloc_working_area_try : buffer_size -> 0x%" PRIx32, buffer_size);
 615
 616         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 617         armv7m_info.core_mode = ARM_MODE_THREAD;
 618
 619         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);         /* buffer start, status (out) */
 620         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);            /* buffer end */
 621         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);            /* target address */
 622         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);            /* count of words (word size = .block_size (bytes) */
 623         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);            /* word size in bytes */
 624         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);            /* flash reg base */
 625
 626         buf_set_u32(reg_params[0].value, 0, 32, source->address);
 627         buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
 628         buf_set_u32(reg_params[2].value, 0, 32, address);
 629         buf_set_u32(reg_params[3].value, 0, 32, count);
 630         buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->part_info->block_size);
 631         buf_set_u32(reg_params[5].value, 0, 32, stm32x_info->flash_regs_base);
 632
 633         retval = target_run_flash_async_algorithm(target,
 634                                                   buffer,
 635                                                   count,
 636                                                   stm32x_info->part_info->block_size,
 637                                                   0, NULL,
 638                                                   ARRAY_SIZE(reg_params), reg_params,
 639                                                   source->address, source->size,
 640                                                   write_algorithm->address, 0,
 641                                                   &armv7m_info);
 642
 643         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 644                 LOG_ERROR("error executing stm32h7x flash write algorithm");
 645
 646                 uint32_t flash_sr = buf_get_u32(reg_params[0].value, 0, 32);
 647
 648                 if (flash_sr & FLASH_WRPERR)
 649                         LOG_ERROR("flash memory write protected");
 650
 651                 if ((flash_sr & FLASH_ERROR) != 0) {
 652                         LOG_ERROR("flash write failed, FLASH_SR = 0x%08" PRIx32, flash_sr);
 653                         /* Clear error + EOP flags but report errors */
 654                         stm32x_write_flash_reg(bank, FLASH_CCR, flash_sr);
 655                         retval = ERROR_FAIL;
 656                 }
 657         }
 658
 659         target_free_working_area(target, source);
 660         target_free_working_area(target, write_algorithm);
 661
 662         destroy_reg_param(&reg_params[0]);
 663         destroy_reg_param(&reg_params[1]);
 664         destroy_reg_param(&reg_params[2]);
 665         destroy_reg_param(&reg_params[3]);
 666         destroy_reg_param(&reg_params[4]);
 667         destroy_reg_param(&reg_params[5]);
 668         return retval;
 669 }
 670
 671 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 672                 uint32_t offset, uint32_t count)
 673 {
 674         struct target *target = bank->target;
 675         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 676         uint32_t address = bank->base + offset;
 677         int retval, retval2;
 678
 679         if (bank->target->state != TARGET_HALTED) {
 680                 LOG_ERROR("Target not halted");
 681                 return ERROR_TARGET_NOT_HALTED;
 682         }
 683
 684         /* should be enforced via bank->write_start_alignment */
 685         assert(!(offset % stm32x_info->part_info->block_size));
 686
 687         /* should be enforced via bank->write_end_alignment */
 688         assert(!(count % stm32x_info->part_info->block_size));
 689
 690         retval = stm32x_unlock_reg(bank);
 691         if (retval != ERROR_OK)
 692                 goto flash_lock;
 693
 694         uint32_t blocks_remaining = count / stm32x_info->part_info->block_size;
 695
 696         /* multiple words (n * .block_size) to be programmed in block */
 697         if (blocks_remaining) {
 698                 retval = stm32x_write_block(bank, buffer, offset, blocks_remaining);
 699                 if (retval != ERROR_OK) {
 700                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 701                                 /* if block write failed (no sufficient working area),
 702                                  * we use normal (slow) dword accesses */
 703                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 704                         }
 705                 } else {
 706                         buffer += blocks_remaining * stm32x_info->part_info->block_size;
 707                         address += blocks_remaining * stm32x_info->part_info->block_size;
 708                         blocks_remaining = 0;
 709                 }
 710                 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
 711                         goto flash_lock;
 712         }
 713
 714         /*
 715         Standard programming
 716         The Flash memory programming sequence is as follows:
 717         1. Check that no main Flash memory operation is ongoing by checking the QW bit in the
 718            FLASH_SR register.
 719         2. Set the PG bit in the FLASH_CR register
 720         3. 8 x Word access (or Force Write FW)
 721         4. Wait for flash operations completion
 722         */
 723         while (blocks_remaining > 0) {
 724                 retval = stm32x_write_flash_reg(bank, FLASH_CR,
 725                                 stm32x_info->part_info->compute_flash_cr(FLASH_PG | FLASH_PSIZE_64, 0));
 726                 if (retval != ERROR_OK)
 727                         goto flash_lock;
 728
 729                 retval = target_write_buffer(target, address, stm32x_info->part_info->block_size, buffer);
 730                 if (retval != ERROR_OK)
 731                         goto flash_lock;
 732
 733                 retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
 734                 if (retval != ERROR_OK)
 735                         goto flash_lock;
 736
 737                 buffer += stm32x_info->part_info->block_size;
 738                 address += stm32x_info->part_info->block_size;
 739                 blocks_remaining--;
 740         }
 741
 742 flash_lock:
 743         retval2 = stm32x_lock_reg(bank);
 744         if (retval2 != ERROR_OK)
 745                 LOG_ERROR("error during the lock of flash");
 746
 747         return (retval == ERROR_OK) ? retval2 : retval;
 748 }
 749
 750 static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
 751 {
 752         /* read stm32 device id register */
 753         int retval = target_read_u32(bank->target, DBGMCU_IDCODE_REGISTER, id);
 754         if (retval != ERROR_OK)
 755                 return retval;
 756         return ERROR_OK;
 757 }
 758
 759 static int stm32x_probe(struct flash_bank *bank)
 760 {
 761         struct target *target = bank->target;
 762         struct cortex_m_common *cortex_m = target_to_cm(target);
 763         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 764         uint16_t flash_size_in_kb;
 765         uint32_t device_id;
 766
 767         stm32x_info->probed = false;
 768         stm32x_info->part_info = NULL;
 769
 770         int retval = stm32x_read_id_code(bank, &stm32x_info->idcode);
 771         if (retval != ERROR_OK)
 772                 return retval;
 773
 774         LOG_DEBUG("device id = 0x%08" PRIx32, stm32x_info->idcode);
 775
 776         device_id = stm32x_info->idcode & 0xfff;
 777
 778         for (unsigned int n = 0; n < ARRAY_SIZE(stm32h7x_parts); n++) {
 779                 if (device_id == stm32h7x_parts[n].id)
 780                         stm32x_info->part_info = &stm32h7x_parts[n];
 781         }
 782         if (!stm32x_info->part_info) {
 783                 LOG_WARNING("Cannot identify target as a STM32H7xx family.");
 784                 return ERROR_FAIL;
 785         } else {
 786                 LOG_INFO("Device: %s", stm32x_info->part_info->device_str);
 787         }
 788
 789         /* update the address of controller */
 790         if (bank->base == FLASH_BANK0_ADDRESS)
 791                 stm32x_info->flash_regs_base = FLASH_REG_BASE_B0;
 792         else if (bank->base == FLASH_BANK1_ADDRESS)
 793                 stm32x_info->flash_regs_base = FLASH_REG_BASE_B1;
 794         else {
 795                 LOG_WARNING("Flash register base not defined for bank %u", bank->bank_number);
 796                 return ERROR_FAIL;
 797         }
 798         LOG_DEBUG("flash_regs_base: 0x%" PRIx32, stm32x_info->flash_regs_base);
 799
 800         /* get flash size from target */
 801         /* STM32H74x/H75x, the second core (Cortex-M4) cannot read the flash size */
 802         retval = ERROR_FAIL;
 803         if (device_id == DEVID_STM32H74_H75XX && cortex_m->core_info->partno == CORTEX_M4_PARTNO)
 804                 LOG_WARNING("%s cannot read the flash size register", target_name(target));
 805         else
 806                 retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb);
 807
 808         if (retval != ERROR_OK) {
 809                 /* read error when device has invalid value, set max flash size */
 810                 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
 811                 LOG_INFO("assuming %" PRIu16 "k flash", flash_size_in_kb);
 812         } else
 813                 LOG_INFO("flash size probed value %" PRIu16 "k", flash_size_in_kb);
 814
 815         /* setup bank size */
 816         const uint32_t bank1_base = FLASH_BANK0_ADDRESS;
 817         const uint32_t bank2_base = bank1_base + stm32x_info->part_info->max_bank_size_kb * 1024;
 818         bool has_dual_bank = stm32x_info->part_info->has_dual_bank;
 819
 820         switch (device_id) {
 821         case DEVID_STM32H74_H75XX:
 822         case DEVID_STM32H7A_H7BXX:
 823                 /* For STM32H74x/75x and STM32H7Ax/Bx
 824                  *  - STM32H7xxxI devices contains dual bank, 1 Mbyte each
 825                  *  - STM32H7xxxG devices contains dual bank, 512 Kbyte each
 826                  *  - STM32H7xxxB devices contains single bank, 128 Kbyte
 827                  *  - the second bank starts always from 0x08100000
 828                  */
 829                 if (flash_size_in_kb == 128)
 830                         has_dual_bank = false;
 831                 else
 832                         /* flash size is 2M or 1M */
 833                         flash_size_in_kb /= 2;
 834                 break;
 835         case DEVID_STM32H72_H73XX:
 836                 break;
 837         default:
 838                 LOG_ERROR("unsupported device");
 839                 return ERROR_FAIL;
 840         }
 841
 842         if (has_dual_bank) {
 843                 LOG_INFO("STM32H7 flash has dual banks");
 844                 if (bank->base != bank1_base && bank->base != bank2_base) {
 845                         LOG_ERROR("STM32H7 flash bank base address config is incorrect. "
 846                                         TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
 847                                         bank->base, bank1_base, bank2_base);
 848                         return ERROR_FAIL;
 849                 }
 850         } else {
 851                 LOG_INFO("STM32H7 flash has a single bank");
 852                 if (bank->base == bank2_base) {
 853                         LOG_ERROR("this device has a single bank only");
 854                         return ERROR_FAIL;
 855                 } else if (bank->base != bank1_base) {
 856                         LOG_ERROR("STM32H7 flash bank base address config is incorrect. "
 857                                         TARGET_ADDR_FMT " but should be 0x%" PRIx32,
 858                                         bank->base, bank1_base);
 859                         return ERROR_FAIL;
 860                 }
 861         }
 862
 863         LOG_INFO("Bank (%u) size is %" PRIu16 " kb, base address is " TARGET_ADDR_FMT,
 864                 bank->bank_number, flash_size_in_kb, bank->base);
 865
 866         /* if the user sets the size manually then ignore the probed value
 867          * this allows us to work around devices that have an invalid flash size register value */
 868         if (stm32x_info->user_bank_size) {
 869                 LOG_INFO("ignoring flash probed value, using configured bank size");
 870                 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
 871         } else if (flash_size_in_kb == 0xffff) {
 872                 /* die flash size */
 873                 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
 874         }
 875
 876         /* did we assign flash size? */
 877         assert(flash_size_in_kb != 0xffff);
 878         bank->size = flash_size_in_kb * 1024;
 879         bank->write_start_alignment = stm32x_info->part_info->block_size;
 880         bank->write_end_alignment = stm32x_info->part_info->block_size;
 881
 882         /* setup sectors */
 883         bank->num_sectors = flash_size_in_kb / stm32x_info->part_info->page_size_kb;
 884         assert(bank->num_sectors > 0);
 885
 886         free(bank->sectors);
 887
 888         bank->sectors = alloc_block_array(0, stm32x_info->part_info->page_size_kb * 1024,
 889                         bank->num_sectors);
 890
 891         if (!bank->sectors) {
 892                 LOG_ERROR("failed to allocate bank sectors");
 893                 return ERROR_FAIL;
 894         }
 895
 896         /* setup protection blocks */
 897         const uint32_t wpsn = stm32x_info->part_info->wps_group_size;
 898         assert(bank->num_sectors % wpsn == 0);
 899
 900         bank->num_prot_blocks = bank->num_sectors / wpsn;
 901         assert(bank->num_prot_blocks > 0);
 902
 903         free(bank->prot_blocks);
 904
 905         bank->prot_blocks = alloc_block_array(0, stm32x_info->part_info->page_size_kb * wpsn * 1024,
 906                         bank->num_prot_blocks);
 907
 908         if (!bank->prot_blocks) {
 909                 LOG_ERROR("failed to allocate bank prot_block");
 910                 return ERROR_FAIL;
 911         }
 912
 913         stm32x_info->probed = true;
 914         return ERROR_OK;
 915 }
 916
 917 static int stm32x_auto_probe(struct flash_bank *bank)
 918 {
 919         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 920
 921         if (stm32x_info->probed)
 922                 return ERROR_OK;
 923
 924         return stm32x_probe(bank);
 925 }
 926
 927 /* This method must return a string displaying information about the bank */
 928 static int stm32x_get_info(struct flash_bank *bank, struct command_invocation *cmd)
 929 {
 930         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
 931         const struct stm32h7x_part_info *info = stm32x_info->part_info;
 932
 933         if (!stm32x_info->probed) {
 934                 int retval = stm32x_probe(bank);
 935                 if (retval != ERROR_OK) {
 936                         command_print_sameline(cmd, "Unable to find bank information.");
 937                         return retval;
 938                 }
 939         }
 940
 941         if (info) {
 942                 const char *rev_str = NULL;
 943                 uint16_t rev_id = stm32x_info->idcode >> 16;
 944
 945                 for (unsigned int i = 0; i < info->num_revs; i++)
 946                         if (rev_id == info->revs[i].rev)
 947                                 rev_str = info->revs[i].str;
 948
 949                 if (rev_str) {
 950                         command_print_sameline(cmd, "%s - Rev: %s",
 951                                 stm32x_info->part_info->device_str, rev_str);
 952                 } else {
 953                         command_print_sameline(cmd,
 954                                  "%s - Rev: unknown (0x%04" PRIx16 ")",
 955                                 stm32x_info->part_info->device_str, rev_id);
 956                 }
 957         } else {
 958                 command_print_sameline(cmd, "Cannot identify target as a STM32H7x");
 959                 return ERROR_FAIL;
 960         }
 961         return ERROR_OK;
 962 }
 963
 964 static int stm32x_set_rdp(struct flash_bank *bank, enum stm32h7x_opt_rdp new_rdp)
 965 {
 966         struct target *target = bank->target;
 967         uint32_t optsr, cur_rdp;
 968         int retval;
 969
 970         if (target->state != TARGET_HALTED) {
 971                 LOG_ERROR("Target not halted");
 972                 return ERROR_TARGET_NOT_HALTED;
 973         }
 974
 975         retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_PRG, &optsr);
 976
 977         if (retval != ERROR_OK) {
 978                 LOG_DEBUG("unable to read FLASH_OPTSR_PRG register");
 979                 return retval;
 980         }
 981
 982         /* get current RDP, and check if there is a change */
 983         cur_rdp = (optsr & OPT_RDP_MASK) >> OPT_RDP_POS;
 984         if (new_rdp == cur_rdp) {
 985                 LOG_INFO("the requested RDP value is already programmed");
 986                 return ERROR_OK;
 987         }
 988
 989         switch (new_rdp) {
 990         case OPT_RDP_L0:
 991                 LOG_WARNING("unlocking the entire flash device");
 992                 break;
 993         case OPT_RDP_L1:
 994                 LOG_WARNING("locking the entire flash device");
 995                 break;
 996         case OPT_RDP_L2:
 997                 LOG_WARNING("locking the entire flash device, irreversible");
 998                 break;
 999         }
1000
1001         /* apply new RDP */
1002         optsr = (optsr & ~OPT_RDP_MASK) | (new_rdp << OPT_RDP_POS);
1003
1004         /* apply new option value */
1005         return stm32x_write_option(bank, FLASH_OPTSR_PRG, optsr);
1006 }
1007
1008 COMMAND_HANDLER(stm32x_handle_lock_command)
1009 {
1010         if (CMD_ARGC < 1)
1011                 return ERROR_COMMAND_SYNTAX_ERROR;
1012
1013         struct flash_bank *bank;
1014         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1015         if (retval != ERROR_OK)
1016                 return retval;
1017
1018         retval = stm32x_set_rdp(bank, OPT_RDP_L1);
1019
1020         if (retval != ERROR_OK)
1021                 command_print(CMD, "%s failed to lock device", bank->driver->name);
1022         else
1023                 command_print(CMD, "%s locked", bank->driver->name);
1024
1025         return retval;
1026 }
1027
1028 COMMAND_HANDLER(stm32x_handle_unlock_command)
1029 {
1030         if (CMD_ARGC < 1)
1031                 return ERROR_COMMAND_SYNTAX_ERROR;
1032
1033         struct flash_bank *bank;
1034         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1035         if (retval != ERROR_OK)
1036                 return retval;
1037
1038         retval = stm32x_set_rdp(bank, OPT_RDP_L0);
1039
1040         if (retval != ERROR_OK)
1041                 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1042         else
1043                 command_print(CMD, "%s unlocked", bank->driver->name);
1044
1045         return retval;
1046 }
1047
1048 static int stm32x_mass_erase(struct flash_bank *bank)
1049 {
1050         int retval, retval2;
1051         struct target *target = bank->target;
1052         struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
1053
1054         if (target->state != TARGET_HALTED) {
1055                 LOG_ERROR("Target not halted");
1056                 return ERROR_TARGET_NOT_HALTED;
1057         }
1058
1059         retval = stm32x_unlock_reg(bank);
1060         if (retval != ERROR_OK)
1061                 goto flash_lock;
1062
1063         /* mass erase flash memory bank */
1064         retval = stm32x_write_flash_reg(bank, FLASH_CR,
1065                         stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64, 0));
1066         if (retval != ERROR_OK)
1067                 goto flash_lock;
1068
1069         retval = stm32x_write_flash_reg(bank, FLASH_CR,
1070                         stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64 | FLASH_START, 0));
1071         if (retval != ERROR_OK)
1072                 goto flash_lock;
1073
1074         retval = stm32x_wait_flash_op_queue(bank, 30000);
1075         if (retval != ERROR_OK)
1076                 goto flash_lock;
1077
1078 flash_lock:
1079         retval2 = stm32x_lock_reg(bank);
1080         if (retval2 != ERROR_OK)
1081                 LOG_ERROR("error during the lock of flash");
1082
1083         return (retval == ERROR_OK) ? retval2 : retval;
1084 }
1085
1086 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1087 {
1088         if (CMD_ARGC < 1) {
1089                 command_print(CMD, "stm32h7x mass_erase <bank>");
1090                 return ERROR_COMMAND_SYNTAX_ERROR;
1091         }
1092
1093         struct flash_bank *bank;
1094         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1095         if (retval != ERROR_OK)
1096                 return retval;
1097
1098         retval = stm32x_mass_erase(bank);
1099         if (retval == ERROR_OK)
1100                 command_print(CMD, "stm32h7x mass erase complete");
1101         else
1102                 command_print(CMD, "stm32h7x mass erase failed");
1103
1104         return retval;
1105 }
1106
1107 COMMAND_HANDLER(stm32x_handle_option_read_command)
1108 {
1109         if (CMD_ARGC < 2) {
1110                 command_print(CMD, "stm32h7x option_read <bank> <option_reg offset>");
1111                 return ERROR_COMMAND_SYNTAX_ERROR;
1112         }
1113
1114         struct flash_bank *bank;
1115         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1116         if (retval != ERROR_OK)
1117                 return retval;
1118
1119         uint32_t reg_offset, value;
1120
1121         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1122         retval = stm32x_read_flash_reg(bank, reg_offset, &value);
1123         if (retval != ERROR_OK)
1124                 return retval;
1125
1126         command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32,
1127                         stm32x_get_flash_reg(bank, reg_offset), value);
1128
1129         return retval;
1130 }
1131
1132 COMMAND_HANDLER(stm32x_handle_option_write_command)
1133 {
1134         if (CMD_ARGC < 3) {
1135                 command_print(CMD, "stm32h7x option_write <bank> <option_reg offset> <value> [mask]");
1136                 return ERROR_COMMAND_SYNTAX_ERROR;
1137         }
1138
1139         struct flash_bank *bank;
1140         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1141         if (retval != ERROR_OK)
1142                 return retval;
1143
1144         uint32_t reg_offset, value, mask = 0xffffffff;
1145
1146         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1147         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1148         if (CMD_ARGC > 3)
1149                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
1150
1151         return stm32x_modify_option(bank, reg_offset, value, mask);
1152 }
1153
1154 static const struct command_registration stm32x_exec_command_handlers[] = {
1155         {
1156                 .name = "lock",
1157                 .handler = stm32x_handle_lock_command,
1158                 .mode = COMMAND_EXEC,
1159                 .usage = "bank_id",
1160                 .help = "Lock entire flash device.",
1161         },
1162         {
1163                 .name = "unlock",
1164                 .handler = stm32x_handle_unlock_command,
1165                 .mode = COMMAND_EXEC,
1166                 .usage = "bank_id",
1167                 .help = "Unlock entire protected flash device.",
1168         },
1169         {
1170                 .name = "mass_erase",
1171                 .handler = stm32x_handle_mass_erase_command,
1172                 .mode = COMMAND_EXEC,
1173                 .usage = "bank_id",
1174                 .help = "Erase entire flash device.",
1175         },
1176         {
1177                 .name = "option_read",
1178                 .handler = stm32x_handle_option_read_command,
1179                 .mode = COMMAND_EXEC,
1180                 .usage = "bank_id reg_offset",
1181                 .help = "Read and display device option bytes.",
1182         },
1183         {
1184                 .name = "option_write",
1185                 .handler = stm32x_handle_option_write_command,
1186                 .mode = COMMAND_EXEC,
1187                 .usage = "bank_id reg_offset value [mask]",
1188                 .help = "Write device option bit fields with provided value.",
1189         },
1190         COMMAND_REGISTRATION_DONE
1191 };
1192
1193 static const struct command_registration stm32x_command_handlers[] = {
1194         {
1195                 .name = "stm32h7x",
1196                 .mode = COMMAND_ANY,
1197                 .help = "stm32h7x flash command group",
1198                 .usage = "",
1199                 .chain = stm32x_exec_command_handlers,
1200         },
1201         COMMAND_REGISTRATION_DONE
1202 };
1203
1204 const struct flash_driver stm32h7x_flash = {
1205         .name = "stm32h7x",
1206         .commands = stm32x_command_handlers,
1207         .flash_bank_command = stm32x_flash_bank_command,
1208         .erase = stm32x_erase,
1209         .protect = stm32x_protect,
1210         .write = stm32x_write,
1211         .read = default_flash_read,
1212         .probe = stm32x_probe,
1213         .auto_probe = stm32x_auto_probe,
1214         .erase_check = default_flash_blank_check,
1215         .protect_check = stm32x_protect_check,
1216         .info = stm32x_get_info,
1217         .free_driver_priv = default_flash_free_driver_priv,
1218 };