1 /***************************************************************************
2 * Copyright (C) 2017 by STMicroelectronics *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
22 #include <helper/binarybuffer.h>
23 #include <target/algorithm.h>
24 #include <target/cortex_m.h>
27 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
28 #define FLASH_ERASE_TIMEOUT 10000
29 #define FLASH_WRITE_TIMEOUT 5
32 /* Same Flash registers for both banks, */
33 /* access depends on Flash Base address */
34 #define FLASH_ACR 0x00
35 #define FLASH_KEYR 0x04
36 #define FLASH_OPTKEYR 0x08
39 #define FLASH_CCR 0x14
40 #define FLASH_OPTCR 0x18
41 #define FLASH_OPTSR_CUR 0x1C
42 #define FLASH_OPTSR_PRG 0x20
43 #define FLASH_OPTCCR 0x24
44 #define FLASH_WPSN_CUR 0x38
45 #define FLASH_WPSN_PRG 0x3C
48 /* FLASH_CR register bits */
49 #define FLASH_LOCK (1 << 0)
50 #define FLASH_PG (1 << 1)
51 #define FLASH_SER (1 << 2)
52 #define FLASH_BER (1 << 3)
53 #define FLASH_PSIZE_8 (0 << 4)
54 #define FLASH_PSIZE_16 (1 << 4)
55 #define FLASH_PSIZE_32 (2 << 4)
56 #define FLASH_PSIZE_64 (3 << 4)
57 #define FLASH_FW (1 << 6)
58 #define FLASH_START (1 << 7)
60 /* FLASH_SR register bits */
61 #define FLASH_BSY (1 << 0) /* Operation in progress */
62 #define FLASH_QW (1 << 2) /* Operation queue in progress */
63 #define FLASH_WRPERR (1 << 17) /* Write protection error */
64 #define FLASH_PGSERR (1 << 18) /* Programming sequence error */
65 #define FLASH_STRBERR (1 << 19) /* Strobe error */
66 #define FLASH_INCERR (1 << 21) /* Inconsistency error */
67 #define FLASH_OPERR (1 << 22) /* Operation error */
68 #define FLASH_RDPERR (1 << 23) /* Read Protection error */
69 #define FLASH_RDSERR (1 << 24) /* Secure Protection error */
70 #define FLASH_SNECCERR (1 << 25) /* Single ECC error */
71 #define FLASH_DBECCERR (1 << 26) /* Double ECC error */
73 #define FLASH_ERROR (FLASH_WRPERR | FLASH_PGSERR | FLASH_STRBERR | FLASH_INCERR | FLASH_OPERR | \
74 FLASH_RDPERR | FLASH_RDSERR | FLASH_SNECCERR | FLASH_DBECCERR)
76 /* FLASH_OPTCR register bits */
77 #define OPT_LOCK (1 << 0)
78 #define OPT_START (1 << 1)
80 /* FLASH_OPTSR register bits */
81 #define OPT_BSY (1 << 0)
83 #define OPT_RDP_MASK (0xff << OPT_RDP_POS)
84 #define OPT_OPTCHANGEERR (1 << 30)
86 /* FLASH_OPTCCR register bits */
87 #define OPT_CLR_OPTCHANGEERR (1 << 30)
89 /* register unlock keys */
90 #define KEY1 0x45670123
91 #define KEY2 0xCDEF89AB
93 /* option register unlock key */
94 #define OPTKEY1 0x08192A3B
95 #define OPTKEY2 0x4C5D6E7F
97 #define DBGMCU_IDCODE_REGISTER 0x5C001000
98 #define FLASH_BANK0_ADDRESS 0x08000000
99 #define FLASH_BANK1_ADDRESS 0x08100000
100 #define FLASH_REG_BASE_B0 0x52002000
101 #define FLASH_REG_BASE_B1 0x52002100
103 /* Supported device IDs */
104 #define DEVID_STM32H74_H75XX 0x450
105 #define DEVID_STM32H7A_H7BXX 0x480
106 #define DEVID_STM32H72_H73XX 0x483
108 struct stm32h7x_rev {
113 /* stm32h7x_part_info permits the store each device information and specificities.
114 * the default unit is byte unless the suffix '_kb' is used. */
116 struct stm32h7x_part_info {
118 const char *device_str;
119 const struct stm32h7x_rev *revs;
121 unsigned int page_size_kb;
122 unsigned int block_size; /* flash write word size in bytes */
123 uint16_t max_flash_size_kb;
125 uint16_t max_bank_size_kb; /* Used when has_dual_bank is true */
126 uint32_t fsize_addr; /* Location of FSIZE register */
127 uint32_t wps_group_size; /* write protection group sectors' count */
129 /* function to compute flash_cr register values */
130 uint32_t (*compute_flash_cr)(uint32_t cmd, int snb);
133 struct stm32h7x_flash_bank {
136 uint32_t user_bank_size;
137 uint32_t flash_regs_base; /* Address of flash reg controller */
138 const struct stm32h7x_part_info *part_info;
141 enum stm32h7x_opt_rdp {
147 static const struct stm32h7x_rev stm32h74_h75xx_revs[] = {
148 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X" }, { 0x2003, "V" },
151 static const struct stm32h7x_rev stm32h7a_h7bxx_revs[] = {
155 static const struct stm32h7x_rev stm32h72_h73xx_revs[] = {
156 { 0x1000, "A" }, { 0x1001, "Z" },
159 static uint32_t stm32h74_h75xx_compute_flash_cr(uint32_t cmd, int snb)
161 return cmd | (snb << 8);
164 static uint32_t stm32h7a_h7bxx_compute_flash_cr(uint32_t cmd, int snb)
166 /* save FW and START bits, to be right shifted by 2 bits later */
167 const uint32_t tmp = cmd & (FLASH_FW | FLASH_START);
169 /* mask parallelism (ignored), FW and START bits */
170 cmd &= ~(FLASH_PSIZE_64 | FLASH_FW | FLASH_START);
172 return cmd | (tmp >> 2) | (snb << 6);
175 static const struct stm32h7x_part_info stm32h7x_parts[] = {
177 .id = DEVID_STM32H74_H75XX,
178 .revs = stm32h74_h75xx_revs,
179 .num_revs = ARRAY_SIZE(stm32h74_h75xx_revs),
180 .device_str = "STM32H74x/75x",
183 .max_flash_size_kb = 2048,
184 .max_bank_size_kb = 1024,
185 .has_dual_bank = true,
186 .fsize_addr = 0x1FF1E880,
189 .compute_flash_cr = stm32h74_h75xx_compute_flash_cr,
192 .id = DEVID_STM32H7A_H7BXX,
193 .revs = stm32h7a_h7bxx_revs,
194 .num_revs = ARRAY_SIZE(stm32h7a_h7bxx_revs),
195 .device_str = "STM32H7Ax/7Bx",
198 .max_flash_size_kb = 2048,
199 .max_bank_size_kb = 1024,
200 .has_dual_bank = true,
201 .fsize_addr = 0x08FFF80C,
203 .wps_mask = 0xFFFFFFFF,
204 .compute_flash_cr = stm32h7a_h7bxx_compute_flash_cr,
207 .id = DEVID_STM32H72_H73XX,
208 .revs = stm32h72_h73xx_revs,
209 .num_revs = ARRAY_SIZE(stm32h72_h73xx_revs),
210 .device_str = "STM32H72x/73x",
213 .max_flash_size_kb = 1024,
214 .max_bank_size_kb = 1024,
215 .has_dual_bank = false,
216 .fsize_addr = 0x1FF1E880,
219 .compute_flash_cr = stm32h74_h75xx_compute_flash_cr,
223 /* flash bank stm32x <base> <size> 0 0 <target#> */
225 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
227 struct stm32h7x_flash_bank *stm32x_info;
230 return ERROR_COMMAND_SYNTAX_ERROR;
232 stm32x_info = malloc(sizeof(struct stm32h7x_flash_bank));
233 bank->driver_priv = stm32x_info;
235 stm32x_info->probed = false;
236 stm32x_info->user_bank_size = bank->size;
241 static inline uint32_t stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
243 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
244 return reg_offset + stm32x_info->flash_regs_base;
247 static inline int stm32x_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
249 uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
250 int retval = target_read_u32(bank->target, reg_addr, value);
252 if (retval != ERROR_OK)
253 LOG_ERROR("error while reading from address 0x%" PRIx32, reg_addr);
258 static inline int stm32x_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
260 uint32_t reg_addr = stm32x_get_flash_reg(bank, reg_offset);
261 int retval = target_write_u32(bank->target, reg_addr, value);
263 if (retval != ERROR_OK)
264 LOG_ERROR("error while writing to address 0x%" PRIx32, reg_addr);
269 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
271 return stm32x_read_flash_reg(bank, FLASH_SR, status);
274 static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
279 /* wait for flash operations completion */
281 retval = stm32x_get_flash_status(bank, &status);
282 if (retval != ERROR_OK)
285 if ((status & FLASH_QW) == 0)
288 if (timeout-- <= 0) {
289 LOG_ERROR("wait_flash_op_queue, time out expired, status: 0x%" PRIx32, status);
295 if (status & FLASH_WRPERR) {
296 LOG_ERROR("wait_flash_op_queue, WRPERR detected");
300 /* Clear error + EOP flags but report errors */
301 if (status & FLASH_ERROR) {
302 if (retval == ERROR_OK)
304 /* If this operation fails, we ignore it and report the original retval */
305 stm32x_write_flash_reg(bank, FLASH_CCR, status);
310 static int stm32x_unlock_reg(struct flash_bank *bank)
314 /* first check if not already unlocked
315 * otherwise writing on FLASH_KEYR will fail
317 int retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
318 if (retval != ERROR_OK)
321 if ((ctrl & FLASH_LOCK) == 0)
324 /* unlock flash registers for bank */
325 retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY1);
326 if (retval != ERROR_OK)
329 retval = stm32x_write_flash_reg(bank, FLASH_KEYR, KEY2);
330 if (retval != ERROR_OK)
333 retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl);
334 if (retval != ERROR_OK)
337 if (ctrl & FLASH_LOCK) {
338 LOG_ERROR("flash not unlocked STM32_FLASH_CRx: 0x%" PRIx32, ctrl);
339 return ERROR_TARGET_FAILURE;
344 static int stm32x_unlock_option_reg(struct flash_bank *bank)
348 int retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
349 if (retval != ERROR_OK)
352 if ((ctrl & OPT_LOCK) == 0)
355 /* unlock option registers */
356 retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY1);
357 if (retval != ERROR_OK)
360 retval = stm32x_write_flash_reg(bank, FLASH_OPTKEYR, OPTKEY2);
361 if (retval != ERROR_OK)
364 retval = stm32x_read_flash_reg(bank, FLASH_OPTCR, &ctrl);
365 if (retval != ERROR_OK)
368 if (ctrl & OPT_LOCK) {
369 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: 0x%" PRIx32, ctrl);
370 return ERROR_TARGET_FAILURE;
376 static inline int stm32x_lock_reg(struct flash_bank *bank)
378 return stm32x_write_flash_reg(bank, FLASH_CR, FLASH_LOCK);
381 static inline int stm32x_lock_option_reg(struct flash_bank *bank)
383 return stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_LOCK);
386 static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
390 /* unlock option bytes for modification */
391 retval = stm32x_unlock_option_reg(bank);
392 if (retval != ERROR_OK)
393 goto flash_options_lock;
395 /* write option bytes */
396 retval = stm32x_write_flash_reg(bank, reg_offset, value);
397 if (retval != ERROR_OK)
398 goto flash_options_lock;
400 /* Remove OPT error flag before programming */
401 retval = stm32x_write_flash_reg(bank, FLASH_OPTCCR, OPT_CLR_OPTCHANGEERR);
402 if (retval != ERROR_OK)
403 goto flash_options_lock;
405 /* start programming cycle */
406 retval = stm32x_write_flash_reg(bank, FLASH_OPTCR, OPT_START);
407 if (retval != ERROR_OK)
408 goto flash_options_lock;
410 /* wait for completion */
411 int timeout = FLASH_ERASE_TIMEOUT;
414 retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_CUR, &status);
415 if (retval != ERROR_OK) {
416 LOG_ERROR("stm32x_options_program: failed to read FLASH_OPTSR_CUR");
417 goto flash_options_lock;
419 if ((status & OPT_BSY) == 0)
422 if (timeout-- <= 0) {
423 LOG_ERROR("waiting for OBL launch, time out expired, OPTSR: 0x%" PRIx32, status);
425 goto flash_options_lock;
430 /* check for failure */
431 if (status & OPT_OPTCHANGEERR) {
432 LOG_ERROR("error changing option bytes (OPTCHANGEERR=1)");
433 retval = ERROR_FLASH_OPERATION_FAILED;
437 retval2 = stm32x_lock_option_reg(bank);
438 if (retval2 != ERROR_OK)
439 LOG_ERROR("error during the lock of flash options");
441 return (retval == ERROR_OK) ? retval2 : retval;
444 static int stm32x_modify_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
448 int retval = stm32x_read_flash_reg(bank, reg_offset, &data);
449 if (retval != ERROR_OK)
452 data = (data & ~mask) | (value & mask);
454 return stm32x_write_option(bank, reg_offset, data);
457 static int stm32x_protect_check(struct flash_bank *bank)
461 /* read 'write protection' settings */
462 int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
463 if (retval != ERROR_OK) {
464 LOG_DEBUG("unable to read WPSN_CUR register");
468 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
469 bank->prot_blocks[i].is_protected = protection & (1 << i) ? 0 : 1;
474 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
477 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
480 assert(first < bank->num_sectors);
481 assert(last < bank->num_sectors);
483 if (bank->target->state != TARGET_HALTED)
484 return ERROR_TARGET_NOT_HALTED;
486 retval = stm32x_unlock_reg(bank);
487 if (retval != ERROR_OK)
492 To erase a sector, follow the procedure below:
493 1. Check that no Flash memory operation is ongoing by checking the QW bit in the
495 2. Set the SER bit and select the sector
496 you wish to erase (SNB) in the FLASH_CR register
497 3. Set the STRT bit in the FLASH_CR register
498 4. Wait for flash operations completion
500 for (unsigned int i = first; i <= last; i++) {
501 LOG_DEBUG("erase sector %u", i);
502 retval = stm32x_write_flash_reg(bank, FLASH_CR,
503 stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64, i));
504 if (retval != ERROR_OK) {
505 LOG_ERROR("Error erase sector %u", i);
508 retval = stm32x_write_flash_reg(bank, FLASH_CR,
509 stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64 | FLASH_START, i));
510 if (retval != ERROR_OK) {
511 LOG_ERROR("Error erase sector %u", i);
514 retval = stm32x_wait_flash_op_queue(bank, FLASH_ERASE_TIMEOUT);
516 if (retval != ERROR_OK) {
517 LOG_ERROR("erase time-out or operation error sector %u", i);
523 retval2 = stm32x_lock_reg(bank);
524 if (retval2 != ERROR_OK)
525 LOG_ERROR("error during the lock of flash");
527 return (retval == ERROR_OK) ? retval2 : retval;
530 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
533 struct target *target = bank->target;
536 if (target->state != TARGET_HALTED) {
537 LOG_ERROR("Target not halted");
538 return ERROR_TARGET_NOT_HALTED;
541 /* read 'write protection' settings */
542 int retval = stm32x_read_flash_reg(bank, FLASH_WPSN_CUR, &protection);
543 if (retval != ERROR_OK) {
544 LOG_DEBUG("unable to read WPSN_CUR register");
548 for (unsigned int i = first; i <= last; i++) {
550 protection &= ~(1 << i);
552 protection |= (1 << i);
555 /* apply WRPSN mask */
558 LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%" PRIx32, protection);
560 /* apply new option value */
561 return stm32x_write_option(bank, FLASH_WPSN_PRG, protection);
564 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
565 uint32_t offset, uint32_t count)
567 struct target *target = bank->target;
568 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
570 * If the size of the data part of the buffer is not a multiple of .block_size, we get
571 * "corrupted fifo read" pointer in target_run_flash_async_algorithm()
573 uint32_t data_size = 512 * stm32x_info->part_info->block_size;
574 uint32_t buffer_size = 8 + data_size;
575 struct working_area *write_algorithm;
576 struct working_area *source;
577 uint32_t address = bank->base + offset;
578 struct reg_param reg_params[6];
579 struct armv7m_algorithm armv7m_info;
580 int retval = ERROR_OK;
582 static const uint8_t stm32x_flash_write_code[] = {
583 #include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
586 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
587 &write_algorithm) != ERROR_OK) {
588 LOG_WARNING("no working area available, can't do block memory writes");
589 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
592 retval = target_write_buffer(target, write_algorithm->address,
593 sizeof(stm32x_flash_write_code),
594 stm32x_flash_write_code);
595 if (retval != ERROR_OK) {
596 target_free_working_area(target, write_algorithm);
601 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
603 buffer_size = 8 + data_size;
604 if (data_size <= 256) {
605 /* we already allocated the writing code, but failed to get a
606 * buffer, free the algorithm */
607 target_free_working_area(target, write_algorithm);
609 LOG_WARNING("no large enough working area available, can't do block memory writes");
610 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
614 LOG_DEBUG("target_alloc_working_area_try : buffer_size -> 0x%" PRIx32, buffer_size);
616 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
617 armv7m_info.core_mode = ARM_MODE_THREAD;
619 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
620 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
621 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
622 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count of words (word size = .block_size (bytes) */
623 init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* word size in bytes */
624 init_reg_param(®_params[5], "r5", 32, PARAM_OUT); /* flash reg base */
626 buf_set_u32(reg_params[0].value, 0, 32, source->address);
627 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
628 buf_set_u32(reg_params[2].value, 0, 32, address);
629 buf_set_u32(reg_params[3].value, 0, 32, count);
630 buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->part_info->block_size);
631 buf_set_u32(reg_params[5].value, 0, 32, stm32x_info->flash_regs_base);
633 retval = target_run_flash_async_algorithm(target,
636 stm32x_info->part_info->block_size,
638 ARRAY_SIZE(reg_params), reg_params,
639 source->address, source->size,
640 write_algorithm->address, 0,
643 if (retval == ERROR_FLASH_OPERATION_FAILED) {
644 LOG_ERROR("error executing stm32h7x flash write algorithm");
646 uint32_t flash_sr = buf_get_u32(reg_params[0].value, 0, 32);
648 if (flash_sr & FLASH_WRPERR)
649 LOG_ERROR("flash memory write protected");
651 if ((flash_sr & FLASH_ERROR) != 0) {
652 LOG_ERROR("flash write failed, FLASH_SR = 0x%08" PRIx32, flash_sr);
653 /* Clear error + EOP flags but report errors */
654 stm32x_write_flash_reg(bank, FLASH_CCR, flash_sr);
659 target_free_working_area(target, source);
660 target_free_working_area(target, write_algorithm);
662 destroy_reg_param(®_params[0]);
663 destroy_reg_param(®_params[1]);
664 destroy_reg_param(®_params[2]);
665 destroy_reg_param(®_params[3]);
666 destroy_reg_param(®_params[4]);
667 destroy_reg_param(®_params[5]);
671 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
672 uint32_t offset, uint32_t count)
674 struct target *target = bank->target;
675 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
676 uint32_t address = bank->base + offset;
679 if (bank->target->state != TARGET_HALTED) {
680 LOG_ERROR("Target not halted");
681 return ERROR_TARGET_NOT_HALTED;
684 /* should be enforced via bank->write_start_alignment */
685 assert(!(offset % stm32x_info->part_info->block_size));
687 /* should be enforced via bank->write_end_alignment */
688 assert(!(count % stm32x_info->part_info->block_size));
690 retval = stm32x_unlock_reg(bank);
691 if (retval != ERROR_OK)
694 uint32_t blocks_remaining = count / stm32x_info->part_info->block_size;
696 /* multiple words (n * .block_size) to be programmed in block */
697 if (blocks_remaining) {
698 retval = stm32x_write_block(bank, buffer, offset, blocks_remaining);
699 if (retval != ERROR_OK) {
700 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
701 /* if block write failed (no sufficient working area),
702 * we use normal (slow) dword accesses */
703 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
706 buffer += blocks_remaining * stm32x_info->part_info->block_size;
707 address += blocks_remaining * stm32x_info->part_info->block_size;
708 blocks_remaining = 0;
710 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
716 The Flash memory programming sequence is as follows:
717 1. Check that no main Flash memory operation is ongoing by checking the QW bit in the
719 2. Set the PG bit in the FLASH_CR register
720 3. 8 x Word access (or Force Write FW)
721 4. Wait for flash operations completion
723 while (blocks_remaining > 0) {
724 retval = stm32x_write_flash_reg(bank, FLASH_CR,
725 stm32x_info->part_info->compute_flash_cr(FLASH_PG | FLASH_PSIZE_64, 0));
726 if (retval != ERROR_OK)
729 retval = target_write_buffer(target, address, stm32x_info->part_info->block_size, buffer);
730 if (retval != ERROR_OK)
733 retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
734 if (retval != ERROR_OK)
737 buffer += stm32x_info->part_info->block_size;
738 address += stm32x_info->part_info->block_size;
743 retval2 = stm32x_lock_reg(bank);
744 if (retval2 != ERROR_OK)
745 LOG_ERROR("error during the lock of flash");
747 return (retval == ERROR_OK) ? retval2 : retval;
750 static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
752 /* read stm32 device id register */
753 int retval = target_read_u32(bank->target, DBGMCU_IDCODE_REGISTER, id);
754 if (retval != ERROR_OK)
759 static int stm32x_probe(struct flash_bank *bank)
761 struct target *target = bank->target;
762 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
763 uint16_t flash_size_in_kb;
766 stm32x_info->probed = false;
767 stm32x_info->part_info = NULL;
769 if (!target_was_examined(target)) {
770 LOG_ERROR("Target not examined yet");
771 return ERROR_TARGET_NOT_EXAMINED;
774 int retval = stm32x_read_id_code(bank, &stm32x_info->idcode);
775 if (retval != ERROR_OK)
778 LOG_DEBUG("device id = 0x%08" PRIx32, stm32x_info->idcode);
780 device_id = stm32x_info->idcode & 0xfff;
782 for (unsigned int n = 0; n < ARRAY_SIZE(stm32h7x_parts); n++) {
783 if (device_id == stm32h7x_parts[n].id)
784 stm32x_info->part_info = &stm32h7x_parts[n];
786 if (!stm32x_info->part_info) {
787 LOG_WARNING("Cannot identify target as a STM32H7xx family.");
790 LOG_INFO("Device: %s", stm32x_info->part_info->device_str);
793 /* update the address of controller */
794 if (bank->base == FLASH_BANK0_ADDRESS)
795 stm32x_info->flash_regs_base = FLASH_REG_BASE_B0;
796 else if (bank->base == FLASH_BANK1_ADDRESS)
797 stm32x_info->flash_regs_base = FLASH_REG_BASE_B1;
799 LOG_WARNING("Flash register base not defined for bank %u", bank->bank_number);
802 LOG_DEBUG("flash_regs_base: 0x%" PRIx32, stm32x_info->flash_regs_base);
804 /* get flash size from target */
805 /* STM32H74x/H75x, the second core (Cortex-M4) cannot read the flash size */
807 if (device_id == DEVID_STM32H74_H75XX
808 && cortex_m_get_partno_safe(target) == CORTEX_M4_PARTNO)
809 LOG_WARNING("%s cannot read the flash size register", target_name(target));
811 retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb);
813 if (retval != ERROR_OK) {
814 /* read error when device has invalid value, set max flash size */
815 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
816 LOG_INFO("assuming %" PRIu16 "k flash", flash_size_in_kb);
818 LOG_INFO("flash size probed value %" PRIu16 "k", flash_size_in_kb);
820 /* setup bank size */
821 const uint32_t bank1_base = FLASH_BANK0_ADDRESS;
822 const uint32_t bank2_base = bank1_base + stm32x_info->part_info->max_bank_size_kb * 1024;
823 bool has_dual_bank = stm32x_info->part_info->has_dual_bank;
826 case DEVID_STM32H74_H75XX:
827 case DEVID_STM32H7A_H7BXX:
828 /* For STM32H74x/75x and STM32H7Ax/Bx
829 * - STM32H7xxxI devices contains dual bank, 1 Mbyte each
830 * - STM32H7xxxG devices contains dual bank, 512 Kbyte each
831 * - STM32H7xxxB devices contains single bank, 128 Kbyte
832 * - the second bank starts always from 0x08100000
834 if (flash_size_in_kb == 128)
835 has_dual_bank = false;
837 /* flash size is 2M or 1M */
838 flash_size_in_kb /= 2;
840 case DEVID_STM32H72_H73XX:
843 LOG_ERROR("unsupported device");
848 LOG_INFO("STM32H7 flash has dual banks");
849 if (bank->base != bank1_base && bank->base != bank2_base) {
850 LOG_ERROR("STM32H7 flash bank base address config is incorrect. "
851 TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
852 bank->base, bank1_base, bank2_base);
856 LOG_INFO("STM32H7 flash has a single bank");
857 if (bank->base == bank2_base) {
858 LOG_ERROR("this device has a single bank only");
860 } else if (bank->base != bank1_base) {
861 LOG_ERROR("STM32H7 flash bank base address config is incorrect. "
862 TARGET_ADDR_FMT " but should be 0x%" PRIx32,
863 bank->base, bank1_base);
868 LOG_INFO("Bank (%u) size is %" PRIu16 " kb, base address is " TARGET_ADDR_FMT,
869 bank->bank_number, flash_size_in_kb, bank->base);
871 /* if the user sets the size manually then ignore the probed value
872 * this allows us to work around devices that have an invalid flash size register value */
873 if (stm32x_info->user_bank_size) {
874 LOG_INFO("ignoring flash probed value, using configured bank size");
875 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
876 } else if (flash_size_in_kb == 0xffff) {
878 flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
881 /* did we assign flash size? */
882 assert(flash_size_in_kb != 0xffff);
883 bank->size = flash_size_in_kb * 1024;
884 bank->write_start_alignment = stm32x_info->part_info->block_size;
885 bank->write_end_alignment = stm32x_info->part_info->block_size;
888 bank->num_sectors = flash_size_in_kb / stm32x_info->part_info->page_size_kb;
889 assert(bank->num_sectors > 0);
893 bank->sectors = alloc_block_array(0, stm32x_info->part_info->page_size_kb * 1024,
896 if (!bank->sectors) {
897 LOG_ERROR("failed to allocate bank sectors");
901 /* setup protection blocks */
902 const uint32_t wpsn = stm32x_info->part_info->wps_group_size;
903 assert(bank->num_sectors % wpsn == 0);
905 bank->num_prot_blocks = bank->num_sectors / wpsn;
906 assert(bank->num_prot_blocks > 0);
908 free(bank->prot_blocks);
910 bank->prot_blocks = alloc_block_array(0, stm32x_info->part_info->page_size_kb * wpsn * 1024,
911 bank->num_prot_blocks);
913 if (!bank->prot_blocks) {
914 LOG_ERROR("failed to allocate bank prot_block");
918 stm32x_info->probed = true;
922 static int stm32x_auto_probe(struct flash_bank *bank)
924 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
926 if (stm32x_info->probed)
929 return stm32x_probe(bank);
932 /* This method must return a string displaying information about the bank */
933 static int stm32x_get_info(struct flash_bank *bank, struct command_invocation *cmd)
935 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
936 const struct stm32h7x_part_info *info = stm32x_info->part_info;
938 if (!stm32x_info->probed) {
939 int retval = stm32x_probe(bank);
940 if (retval != ERROR_OK) {
941 command_print_sameline(cmd, "Unable to find bank information.");
947 const char *rev_str = NULL;
948 uint16_t rev_id = stm32x_info->idcode >> 16;
950 for (unsigned int i = 0; i < info->num_revs; i++)
951 if (rev_id == info->revs[i].rev)
952 rev_str = info->revs[i].str;
955 command_print_sameline(cmd, "%s - Rev: %s",
956 stm32x_info->part_info->device_str, rev_str);
958 command_print_sameline(cmd,
959 "%s - Rev: unknown (0x%04" PRIx16 ")",
960 stm32x_info->part_info->device_str, rev_id);
963 command_print_sameline(cmd, "Cannot identify target as a STM32H7x");
969 static int stm32x_set_rdp(struct flash_bank *bank, enum stm32h7x_opt_rdp new_rdp)
971 struct target *target = bank->target;
972 uint32_t optsr, cur_rdp;
975 if (target->state != TARGET_HALTED) {
976 LOG_ERROR("Target not halted");
977 return ERROR_TARGET_NOT_HALTED;
980 retval = stm32x_read_flash_reg(bank, FLASH_OPTSR_PRG, &optsr);
982 if (retval != ERROR_OK) {
983 LOG_DEBUG("unable to read FLASH_OPTSR_PRG register");
987 /* get current RDP, and check if there is a change */
988 cur_rdp = (optsr & OPT_RDP_MASK) >> OPT_RDP_POS;
989 if (new_rdp == cur_rdp) {
990 LOG_INFO("the requested RDP value is already programmed");
996 LOG_WARNING("unlocking the entire flash device");
999 LOG_WARNING("locking the entire flash device");
1002 LOG_WARNING("locking the entire flash device, irreversible");
1007 optsr = (optsr & ~OPT_RDP_MASK) | (new_rdp << OPT_RDP_POS);
1009 /* apply new option value */
1010 return stm32x_write_option(bank, FLASH_OPTSR_PRG, optsr);
1013 COMMAND_HANDLER(stm32x_handle_lock_command)
1016 return ERROR_COMMAND_SYNTAX_ERROR;
1018 struct flash_bank *bank;
1019 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1020 if (retval != ERROR_OK)
1023 retval = stm32x_set_rdp(bank, OPT_RDP_L1);
1025 if (retval != ERROR_OK)
1026 command_print(CMD, "%s failed to lock device", bank->driver->name);
1028 command_print(CMD, "%s locked", bank->driver->name);
1033 COMMAND_HANDLER(stm32x_handle_unlock_command)
1036 return ERROR_COMMAND_SYNTAX_ERROR;
1038 struct flash_bank *bank;
1039 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1040 if (retval != ERROR_OK)
1043 retval = stm32x_set_rdp(bank, OPT_RDP_L0);
1045 if (retval != ERROR_OK)
1046 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1048 command_print(CMD, "%s unlocked", bank->driver->name);
1053 static int stm32x_mass_erase(struct flash_bank *bank)
1055 int retval, retval2;
1056 struct target *target = bank->target;
1057 struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
1059 if (target->state != TARGET_HALTED) {
1060 LOG_ERROR("Target not halted");
1061 return ERROR_TARGET_NOT_HALTED;
1064 retval = stm32x_unlock_reg(bank);
1065 if (retval != ERROR_OK)
1068 /* mass erase flash memory bank */
1069 retval = stm32x_write_flash_reg(bank, FLASH_CR,
1070 stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64, 0));
1071 if (retval != ERROR_OK)
1074 retval = stm32x_write_flash_reg(bank, FLASH_CR,
1075 stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64 | FLASH_START, 0));
1076 if (retval != ERROR_OK)
1079 retval = stm32x_wait_flash_op_queue(bank, 30000);
1080 if (retval != ERROR_OK)
1084 retval2 = stm32x_lock_reg(bank);
1085 if (retval2 != ERROR_OK)
1086 LOG_ERROR("error during the lock of flash");
1088 return (retval == ERROR_OK) ? retval2 : retval;
1091 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1094 command_print(CMD, "stm32h7x mass_erase <bank>");
1095 return ERROR_COMMAND_SYNTAX_ERROR;
1098 struct flash_bank *bank;
1099 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1100 if (retval != ERROR_OK)
1103 retval = stm32x_mass_erase(bank);
1104 if (retval == ERROR_OK)
1105 command_print(CMD, "stm32h7x mass erase complete");
1107 command_print(CMD, "stm32h7x mass erase failed");
1112 COMMAND_HANDLER(stm32x_handle_option_read_command)
1115 command_print(CMD, "stm32h7x option_read <bank> <option_reg offset>");
1116 return ERROR_COMMAND_SYNTAX_ERROR;
1119 struct flash_bank *bank;
1120 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1121 if (retval != ERROR_OK)
1124 uint32_t reg_offset, value;
1126 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1127 retval = stm32x_read_flash_reg(bank, reg_offset, &value);
1128 if (retval != ERROR_OK)
1131 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32,
1132 stm32x_get_flash_reg(bank, reg_offset), value);
1137 COMMAND_HANDLER(stm32x_handle_option_write_command)
1140 command_print(CMD, "stm32h7x option_write <bank> <option_reg offset> <value> [mask]");
1141 return ERROR_COMMAND_SYNTAX_ERROR;
1144 struct flash_bank *bank;
1145 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1146 if (retval != ERROR_OK)
1149 uint32_t reg_offset, value, mask = 0xffffffff;
1151 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
1152 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1154 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
1156 return stm32x_modify_option(bank, reg_offset, value, mask);
1159 static const struct command_registration stm32h7x_exec_command_handlers[] = {
1162 .handler = stm32x_handle_lock_command,
1163 .mode = COMMAND_EXEC,
1165 .help = "Lock entire flash device.",
1169 .handler = stm32x_handle_unlock_command,
1170 .mode = COMMAND_EXEC,
1172 .help = "Unlock entire protected flash device.",
1175 .name = "mass_erase",
1176 .handler = stm32x_handle_mass_erase_command,
1177 .mode = COMMAND_EXEC,
1179 .help = "Erase entire flash device.",
1182 .name = "option_read",
1183 .handler = stm32x_handle_option_read_command,
1184 .mode = COMMAND_EXEC,
1185 .usage = "bank_id reg_offset",
1186 .help = "Read and display device option bytes.",
1189 .name = "option_write",
1190 .handler = stm32x_handle_option_write_command,
1191 .mode = COMMAND_EXEC,
1192 .usage = "bank_id reg_offset value [mask]",
1193 .help = "Write device option bit fields with provided value.",
1195 COMMAND_REGISTRATION_DONE
1198 static const struct command_registration stm32h7x_command_handlers[] = {
1201 .mode = COMMAND_ANY,
1202 .help = "stm32h7x flash command group",
1204 .chain = stm32h7x_exec_command_handlers,
1206 COMMAND_REGISTRATION_DONE
1209 const struct flash_driver stm32h7x_flash = {
1211 .commands = stm32h7x_command_handlers,
1212 .flash_bank_command = stm32x_flash_bank_command,
1213 .erase = stm32x_erase,
1214 .protect = stm32x_protect,
1215 .write = stm32x_write,
1216 .read = default_flash_read,
1217 .probe = stm32x_probe,
1218 .auto_probe = stm32x_auto_probe,
1219 .erase_check = default_flash_blank_check,
1220 .protect_check = stm32x_protect_check,
1221 .info = stm32x_get_info,
1222 .free_driver_priv = default_flash_free_driver_priv,