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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 Øyvind Harboe                                      *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "imp.h"
  30 #include <helper/binarybuffer.h>
  31 #include <target/algorithm.h>
  32 #include <target/armv7m.h>
  33
  34 /* Regarding performance:
  35  *
  36  * Short story - it might be best to leave the performance at
  37  * current levels.
  38  *
  39  * You may see a jump in speed if you change to using
  40  * 32bit words for the block programming.
  41  *
  42  * Its a shame you cannot use the double word as its
  43  * even faster - but you require external VPP for that mode.
  44  *
  45  * Having said all that 16bit writes give us the widest vdd
  46  * operating range, so may be worth adding a note to that effect.
  47  *
  48  */
  49
  50 /* Danger!!!! The STM32F1x and STM32F2x series actually have
  51  * quite different flash controllers.
  52  *
  53  * What's more scary is that the names of the registers and their
  54  * addresses are the same, but the actual bits and what they do are
  55  * can be very different.
  56  *
  57  * To reduce testing complexity and dangers of regressions,
  58  * a seperate file is used for stm32fx2x.
  59  *
  60  * Sector sizes in kiBytes:
  61  * 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
  62  * 1.5 MiByte part with 4 x 16, 1 x 64, 11 x 128.
  63  * 2 MiByte part with 4 x 16, 1 x 64, 7 x 128, 4 x 16, 1 x 64, 7 x 128.
  64  * 1 MiByte STM32F42x/43x part with DB1M Option set:
  65  *                    4 x 16, 1 x 64, 3 x 128, 4 x 16, 1 x 64, 3 x 128.
  66  *
  67  * STM32F7[2|3]
  68  * 512 kiByte part with 4 x 16, 1 x 64, 3 x 128.
  69  *
  70  * STM32F7[4|5]
  71  * 1 MiByte part with 4 x 32, 1 x 128, 3 x 256.
  72  *
  73  * STM32F7[6|7]
  74  * 1 MiByte part in single bank mode with 4 x 32, 1 x 128, 3 x 256.
  75  * 1 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 3 x 128 each.
  76  * 2 MiByte part in single-bank mode with 4 x 32, 1 x 128, 7 x 256.
  77  * 2 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 7 x 128 each.
  78  *
  79  * Protection size is sector size.
  80  *
  81  * Tested with STM3220F-EVAL board.
  82  *
  83  * STM32F4xx series for reference.
  84  *
  85  * RM0090
  86  * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00031020.pdf
  87  *
  88  * PM0059
  89  * www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/
  90  * PROGRAMMING_MANUAL/CD00233952.pdf
  91  *
  92  * STM32F7xx series for reference.
  93  *
  94  * RM0385
  95  * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00124865.pdf
  96  *
  97  * RM0410
  98  * http://www.st.com/resource/en/reference_manual/dm00224583.pdf
  99  *
 100  * RM0430
 101  * http://www.st.com/resource/en/reference_manual/dm00305666.pdf
 102  *
 103  * RM0431
 104  * http://www.st.com/resource/en/reference_manual/dm00305990.pdf
 105  *
 106  * STM32F1x series - notice that this code was copy, pasted and knocked
 107  * into a stm32f2x driver, so in case something has been converted or
 108  * bugs haven't been fixed, here are the original manuals:
 109  *
 110  * RM0008 - Reference manual
 111  *
 112  * RM0042, the Flash programming manual for low-, medium- high-density and
 113  * connectivity line STM32F10x devices
 114  *
 115  * PM0068, the Flash programming manual for XL-density STM32F10x devices.
 116  *
 117  */
 118
 119 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
 120 #define FLASH_ERASE_TIMEOUT 10000
 121 #define FLASH_WRITE_TIMEOUT 5
 122
 123 /* Mass erase time can be as high as 32 s in x8 mode. */
 124 #define FLASH_MASS_ERASE_TIMEOUT 33000
 125
 126 #define STM32_FLASH_BASE    0x40023c00
 127 #define STM32_FLASH_ACR     0x40023c00
 128 #define STM32_FLASH_KEYR    0x40023c04
 129 #define STM32_FLASH_OPTKEYR 0x40023c08
 130 #define STM32_FLASH_SR      0x40023c0C
 131 #define STM32_FLASH_CR      0x40023c10
 132 #define STM32_FLASH_OPTCR   0x40023c14
 133 #define STM32_FLASH_OPTCR1  0x40023c18
 134 #define STM32_FLASH_OPTCR2  0x40023c1c
 135
 136 /* FLASH_CR register bits */
 137 #define FLASH_PG       (1 << 0)
 138 #define FLASH_SER      (1 << 1)
 139 #define FLASH_MER      (1 << 2)         /* MER/MER1 for f76x/77x */
 140 #define FLASH_MER1     (1 << 15)        /* MER2 for f76x/77x, confusing ... */
 141 #define FLASH_STRT     (1 << 16)
 142 #define FLASH_PSIZE_8  (0 << 8)
 143 #define FLASH_PSIZE_16 (1 << 8)
 144 #define FLASH_PSIZE_32 (2 << 8)
 145 #define FLASH_PSIZE_64 (3 << 8)
 146 /* The sector number encoding is not straight binary for dual bank flash. */
 147 #define FLASH_SNB(a)   ((a) << 3)
 148 #define FLASH_LOCK     (1 << 31)
 149
 150 /* FLASH_SR register bits */
 151 #define FLASH_BSY      (1 << 16)
 152 #define FLASH_PGSERR   (1 << 7) /* Programming sequence error */
 153 #define FLASH_PGPERR   (1 << 6) /* Programming parallelism error */
 154 #define FLASH_PGAERR   (1 << 5) /* Programming alignment error */
 155 #define FLASH_WRPERR   (1 << 4) /* Write protection error */
 156 #define FLASH_OPERR    (1 << 1) /* Operation error */
 157
 158 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
 159
 160 /* STM32_FLASH_OPTCR register bits */
 161 #define OPTCR_LOCK     (1 << 0)
 162 #define OPTCR_START    (1 << 1)
 163 #define OPTCR_NDBANK   (1 << 29)        /* not dual bank mode */
 164 #define OPTCR_DB1M     (1 << 30)        /* 1 MiB devices dual flash bank option */
 165 #define OPTCR_SPRMOD   (1 << 31)        /* switches PCROPi/nWPRi interpretation */
 166
 167 /* STM32_FLASH_OPTCR2 register bits */
 168 #define OPTCR2_PCROP_RDP        (1 << 31)       /* erase PCROP zone when decreasing RDP */
 169
 170 /* register unlock keys */
 171 #define KEY1           0x45670123
 172 #define KEY2           0xCDEF89AB
 173
 174 /* option register unlock key */
 175 #define OPTKEY1        0x08192A3B
 176 #define OPTKEY2        0x4C5D6E7F
 177
 178 struct stm32x_options {
 179         uint8_t RDP;
 180         uint16_t user_options;  /* bit 0-7 usual options, bit 8-11 extra options */
 181         uint32_t protection;
 182         uint32_t boot_addr;
 183         uint32_t optcr2_pcrop;
 184 };
 185
 186 struct stm32x_flash_bank {
 187         struct stm32x_options option_bytes;
 188         int probed;
 189         bool has_large_mem;             /* F42x/43x/469/479/7xx in dual bank mode */
 190         bool has_extra_options; /* F42x/43x/469/479/7xx */
 191         bool has_boot_addr;     /* F7xx */
 192         bool has_optcr2_pcrop;  /* F72x/73x */
 193         int protection_bits;    /* F413/423 */
 194         uint32_t user_bank_size;
 195 };
 196
 197 /* flash bank stm32x <base> <size> 0 0 <target#>
 198  */
 199 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 200 {
 201         struct stm32x_flash_bank *stm32x_info;
 202
 203         if (CMD_ARGC < 6)
 204                 return ERROR_COMMAND_SYNTAX_ERROR;
 205
 206         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 207         bank->driver_priv = stm32x_info;
 208
 209         stm32x_info->probed = 0;
 210         stm32x_info->user_bank_size = bank->size;
 211
 212         return ERROR_OK;
 213 }
 214
 215 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 216 {
 217         return reg;
 218 }
 219
 220 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 221 {
 222         struct target *target = bank->target;
 223         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 224 }
 225
 226 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 227 {
 228         struct target *target = bank->target;
 229         uint32_t status;
 230         int retval = ERROR_OK;
 231
 232         /* wait for busy to clear */
 233         for (;;) {
 234                 retval = stm32x_get_flash_status(bank, &status);
 235                 if (retval != ERROR_OK)
 236                         return retval;
 237                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 238                 if ((status & FLASH_BSY) == 0)
 239                         break;
 240                 if (timeout-- <= 0) {
 241                         LOG_ERROR("timed out waiting for flash");
 242                         return ERROR_FAIL;
 243                 }
 244                 alive_sleep(1);
 245         }
 246
 247
 248         if (status & FLASH_WRPERR) {
 249                 LOG_ERROR("stm32x device protected");
 250                 retval = ERROR_FAIL;
 251         }
 252
 253         /* Clear but report errors */
 254         if (status & FLASH_ERROR) {
 255                 /* If this operation fails, we ignore it and report the original
 256                  * retval
 257                  */
 258                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 259                                 status & FLASH_ERROR);
 260         }
 261         return retval;
 262 }
 263
 264 static int stm32x_unlock_reg(struct target *target)
 265 {
 266         uint32_t ctrl;
 267
 268         /* first check if not already unlocked
 269          * otherwise writing on STM32_FLASH_KEYR will fail
 270          */
 271         int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
 272         if (retval != ERROR_OK)
 273                 return retval;
 274
 275         if ((ctrl & FLASH_LOCK) == 0)
 276                 return ERROR_OK;
 277
 278         /* unlock flash registers */
 279         retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 280         if (retval != ERROR_OK)
 281                 return retval;
 282
 283         retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 284         if (retval != ERROR_OK)
 285                 return retval;
 286
 287         retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
 288         if (retval != ERROR_OK)
 289                 return retval;
 290
 291         if (ctrl & FLASH_LOCK) {
 292                 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
 293                 return ERROR_TARGET_FAILURE;
 294         }
 295
 296         return ERROR_OK;
 297 }
 298
 299 static int stm32x_unlock_option_reg(struct target *target)
 300 {
 301         uint32_t ctrl;
 302
 303         int retval = target_read_u32(target, STM32_FLASH_OPTCR, &ctrl);
 304         if (retval != ERROR_OK)
 305                 return retval;
 306
 307         if ((ctrl & OPTCR_LOCK) == 0)
 308                 return ERROR_OK;
 309
 310         /* unlock option registers */
 311         retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY1);
 312         if (retval != ERROR_OK)
 313                 return retval;
 314
 315         retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY2);
 316         if (retval != ERROR_OK)
 317                 return retval;
 318
 319         retval = target_read_u32(target, STM32_FLASH_OPTCR, &ctrl);
 320         if (retval != ERROR_OK)
 321                 return retval;
 322
 323         if (ctrl & OPTCR_LOCK) {
 324                 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
 325                 return ERROR_TARGET_FAILURE;
 326         }
 327
 328         return ERROR_OK;
 329 }
 330
 331 static int stm32x_read_options(struct flash_bank *bank)
 332 {
 333         uint32_t optiondata;
 334         struct stm32x_flash_bank *stm32x_info = NULL;
 335         struct target *target = bank->target;
 336
 337         stm32x_info = bank->driver_priv;
 338
 339         /* read current option bytes */
 340         int retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
 341         if (retval != ERROR_OK)
 342                 return retval;
 343
 344     /* caution: F2 implements 5 bits (WDG_SW only)
 345      * whereas F7 6 bits (IWDG_SW and WWDG_SW) in user_options */
 346         stm32x_info->option_bytes.user_options = optiondata & 0xfc;
 347         stm32x_info->option_bytes.RDP = (optiondata >> 8) & 0xff;
 348         stm32x_info->option_bytes.protection =
 349                 (optiondata >> 16) & (~(0xffff << stm32x_info->protection_bits) & 0xffff);
 350
 351         if (stm32x_info->has_extra_options) {
 352                 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
 353                 stm32x_info->option_bytes.user_options |= (optiondata >> 20) &
 354                         ((0xf00 << (stm32x_info->protection_bits - 12)) & 0xf00);
 355         }
 356
 357         if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
 358                 retval = target_read_u32(target, STM32_FLASH_OPTCR1, &optiondata);
 359                 if (retval != ERROR_OK)
 360                         return retval;
 361
 362                 /* FLASH_OPTCR1 has quite diffent meanings ... */
 363                 if (stm32x_info->has_boot_addr) {
 364                         /* for F7xx it contains boot0 and boot1 */
 365                         stm32x_info->option_bytes.boot_addr = optiondata;
 366                 } else {
 367                         /* for F42x/43x/469/479 it contains 12 additional protection bits */
 368                         stm32x_info->option_bytes.protection |= (optiondata >> 4) & 0x00fff000;
 369                 }
 370         }
 371
 372         if (stm32x_info->has_optcr2_pcrop) {
 373                 retval = target_read_u32(target, STM32_FLASH_OPTCR2, &optiondata);
 374                 if (retval != ERROR_OK)
 375                         return retval;
 376
 377                 stm32x_info->option_bytes.optcr2_pcrop = optiondata;
 378                 if (stm32x_info->has_optcr2_pcrop &&
 379                         (stm32x_info->option_bytes.optcr2_pcrop & ~OPTCR2_PCROP_RDP)) {
 380                         LOG_INFO("PCROP Engaged");
 381                 }
 382         } else {
 383                 stm32x_info->option_bytes.optcr2_pcrop = 0x0;
 384         }
 385
 386         if (stm32x_info->option_bytes.RDP != 0xAA)
 387                 LOG_INFO("Device Security Bit Set");
 388
 389         return ERROR_OK;
 390 }
 391
 392 static int stm32x_write_options(struct flash_bank *bank)
 393 {
 394         struct stm32x_flash_bank *stm32x_info = NULL;
 395         struct target *target = bank->target;
 396         uint32_t optiondata, optiondata2;
 397
 398         stm32x_info = bank->driver_priv;
 399
 400         int retval = stm32x_unlock_option_reg(target);
 401         if (retval != ERROR_OK)
 402                 return retval;
 403
 404         /* rebuild option data */
 405         optiondata = stm32x_info->option_bytes.user_options & 0xfc;
 406         optiondata |= stm32x_info->option_bytes.RDP << 8;
 407         optiondata |= (stm32x_info->option_bytes.protection &
 408                 (~(0xffff << stm32x_info->protection_bits))) << 16;
 409
 410         if (stm32x_info->has_extra_options) {
 411                 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
 412                 optiondata |= (stm32x_info->option_bytes.user_options &
 413                         ((0xf00 << (stm32x_info->protection_bits - 12)) & 0xf00)) << 20;
 414         }
 415
 416         if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
 417                 if (stm32x_info->has_boot_addr) {
 418                         /* F7xx uses FLASH_OPTCR1 for boot0 and boot1 ... */
 419                         optiondata2 = stm32x_info->option_bytes.boot_addr;
 420                 } else {
 421                         /* F42x/43x/469/479 uses FLASH_OPTCR1 for additional protection bits */
 422                         optiondata2 = (stm32x_info->option_bytes.protection & 0x00fff000) << 4;
 423                 }
 424
 425                 retval = target_write_u32(target, STM32_FLASH_OPTCR1, optiondata2);
 426                 if (retval != ERROR_OK)
 427                         return retval;
 428         }
 429
 430         /* program extra pcrop register */
 431         if (stm32x_info->has_optcr2_pcrop) {
 432                 retval = target_write_u32(target, STM32_FLASH_OPTCR2,
 433                         stm32x_info->option_bytes.optcr2_pcrop);
 434                 if (retval != ERROR_OK)
 435                         return retval;
 436         }
 437
 438         /* program options */
 439         retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata);
 440         if (retval != ERROR_OK)
 441                 return retval;
 442
 443         /* start programming cycle */
 444         retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPTCR_START);
 445         if (retval != ERROR_OK)
 446                 return retval;
 447
 448         /* wait for completion, this might trigger a security erase and take a while */
 449         retval = stm32x_wait_status_busy(bank, FLASH_MASS_ERASE_TIMEOUT);
 450         if (retval != ERROR_OK)
 451                 return retval;
 452
 453         /* relock registers */
 454         retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPTCR_LOCK);
 455         if (retval != ERROR_OK)
 456                 return retval;
 457
 458         return ERROR_OK;
 459 }
 460
 461 static int stm32x_protect_check(struct flash_bank *bank)
 462 {
 463         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 464         struct flash_sector *prot_blocks;
 465         int num_prot_blocks;
 466
 467         /* read write protection settings */
 468         int retval = stm32x_read_options(bank);
 469         if (retval != ERROR_OK) {
 470                 LOG_DEBUG("unable to read option bytes");
 471                 return retval;
 472         }
 473
 474         if (bank->prot_blocks) {
 475                 num_prot_blocks = bank->num_prot_blocks;
 476                 prot_blocks = bank->prot_blocks;
 477         } else {
 478                 num_prot_blocks = bank->num_sectors;
 479                 prot_blocks = bank->sectors;
 480         }
 481
 482         for (int i = 0; i < num_prot_blocks; i++)
 483                 prot_blocks[i].is_protected =
 484                         ~(stm32x_info->option_bytes.protection >> i) & 1;
 485
 486         return ERROR_OK;
 487 }
 488
 489 static int stm32x_erase(struct flash_bank *bank, int first, int last)
 490 {
 491         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 492         struct target *target = bank->target;
 493         int i;
 494
 495         assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
 496
 497         if (bank->target->state != TARGET_HALTED) {
 498                 LOG_ERROR("Target not halted");
 499                 return ERROR_TARGET_NOT_HALTED;
 500         }
 501
 502         int retval;
 503         retval = stm32x_unlock_reg(target);
 504         if (retval != ERROR_OK)
 505                 return retval;
 506
 507         /*
 508         Sector Erase
 509         To erase a sector, follow the procedure below:
 510         1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
 511           FLASH_SR register
 512         2. Set the SER bit and select the sector
 513           you wish to erase (SNB) in the FLASH_CR register
 514         3. Set the STRT bit in the FLASH_CR register
 515         4. Wait for the BSY bit to be cleared
 516          */
 517
 518         for (i = first; i <= last; i++) {
 519                 int snb;
 520                 if (stm32x_info->has_large_mem && i >= 12)
 521                         snb = (i - 12) | 0x10;
 522                 else
 523                         snb = i;
 524
 525                 retval = target_write_u32(target,
 526                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_SER | FLASH_SNB(snb) | FLASH_STRT);
 527                 if (retval != ERROR_OK)
 528                         return retval;
 529
 530                 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 531                 if (retval != ERROR_OK)
 532                         return retval;
 533
 534                 bank->sectors[i].is_erased = 1;
 535         }
 536
 537         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 538         if (retval != ERROR_OK)
 539                 return retval;
 540
 541         return ERROR_OK;
 542 }
 543
 544 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
 545 {
 546         struct target *target = bank->target;
 547         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 548
 549         if (target->state != TARGET_HALTED) {
 550                 LOG_ERROR("Target not halted");
 551                 return ERROR_TARGET_NOT_HALTED;
 552         }
 553
 554         /* read protection settings */
 555         int retval = stm32x_read_options(bank);
 556         if (retval != ERROR_OK) {
 557                 LOG_DEBUG("unable to read option bytes");
 558                 return retval;
 559         }
 560
 561         for (int i = first; i <= last; i++) {
 562                 if (set)
 563                         stm32x_info->option_bytes.protection &= ~(1 << i);
 564                 else
 565                         stm32x_info->option_bytes.protection |= (1 << i);
 566         }
 567
 568         retval = stm32x_write_options(bank);
 569         if (retval != ERROR_OK)
 570                 return retval;
 571
 572         return ERROR_OK;
 573 }
 574
 575 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 576                 uint32_t offset, uint32_t count)
 577 {
 578         struct target *target = bank->target;
 579         uint32_t buffer_size = 16384;
 580         struct working_area *write_algorithm;
 581         struct working_area *source;
 582         uint32_t address = bank->base + offset;
 583         struct reg_param reg_params[5];
 584         struct armv7m_algorithm armv7m_info;
 585         int retval = ERROR_OK;
 586
 587         static const uint8_t stm32x_flash_write_code[] = {
 588 #include "../../../contrib/loaders/flash/stm32/stm32f2x.inc"
 589         };
 590
 591         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 592                         &write_algorithm) != ERROR_OK) {
 593                 LOG_WARNING("no working area available, can't do block memory writes");
 594                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 595         }
 596
 597         retval = target_write_buffer(target, write_algorithm->address,
 598                         sizeof(stm32x_flash_write_code),
 599                         stm32x_flash_write_code);
 600         if (retval != ERROR_OK)
 601                 return retval;
 602
 603         /* memory buffer */
 604         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 605                 buffer_size /= 2;
 606                 if (buffer_size <= 256) {
 607                         /* we already allocated the writing code, but failed to get a
 608                          * buffer, free the algorithm */
 609                         target_free_working_area(target, write_algorithm);
 610
 611                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 612                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 613                 }
 614         }
 615
 616         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 617         armv7m_info.core_mode = ARM_MODE_THREAD;
 618
 619         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);         /* buffer start, status (out) */
 620         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);            /* buffer end */
 621         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);            /* target address */
 622         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);            /* count (halfword-16bit) */
 623         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);            /* flash base */
 624
 625         buf_set_u32(reg_params[0].value, 0, 32, source->address);
 626         buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
 627         buf_set_u32(reg_params[2].value, 0, 32, address);
 628         buf_set_u32(reg_params[3].value, 0, 32, count);
 629         buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
 630
 631         retval = target_run_flash_async_algorithm(target, buffer, count, 2,
 632                         0, NULL,
 633                         5, reg_params,
 634                         source->address, source->size,
 635                         write_algorithm->address, 0,
 636                         &armv7m_info);
 637
 638         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 639                 LOG_ERROR("error executing stm32x flash write algorithm");
 640
 641                 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
 642
 643                 if (error & FLASH_WRPERR)
 644                         LOG_ERROR("flash memory write protected");
 645
 646                 if (error != 0) {
 647                         LOG_ERROR("flash write failed = %08" PRIx32, error);
 648                         /* Clear but report errors */
 649                         target_write_u32(target, STM32_FLASH_SR, error);
 650                         retval = ERROR_FAIL;
 651                 }
 652         }
 653
 654         target_free_working_area(target, source);
 655         target_free_working_area(target, write_algorithm);
 656
 657         destroy_reg_param(&reg_params[0]);
 658         destroy_reg_param(&reg_params[1]);
 659         destroy_reg_param(&reg_params[2]);
 660         destroy_reg_param(&reg_params[3]);
 661         destroy_reg_param(&reg_params[4]);
 662
 663         return retval;
 664 }
 665
 666 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 667                 uint32_t offset, uint32_t count)
 668 {
 669         struct target *target = bank->target;
 670         uint32_t words_remaining = (count / 2);
 671         uint32_t bytes_remaining = (count & 0x00000001);
 672         uint32_t address = bank->base + offset;
 673         uint32_t bytes_written = 0;
 674         int retval;
 675
 676         if (bank->target->state != TARGET_HALTED) {
 677                 LOG_ERROR("Target not halted");
 678                 return ERROR_TARGET_NOT_HALTED;
 679         }
 680
 681         if (offset & 0x1) {
 682                 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 683                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 684         }
 685
 686         retval = stm32x_unlock_reg(target);
 687         if (retval != ERROR_OK)
 688                 return retval;
 689
 690         /* multiple half words (2-byte) to be programmed? */
 691         if (words_remaining > 0) {
 692                 /* try using a block write */
 693                 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
 694                 if (retval != ERROR_OK) {
 695                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 696                                 /* if block write failed (no sufficient working area),
 697                                  * we use normal (slow) single dword accesses */
 698                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 699                         }
 700                 } else {
 701                         buffer += words_remaining * 2;
 702                         address += words_remaining * 2;
 703                         words_remaining = 0;
 704                 }
 705         }
 706
 707         if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
 708                 return retval;
 709
 710         /*
 711         Standard programming
 712         The Flash memory programming sequence is as follows:
 713         1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
 714           FLASH_SR register.
 715         2. Set the PG bit in the FLASH_CR register
 716         3. Perform the data write operation(s) to the desired memory address (inside main
 717           memory block or OTP area):
 718         – – Half-word access in case of x16 parallelism
 719         – Word access in case of x32 parallelism
 720         –
 721         4.
 722         Byte access in case of x8 parallelism
 723         Double word access in case of x64 parallelism
 724         Wait for the BSY bit to be cleared
 725         */
 726         while (words_remaining > 0) {
 727                 uint16_t value;
 728                 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
 729
 730                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
 731                                 FLASH_PG | FLASH_PSIZE_16);
 732                 if (retval != ERROR_OK)
 733                         return retval;
 734
 735                 retval = target_write_u16(target, address, value);
 736                 if (retval != ERROR_OK)
 737                         return retval;
 738
 739                 retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
 740                 if (retval != ERROR_OK)
 741                         return retval;
 742
 743                 bytes_written += 2;
 744                 words_remaining--;
 745                 address += 2;
 746         }
 747
 748         if (bytes_remaining) {
 749                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
 750                                 FLASH_PG | FLASH_PSIZE_8);
 751                 if (retval != ERROR_OK)
 752                         return retval;
 753                 retval = target_write_u8(target, address, buffer[bytes_written]);
 754                 if (retval != ERROR_OK)
 755                         return retval;
 756
 757                 retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
 758                 if (retval != ERROR_OK)
 759                         return retval;
 760         }
 761
 762         return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 763 }
 764
 765 static int setup_sector(struct flash_bank *bank, int start, int num, int size)
 766 {
 767
 768         for (int i = start; i < (start + num) ; i++) {
 769                 assert(i < bank->num_sectors);
 770                 bank->sectors[i].offset = bank->size;
 771                 bank->sectors[i].size = size;
 772                 bank->size += bank->sectors[i].size;
 773             LOG_DEBUG("sector %d: %dkBytes", i, size >> 10);
 774         }
 775
 776         return start + num;
 777 }
 778
 779 static void setup_bank(struct flash_bank *bank, int start,
 780         uint16_t flash_size_in_kb, uint16_t max_sector_size_in_kb)
 781 {
 782         int remain;
 783
 784         start = setup_sector(bank, start, 4, (max_sector_size_in_kb / 8) * 1024);
 785         start = setup_sector(bank, start, 1, (max_sector_size_in_kb / 2) * 1024);
 786
 787         /* remaining sectors all of size max_sector_size_in_kb */
 788         remain = (flash_size_in_kb / max_sector_size_in_kb) - 1;
 789         start = setup_sector(bank, start, remain, max_sector_size_in_kb * 1024);
 790 }
 791
 792 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 793 {
 794         /* this checks for a stm32f4x errata issue where a
 795          * stm32f2x DBGMCU_IDCODE is incorrectly returned.
 796          * If the issue is detected target is forced to stm32f4x Rev A.
 797          * Only effects Rev A silicon */
 798
 799         struct target *target = bank->target;
 800         uint32_t cpuid;
 801
 802         /* read stm32 device id register */
 803         int retval = target_read_u32(target, 0xE0042000, device_id);
 804         if (retval != ERROR_OK)
 805                 return retval;
 806
 807         if ((*device_id & 0xfff) == 0x411) {
 808                 /* read CPUID reg to check core type */
 809                 retval = target_read_u32(target, 0xE000ED00, &cpuid);
 810                 if (retval != ERROR_OK)
 811                         return retval;
 812
 813                 /* check for cortex_m4 */
 814                 if (((cpuid >> 4) & 0xFFF) == 0xC24) {
 815                         *device_id &= ~((0xFFFF << 16) | 0xfff);
 816                         *device_id |= (0x1000 << 16) | 0x413;
 817                         LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
 818                 }
 819         }
 820         return retval;
 821 }
 822
 823 static int stm32x_probe(struct flash_bank *bank)
 824 {
 825         struct target *target = bank->target;
 826         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 827         int i, num_prot_blocks;
 828         uint16_t flash_size_in_kb;
 829         uint32_t flash_size_reg = 0x1FFF7A22;
 830         uint16_t max_sector_size_in_kb = 128;
 831         uint16_t max_flash_size_in_kb;
 832         uint32_t device_id;
 833         uint32_t base_address = 0x08000000;
 834
 835         stm32x_info->probed = 0;
 836         stm32x_info->has_large_mem = false;
 837         stm32x_info->has_boot_addr = false;
 838         stm32x_info->has_extra_options = false;
 839         stm32x_info->has_optcr2_pcrop = false;
 840         stm32x_info->protection_bits = 12;              /* max. number of nWRPi bits (in FLASH_OPTCR !!!) */
 841         num_prot_blocks = 0;
 842
 843         if (bank->sectors) {
 844                 free(bank->sectors);
 845                 bank->num_sectors = 0;
 846                 bank->sectors = NULL;
 847         }
 848
 849         if (bank->prot_blocks) {
 850                 free(bank->prot_blocks);
 851                 bank->num_prot_blocks = 0;
 852                 bank->prot_blocks = NULL;
 853         }
 854
 855         /* read stm32 device id register */
 856         int retval = stm32x_get_device_id(bank, &device_id);
 857         if (retval != ERROR_OK)
 858                 return retval;
 859         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 860         device_id &= 0xfff;             /* only bits 0-11 are used further on */
 861
 862         /* set max flash size depending on family, id taken from AN2606 */
 863         switch (device_id) {
 864         case 0x411: /* F20x/21x */
 865         case 0x413: /* F40x/41x */
 866                 max_flash_size_in_kb = 1024;
 867                 break;
 868
 869         case 0x419: /* F42x/43x */
 870         case 0x434: /* F469/479 */
 871                 stm32x_info->has_extra_options = true;
 872                 max_flash_size_in_kb = 2048;
 873                 break;
 874
 875         case 0x423:     /* F401xB/C */
 876                 max_flash_size_in_kb = 256;
 877                 break;
 878
 879         case 0x421:     /* F446 */
 880         case 0x431: /* F411 */
 881         case 0x433: /* F401xD/E */
 882         case 0x441: /* F412 */
 883                 max_flash_size_in_kb = 512;
 884                 break;
 885
 886         case 0x458: /* F410 */
 887                 max_flash_size_in_kb = 128;
 888                 break;
 889
 890         case 0x449:     /* F74x/75x */
 891                 max_flash_size_in_kb = 1024;
 892                 max_sector_size_in_kb = 256;
 893                 flash_size_reg = 0x1FF0F442;
 894                 stm32x_info->has_extra_options = true;
 895                 stm32x_info->has_boot_addr = true;
 896                 break;
 897
 898         case 0x451:     /* F76x/77x */
 899                 max_flash_size_in_kb = 2048;
 900                 max_sector_size_in_kb = 256;
 901                 flash_size_reg = 0x1FF0F442;
 902                 stm32x_info->has_extra_options = true;
 903                 stm32x_info->has_boot_addr = true;
 904                 break;
 905
 906         case 0x452:     /* F72x/73x */
 907                 max_flash_size_in_kb = 512;
 908                 flash_size_reg = 0x1FF07A22;    /* yes, 0x1FF*0*7A22, not 0x1FF*F*7A22 */
 909                 stm32x_info->has_extra_options = true;
 910                 stm32x_info->has_boot_addr = true;
 911                 stm32x_info->has_optcr2_pcrop = true;
 912                 break;
 913
 914         case 0x463:     /* F413x/423x */
 915                 max_flash_size_in_kb = 1536;
 916                 stm32x_info->has_extra_options = true;
 917                 stm32x_info->protection_bits = 15;
 918                 num_prot_blocks = 15;
 919                 break;
 920
 921         default:
 922                 LOG_WARNING("Cannot identify target as a STM32 family.");
 923                 return ERROR_FAIL;
 924         }
 925
 926         /* get flash size from target. */
 927         retval = target_read_u16(target, flash_size_reg, &flash_size_in_kb);
 928
 929         /* failed reading flash size or flash size invalid (early silicon),
 930          * default to max target family */
 931         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 932                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 933                         max_flash_size_in_kb);
 934                 flash_size_in_kb = max_flash_size_in_kb;
 935         }
 936
 937         /* if the user sets the size manually then ignore the probed value
 938          * this allows us to work around devices that have a invalid flash size register value */
 939         if (stm32x_info->user_bank_size) {
 940                 LOG_INFO("ignoring flash probed value, using configured bank size");
 941                 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
 942         }
 943
 944         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 945
 946         /* did we assign flash size? */
 947         assert(flash_size_in_kb != 0xffff);
 948
 949         /* F42x/43x/469/479 1024 kiByte devices have a dual bank option */
 950         if ((device_id == 0x419) || (device_id == 0x434)) {
 951                 uint32_t optiondata;
 952                 retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
 953                 if (retval != ERROR_OK) {
 954                         LOG_DEBUG("unable to read option bytes");
 955                         return retval;
 956                 }
 957                 if ((flash_size_in_kb > 1024) || (optiondata & OPTCR_DB1M)) {
 958                         stm32x_info->has_large_mem = true;
 959                         LOG_INFO("Dual Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
 960                 } else {
 961                         stm32x_info->has_large_mem = false;
 962                         LOG_INFO("Single Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
 963                 }
 964         }
 965
 966         /* F76x/77x devices have a dual bank option */
 967         if (device_id == 0x451) {
 968                 uint32_t optiondata;
 969                 retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
 970                 if (retval != ERROR_OK) {
 971                         LOG_DEBUG("unable to read option bytes");
 972                         return retval;
 973                 }
 974                 if (optiondata & OPTCR_NDBANK) {
 975                         stm32x_info->has_large_mem = false;
 976                         LOG_INFO("Single Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
 977                 } else {
 978                         stm32x_info->has_large_mem = true;
 979                         max_sector_size_in_kb >>= 1; /* sector size divided by 2 in dual-bank mode */
 980                         LOG_INFO("Dual Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
 981                 }
 982         }
 983
 984         /* calculate numbers of pages */
 985         int num_pages = flash_size_in_kb / max_sector_size_in_kb
 986                 + (stm32x_info->has_large_mem ? 8 : 4);
 987
 988         bank->base = base_address;
 989         bank->num_sectors = num_pages;
 990         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
 991         for (i = 0; i < num_pages; i++) {
 992                 bank->sectors[i].is_erased = -1;
 993                 bank->sectors[i].is_protected = 0;
 994         }
 995         bank->size = 0;
 996         LOG_DEBUG("allocated %d sectors", num_pages);
 997
 998         /* F76x/77x in dual bank mode */
 999         if ((device_id == 0x451) && stm32x_info->has_large_mem)
1000                 num_prot_blocks = num_pages >> 1;
1001
1002         if (num_prot_blocks) {
1003                 bank->prot_blocks = malloc(sizeof(struct flash_sector) * num_prot_blocks);
1004                 for (i = 0; i < num_prot_blocks; i++)
1005                         bank->prot_blocks[i].is_protected = 0;
1006                 LOG_DEBUG("allocated %d prot blocks", num_prot_blocks);
1007         }
1008
1009         if (stm32x_info->has_large_mem) {
1010                 /* dual-bank */
1011                 setup_bank(bank, 0, flash_size_in_kb >> 1, max_sector_size_in_kb);
1012                 setup_bank(bank, num_pages >> 1, flash_size_in_kb >> 1,
1013                         max_sector_size_in_kb);
1014
1015                 /* F767x/F77x in dual mode, one protection bit refers to two adjacent sectors */
1016                 if (device_id == 0x451) {
1017                         for (i = 0; i < num_prot_blocks; i++) {
1018                                 bank->prot_blocks[i].offset = bank->sectors[i << 1].offset;
1019                                 bank->prot_blocks[i].size = bank->sectors[i << 1].size
1020                                                 + bank->sectors[(i << 1) + 1].size;
1021                         }
1022                 }
1023         } else {
1024                 /* single-bank */
1025                 setup_bank(bank, 0, flash_size_in_kb, max_sector_size_in_kb);
1026
1027                 /* F413/F423, sectors 14 and 15 share one common protection bit */
1028                 if (device_id == 0x463) {
1029                         for (i = 0; i < num_prot_blocks; i++) {
1030                                 bank->prot_blocks[i].offset = bank->sectors[i].offset;
1031                                 bank->prot_blocks[i].size = bank->sectors[i].size;
1032                         }
1033                         bank->prot_blocks[num_prot_blocks - 1].size <<= 1;
1034                 }
1035         }
1036         bank->num_prot_blocks = num_prot_blocks;
1037         assert((bank->size >> 10) == flash_size_in_kb);
1038
1039         stm32x_info->probed = 1;
1040         return ERROR_OK;
1041 }
1042
1043 static int stm32x_auto_probe(struct flash_bank *bank)
1044 {
1045         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1046         if (stm32x_info->probed)
1047                 return ERROR_OK;
1048         return stm32x_probe(bank);
1049 }
1050
1051 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1052 {
1053         uint32_t dbgmcu_idcode;
1054
1055         /* read stm32 device id register */
1056         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1057         if (retval != ERROR_OK)
1058                 return retval;
1059
1060         uint16_t device_id = dbgmcu_idcode & 0xfff;
1061         uint16_t rev_id = dbgmcu_idcode >> 16;
1062         const char *device_str;
1063         const char *rev_str = NULL;
1064
1065         switch (device_id) {
1066         case 0x411:
1067                 device_str = "STM32F2xx";
1068
1069                 switch (rev_id) {
1070                 case 0x1000:
1071                         rev_str = "A";
1072                         break;
1073
1074                 case 0x2000:
1075                         rev_str = "B";
1076                         break;
1077
1078                 case 0x1001:
1079                         rev_str = "Z";
1080                         break;
1081
1082                 case 0x2001:
1083                         rev_str = "Y";
1084                         break;
1085
1086                 case 0x2003:
1087                         rev_str = "X";
1088                         break;
1089
1090                 case 0x2007:
1091                         rev_str = "1";
1092                         break;
1093
1094                 case 0x200F:
1095                         rev_str = "V";
1096                         break;
1097
1098                 case 0x201F:
1099                         rev_str = "2";
1100                         break;
1101                 }
1102                 break;
1103
1104         case 0x413:
1105         case 0x419:
1106         case 0x434:
1107                 device_str = "STM32F4xx";
1108
1109                 switch (rev_id) {
1110                 case 0x1000:
1111                         rev_str = "A";
1112                         break;
1113
1114                 case 0x1001:
1115                         rev_str = "Z";
1116                         break;
1117
1118                 case 0x1003:
1119                         rev_str = "Y";
1120                         break;
1121
1122                 case 0x1007:
1123                         rev_str = "1";
1124                         break;
1125
1126                 case 0x2001:
1127                         rev_str = "3";
1128                         break;
1129                 }
1130                 break;
1131
1132         case 0x421:
1133                 device_str = "STM32F446";
1134
1135                 switch (rev_id) {
1136                 case 0x1000:
1137                         rev_str = "A";
1138                         break;
1139                 }
1140                 break;
1141
1142         case 0x423:
1143         case 0x431:
1144         case 0x433:
1145         case 0x458:
1146         case 0x441:
1147                 device_str = "STM32F4xx (Low Power)";
1148
1149                 switch (rev_id) {
1150                 case 0x1000:
1151                         rev_str = "A";
1152                         break;
1153
1154                 case 0x1001:
1155                         rev_str = "Z";
1156                         break;
1157
1158                 case 0x2000:
1159                         rev_str = "B";
1160                         break;
1161
1162                 case 0x3000:
1163                         rev_str = "C";
1164                         break;
1165                 }
1166                 break;
1167
1168         case 0x449:
1169                 device_str = "STM32F7[4|5]x";
1170
1171                 switch (rev_id) {
1172                 case 0x1000:
1173                         rev_str = "A";
1174                         break;
1175
1176                 case 0x1001:
1177                         rev_str = "Z";
1178                         break;
1179                 }
1180                 break;
1181
1182         case 0x451:
1183                 device_str = "STM32F7[6|7]x";
1184
1185                 switch (rev_id) {
1186                 case 0x1000:
1187                         rev_str = "A";
1188                         break;
1189                 }
1190                 break;
1191
1192         case 0x452:
1193                 device_str = "STM32F7[2|3]x";
1194
1195                 switch (rev_id) {
1196                 case 0x1000:
1197                         rev_str = "A";
1198                         break;
1199                 }
1200                 break;
1201
1202         case 0x463:
1203                 device_str = "STM32F4[1|2]3";
1204
1205                 switch (rev_id) {
1206                 case 0x1000:
1207                         rev_str = "A";
1208                         break;
1209                 }
1210                 break;
1211
1212         default:
1213                 snprintf(buf, buf_size, "Cannot identify target as a STM32F2/4/7\n");
1214                 return ERROR_FAIL;
1215         }
1216
1217         if (rev_str != NULL)
1218                 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1219         else
1220                 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1221
1222         return ERROR_OK;
1223 }
1224
1225 COMMAND_HANDLER(stm32x_handle_lock_command)
1226 {
1227         struct target *target = NULL;
1228         struct stm32x_flash_bank *stm32x_info = NULL;
1229
1230         if (CMD_ARGC < 1)
1231                 return ERROR_COMMAND_SYNTAX_ERROR;
1232
1233         struct flash_bank *bank;
1234         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1235         if (ERROR_OK != retval)
1236                 return retval;
1237
1238         stm32x_info = bank->driver_priv;
1239         target = bank->target;
1240
1241         if (target->state != TARGET_HALTED) {
1242                 LOG_INFO("Target not halted");
1243                 /* return ERROR_TARGET_NOT_HALTED; */
1244         }
1245
1246         if (stm32x_read_options(bank) != ERROR_OK) {
1247                 command_print(CMD_CTX, "%s failed to read options", bank->driver->name);
1248                 return ERROR_OK;
1249         }
1250
1251         /* set readout protection */
1252         stm32x_info->option_bytes.RDP = 0;
1253
1254         if (stm32x_write_options(bank) != ERROR_OK) {
1255                 command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
1256                 return ERROR_OK;
1257         }
1258
1259         command_print(CMD_CTX, "%s locked", bank->driver->name);
1260
1261         return ERROR_OK;
1262 }
1263
1264 COMMAND_HANDLER(stm32x_handle_unlock_command)
1265 {
1266         struct target *target = NULL;
1267         struct stm32x_flash_bank *stm32x_info = NULL;
1268
1269         if (CMD_ARGC < 1)
1270                 return ERROR_COMMAND_SYNTAX_ERROR;
1271
1272         struct flash_bank *bank;
1273         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1274         if (ERROR_OK != retval)
1275                 return retval;
1276
1277         stm32x_info = bank->driver_priv;
1278         target = bank->target;
1279
1280         if (target->state != TARGET_HALTED) {
1281                 LOG_INFO("Target not halted");
1282                 /* return ERROR_TARGET_NOT_HALTED; */
1283         }
1284
1285         if (stm32x_read_options(bank) != ERROR_OK) {
1286                 command_print(CMD_CTX, "%s failed to read options", bank->driver->name);
1287                 return ERROR_OK;
1288         }
1289
1290         /* clear readout protection and complementary option bytes
1291          * this will also force a device unlock if set */
1292         stm32x_info->option_bytes.RDP = 0xAA;
1293         if (stm32x_info->has_optcr2_pcrop) {
1294                 stm32x_info->option_bytes.optcr2_pcrop = OPTCR2_PCROP_RDP | (~1U << bank->num_sectors);
1295         }
1296
1297         if (stm32x_write_options(bank) != ERROR_OK) {
1298                 command_print(CMD_CTX, "%s failed to unlock device", bank->driver->name);
1299                 return ERROR_OK;
1300         }
1301
1302         command_print(CMD_CTX, "%s unlocked.\n"
1303                         "INFO: a reset or power cycle is required "
1304                         "for the new settings to take effect.", bank->driver->name);
1305
1306         return ERROR_OK;
1307 }
1308
1309 static int stm32x_mass_erase(struct flash_bank *bank)
1310 {
1311         int retval;
1312         uint32_t flash_mer;
1313         struct target *target = bank->target;
1314         struct stm32x_flash_bank *stm32x_info = NULL;
1315
1316         if (target->state != TARGET_HALTED) {
1317                 LOG_ERROR("Target not halted");
1318                 return ERROR_TARGET_NOT_HALTED;
1319         }
1320
1321         stm32x_info = bank->driver_priv;
1322
1323         retval = stm32x_unlock_reg(target);
1324         if (retval != ERROR_OK)
1325                 return retval;
1326
1327         /* mass erase flash memory */
1328         if (stm32x_info->has_large_mem)
1329                 flash_mer = FLASH_MER | FLASH_MER1;
1330         else
1331                 flash_mer = FLASH_MER;
1332
1333         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), flash_mer);
1334         if (retval != ERROR_OK)
1335                 return retval;
1336         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1337                 flash_mer | FLASH_STRT);
1338         if (retval != ERROR_OK)
1339                 return retval;
1340
1341         retval = stm32x_wait_status_busy(bank, FLASH_MASS_ERASE_TIMEOUT);
1342         if (retval != ERROR_OK)
1343                 return retval;
1344
1345         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1346         if (retval != ERROR_OK)
1347                 return retval;
1348
1349         return ERROR_OK;
1350 }
1351
1352 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1353 {
1354         int i;
1355
1356         if (CMD_ARGC < 1) {
1357                 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1358                 return ERROR_COMMAND_SYNTAX_ERROR;
1359         }
1360
1361         struct flash_bank *bank;
1362         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1363         if (ERROR_OK != retval)
1364                 return retval;
1365
1366         retval = stm32x_mass_erase(bank);
1367         if (retval == ERROR_OK) {
1368                 /* set all sectors as erased */
1369                 for (i = 0; i < bank->num_sectors; i++)
1370                         bank->sectors[i].is_erased = 1;
1371
1372                 command_print(CMD_CTX, "stm32x mass erase complete");
1373         } else {
1374                 command_print(CMD_CTX, "stm32x mass erase failed");
1375         }
1376
1377         return retval;
1378 }
1379
1380 COMMAND_HANDLER(stm32f2x_handle_options_read_command)
1381 {
1382         int retval;
1383         struct flash_bank *bank;
1384         struct stm32x_flash_bank *stm32x_info = NULL;
1385
1386         if (CMD_ARGC != 1) {
1387                 command_print(CMD_CTX, "stm32f2x options_read <bank>");
1388                 return ERROR_COMMAND_SYNTAX_ERROR;
1389         }
1390
1391         retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1392         if (ERROR_OK != retval)
1393                 return retval;
1394
1395         retval = stm32x_read_options(bank);
1396         if (ERROR_OK != retval)
1397                 return retval;
1398
1399         stm32x_info = bank->driver_priv;
1400         if (stm32x_info->has_extra_options) {
1401                 if (stm32x_info->has_boot_addr) {
1402                         uint32_t boot_addr = stm32x_info->option_bytes.boot_addr;
1403
1404                         command_print(CMD_CTX, "stm32f2x user_options 0x%03X,"
1405                                 " boot_add0 0x%04X, boot_add1 0x%04X",
1406                                 stm32x_info->option_bytes.user_options,
1407                                 boot_addr & 0xffff, (boot_addr & 0xffff0000) >> 16);
1408                         if (stm32x_info->has_optcr2_pcrop) {
1409                                 command_print(CMD_CTX, "stm32f2x optcr2_pcrop 0x%08X",
1410                                                 stm32x_info->option_bytes.optcr2_pcrop);
1411                         }
1412                 } else {
1413                         command_print(CMD_CTX, "stm32f2x user_options 0x%03X",
1414                                 stm32x_info->option_bytes.user_options);
1415                 }
1416         } else {
1417                 command_print(CMD_CTX, "stm32f2x user_options 0x%02X",
1418                         stm32x_info->option_bytes.user_options);
1419
1420         }
1421
1422         return retval;
1423 }
1424
1425 COMMAND_HANDLER(stm32f2x_handle_options_write_command)
1426 {
1427         int retval;
1428         struct flash_bank *bank;
1429         struct stm32x_flash_bank *stm32x_info = NULL;
1430         uint16_t user_options, boot_addr0, boot_addr1, options_mask;
1431
1432         if (CMD_ARGC < 1) {
1433                 command_print(CMD_CTX, "stm32f2x options_write <bank> ...");
1434                 return ERROR_COMMAND_SYNTAX_ERROR;
1435         }
1436
1437         retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1438         if (ERROR_OK != retval)
1439                 return retval;
1440
1441         retval = stm32x_read_options(bank);
1442         if (ERROR_OK != retval)
1443                 return retval;
1444
1445         stm32x_info = bank->driver_priv;
1446         if (stm32x_info->has_boot_addr) {
1447                 if (CMD_ARGC != 4) {
1448                         command_print(CMD_CTX, "stm32f2x options_write <bank> <user_options>"
1449                                 " <boot_addr0> <boot_addr1>");
1450                         return ERROR_COMMAND_SYNTAX_ERROR;
1451                 }
1452                 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[2], boot_addr0);
1453                 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], boot_addr1);
1454                 stm32x_info->option_bytes.boot_addr = boot_addr0 | (((uint32_t) boot_addr1) << 16);
1455         } else {
1456                 if (CMD_ARGC != 2) {
1457                         command_print(CMD_CTX, "stm32f2x options_write <bank> <user_options>");
1458                         return ERROR_COMMAND_SYNTAX_ERROR;
1459                 }
1460         }
1461
1462         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], user_options);
1463         options_mask = !stm32x_info->has_extra_options ? ~0xfc :
1464                 ~(((0xf00 << (stm32x_info->protection_bits - 12)) | 0xff) & 0xffc);
1465         if (user_options & options_mask) {
1466                 command_print(CMD_CTX, "stm32f2x invalid user_options");
1467                 return ERROR_COMMAND_ARGUMENT_INVALID;
1468         }
1469
1470         stm32x_info->option_bytes.user_options = user_options;
1471
1472         if (stm32x_write_options(bank) != ERROR_OK) {
1473                 command_print(CMD_CTX, "stm32f2x failed to write options");
1474                 return ERROR_OK;
1475         }
1476
1477         /* switching between single- and dual-bank modes requires re-probe */
1478         /* ... and reprogramming of whole flash */
1479         stm32x_info->probed = 0;
1480
1481         command_print(CMD_CTX, "stm32f2x write options complete.\n"
1482                                 "INFO: a reset or power cycle is required "
1483                                 "for the new settings to take effect.");
1484         return retval;
1485 }
1486
1487 COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command)
1488 {
1489         int retval;
1490         struct flash_bank *bank;
1491         struct stm32x_flash_bank *stm32x_info = NULL;
1492         uint32_t optcr2_pcrop;
1493
1494         if (CMD_ARGC != 2) {
1495                 command_print(CMD_CTX, "stm32f2x optcr2_write <bank> <optcr2_value>");
1496                 return ERROR_COMMAND_SYNTAX_ERROR;
1497         }
1498
1499         retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1500         if (ERROR_OK != retval)
1501                 return retval;
1502
1503         stm32x_info = bank->driver_priv;
1504         if (!stm32x_info->has_optcr2_pcrop) {
1505                 command_print(CMD_CTX, "no optcr2 register");
1506                 return ERROR_COMMAND_ARGUMENT_INVALID;
1507         }
1508
1509         command_print(CMD_CTX, "INFO: To disable PCROP, set PCROP_RDP"
1510                                 " with PCROPi bits STILL SET, then\nlock device and"
1511                                 " finally unlock it. Clears PCROP and mass erases flash.");
1512
1513         retval = stm32x_read_options(bank);
1514         if (ERROR_OK != retval)
1515                 return retval;
1516
1517         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], optcr2_pcrop);
1518         stm32x_info->option_bytes.optcr2_pcrop = optcr2_pcrop;
1519
1520         if (stm32x_write_options(bank) != ERROR_OK) {
1521                 command_print(CMD_CTX, "stm32f2x failed to write options");
1522                 return ERROR_OK;
1523         }
1524
1525         command_print(CMD_CTX, "stm32f2x optcr2_write complete.");
1526         return retval;
1527 }
1528
1529 static const struct command_registration stm32x_exec_command_handlers[] = {
1530         {
1531                 .name = "lock",
1532                 .handler = stm32x_handle_lock_command,
1533                 .mode = COMMAND_EXEC,
1534                 .usage = "bank_id",
1535                 .help = "Lock entire flash device.",
1536         },
1537         {
1538                 .name = "unlock",
1539                 .handler = stm32x_handle_unlock_command,
1540                 .mode = COMMAND_EXEC,
1541                 .usage = "bank_id",
1542                 .help = "Unlock entire protected flash device.",
1543         },
1544         {
1545                 .name = "mass_erase",
1546                 .handler = stm32x_handle_mass_erase_command,
1547                 .mode = COMMAND_EXEC,
1548                 .usage = "bank_id",
1549                 .help = "Erase entire flash device.",
1550         },
1551         {
1552                 .name = "options_read",
1553                 .handler = stm32f2x_handle_options_read_command,
1554                 .mode = COMMAND_EXEC,
1555                 .usage = "bank_id",
1556                 .help = "Read and display device option bytes.",
1557         },
1558         {
1559                 .name = "options_write",
1560                 .handler = stm32f2x_handle_options_write_command,
1561                 .mode = COMMAND_EXEC,
1562                 .usage = "bank_id user_options [ boot_add0 boot_add1 ]",
1563                 .help = "Write option bytes",
1564         },
1565         {
1566                 .name = "optcr2_write",
1567                 .handler = stm32f2x_handle_optcr2_write_command,
1568                 .mode = COMMAND_EXEC,
1569                 .usage = "bank_id optcr2",
1570                 .help = "Write optcr2 word",
1571         },
1572
1573         COMMAND_REGISTRATION_DONE
1574 };
1575
1576 static const struct command_registration stm32x_command_handlers[] = {
1577         {
1578                 .name = "stm32f2x",
1579                 .mode = COMMAND_ANY,
1580                 .help = "stm32f2x flash command group",
1581                 .usage = "",
1582                 .chain = stm32x_exec_command_handlers,
1583         },
1584         COMMAND_REGISTRATION_DONE
1585 };
1586
1587 struct flash_driver stm32f2x_flash = {
1588         .name = "stm32f2x",
1589         .commands = stm32x_command_handlers,
1590         .flash_bank_command = stm32x_flash_bank_command,
1591         .erase = stm32x_erase,
1592         .protect = stm32x_protect,
1593         .write = stm32x_write,
1594         .read = default_flash_read,
1595         .probe = stm32x_probe,
1596         .auto_probe = stm32x_auto_probe,
1597         .erase_check = default_flash_blank_check,
1598         .protect_check = stm32x_protect_check,
1599         .info = get_stm32x_info,
1600         .free_driver_priv = default_flash_free_driver_priv,
1601 };